1 /* SPDX-License-Identifier: GPL-2.0-only OR MI <<
2 /* 1 /*
3 * Device Tree constants for the Texas Instrum 2 * Device Tree constants for the Texas Instruments DP83867 PHY
4 * 3 *
5 * Author: Dan Murphy <dmurphy@ti.com> 4 * Author: Dan Murphy <dmurphy@ti.com>
6 * 5 *
7 * Copyright (C) 2015-2024 Texas Instruments I !! 6 * Copyright: (C) 2015 Texas Instruments, Inc.
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License version 2 as
>> 10 * published by the Free Software Foundation.
>> 11 *
>> 12 * This program is distributed in the hope that it will be useful, but
>> 13 * WITHOUT ANY WARRANTY; without even the implied warranty of
>> 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> 15 * General Public License for more details.
8 */ 16 */
9 17
10 #ifndef _DT_BINDINGS_TI_DP83867_H 18 #ifndef _DT_BINDINGS_TI_DP83867_H
11 #define _DT_BINDINGS_TI_DP83867_H 19 #define _DT_BINDINGS_TI_DP83867_H
12 20
13 /* PHY CTRL bits */ 21 /* PHY CTRL bits */
14 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 22 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
15 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 23 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
16 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 24 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
17 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 25 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
18 26
19 /* RGMIIDCTL internal delay for rx and tx */ 27 /* RGMIIDCTL internal delay for rx and tx */
20 #define DP83867_RGMIIDCTL_250_PS 0x0 28 #define DP83867_RGMIIDCTL_250_PS 0x0
21 #define DP83867_RGMIIDCTL_500_PS 0x1 29 #define DP83867_RGMIIDCTL_500_PS 0x1
22 #define DP83867_RGMIIDCTL_750_PS 0x2 30 #define DP83867_RGMIIDCTL_750_PS 0x2
23 #define DP83867_RGMIIDCTL_1_NS 0x3 31 #define DP83867_RGMIIDCTL_1_NS 0x3
24 #define DP83867_RGMIIDCTL_1_25_NS 0x4 32 #define DP83867_RGMIIDCTL_1_25_NS 0x4
25 #define DP83867_RGMIIDCTL_1_50_NS 0x5 33 #define DP83867_RGMIIDCTL_1_50_NS 0x5
26 #define DP83867_RGMIIDCTL_1_75_NS 0x6 34 #define DP83867_RGMIIDCTL_1_75_NS 0x6
27 #define DP83867_RGMIIDCTL_2_00_NS 0x7 35 #define DP83867_RGMIIDCTL_2_00_NS 0x7
28 #define DP83867_RGMIIDCTL_2_25_NS 0x8 36 #define DP83867_RGMIIDCTL_2_25_NS 0x8
29 #define DP83867_RGMIIDCTL_2_50_NS 0x9 37 #define DP83867_RGMIIDCTL_2_50_NS 0x9
30 #define DP83867_RGMIIDCTL_2_75_NS 0xa 38 #define DP83867_RGMIIDCTL_2_75_NS 0xa
31 #define DP83867_RGMIIDCTL_3_00_NS 0xb 39 #define DP83867_RGMIIDCTL_3_00_NS 0xb
32 #define DP83867_RGMIIDCTL_3_25_NS 0xc 40 #define DP83867_RGMIIDCTL_3_25_NS 0xc
33 #define DP83867_RGMIIDCTL_3_50_NS 0xd 41 #define DP83867_RGMIIDCTL_3_50_NS 0xd
34 #define DP83867_RGMIIDCTL_3_75_NS 0xe 42 #define DP83867_RGMIIDCTL_3_75_NS 0xe
35 #define DP83867_RGMIIDCTL_4_00_NS 0xf 43 #define DP83867_RGMIIDCTL_4_00_NS 0xf
36 44
37 /* IO_MUX_CFG - Clock output selection */ <<
38 #define DP83867_CLK_O_SEL_CHN_A_RCLK <<
39 #define DP83867_CLK_O_SEL_CHN_B_RCLK <<
40 #define DP83867_CLK_O_SEL_CHN_C_RCLK <<
41 #define DP83867_CLK_O_SEL_CHN_D_RCLK <<
42 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 <<
43 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 <<
44 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 <<
45 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 <<
46 #define DP83867_CLK_O_SEL_CHN_A_TCLK <<
47 #define DP83867_CLK_O_SEL_CHN_B_TCLK <<
48 #define DP83867_CLK_O_SEL_CHN_C_TCLK <<
49 #define DP83867_CLK_O_SEL_CHN_D_TCLK <<
50 #define DP83867_CLK_O_SEL_REF_CLK <<
51 /* Special flag to indicate clock should be of <<
52 #define DP83867_CLK_O_SEL_OFF <<
53 #endif 45 #endif
54 46
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