1 /* SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Device Tree constants for the Texas Instrum 3 * Device Tree constants for the Texas Instruments DP83867 PHY 4 * 4 * 5 * Author: Dan Murphy <dmurphy@ti.com> 5 * Author: Dan Murphy <dmurphy@ti.com> 6 * 6 * 7 * Copyright (C) 2015-2024 Texas Instruments I !! 7 * Copyright: (C) 2015 Texas Instruments, Inc. 8 */ 8 */ 9 9 10 #ifndef _DT_BINDINGS_TI_DP83867_H 10 #ifndef _DT_BINDINGS_TI_DP83867_H 11 #define _DT_BINDINGS_TI_DP83867_H 11 #define _DT_BINDINGS_TI_DP83867_H 12 12 13 /* PHY CTRL bits */ 13 /* PHY CTRL bits */ 14 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 14 #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 15 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 15 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 16 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 16 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 17 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 17 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 18 18 19 /* RGMIIDCTL internal delay for rx and tx */ 19 /* RGMIIDCTL internal delay for rx and tx */ 20 #define DP83867_RGMIIDCTL_250_PS 0x0 20 #define DP83867_RGMIIDCTL_250_PS 0x0 21 #define DP83867_RGMIIDCTL_500_PS 0x1 21 #define DP83867_RGMIIDCTL_500_PS 0x1 22 #define DP83867_RGMIIDCTL_750_PS 0x2 22 #define DP83867_RGMIIDCTL_750_PS 0x2 23 #define DP83867_RGMIIDCTL_1_NS 0x3 23 #define DP83867_RGMIIDCTL_1_NS 0x3 24 #define DP83867_RGMIIDCTL_1_25_NS 0x4 24 #define DP83867_RGMIIDCTL_1_25_NS 0x4 25 #define DP83867_RGMIIDCTL_1_50_NS 0x5 25 #define DP83867_RGMIIDCTL_1_50_NS 0x5 26 #define DP83867_RGMIIDCTL_1_75_NS 0x6 26 #define DP83867_RGMIIDCTL_1_75_NS 0x6 27 #define DP83867_RGMIIDCTL_2_00_NS 0x7 27 #define DP83867_RGMIIDCTL_2_00_NS 0x7 28 #define DP83867_RGMIIDCTL_2_25_NS 0x8 28 #define DP83867_RGMIIDCTL_2_25_NS 0x8 29 #define DP83867_RGMIIDCTL_2_50_NS 0x9 29 #define DP83867_RGMIIDCTL_2_50_NS 0x9 30 #define DP83867_RGMIIDCTL_2_75_NS 0xa 30 #define DP83867_RGMIIDCTL_2_75_NS 0xa 31 #define DP83867_RGMIIDCTL_3_00_NS 0xb 31 #define DP83867_RGMIIDCTL_3_00_NS 0xb 32 #define DP83867_RGMIIDCTL_3_25_NS 0xc 32 #define DP83867_RGMIIDCTL_3_25_NS 0xc 33 #define DP83867_RGMIIDCTL_3_50_NS 0xd 33 #define DP83867_RGMIIDCTL_3_50_NS 0xd 34 #define DP83867_RGMIIDCTL_3_75_NS 0xe 34 #define DP83867_RGMIIDCTL_3_75_NS 0xe 35 #define DP83867_RGMIIDCTL_4_00_NS 0xf 35 #define DP83867_RGMIIDCTL_4_00_NS 0xf 36 36 37 /* IO_MUX_CFG - Clock output selection */ 37 /* IO_MUX_CFG - Clock output selection */ 38 #define DP83867_CLK_O_SEL_CHN_A_RCLK 38 #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 39 #define DP83867_CLK_O_SEL_CHN_B_RCLK 39 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 40 #define DP83867_CLK_O_SEL_CHN_C_RCLK 40 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 41 #define DP83867_CLK_O_SEL_CHN_D_RCLK 41 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 42 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 42 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 43 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 43 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 44 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 44 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 45 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 45 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 46 #define DP83867_CLK_O_SEL_CHN_A_TCLK 46 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 47 #define DP83867_CLK_O_SEL_CHN_B_TCLK 47 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 48 #define DP83867_CLK_O_SEL_CHN_C_TCLK 48 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 49 #define DP83867_CLK_O_SEL_CHN_D_TCLK 49 #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 50 #define DP83867_CLK_O_SEL_REF_CLK 50 #define DP83867_CLK_O_SEL_REF_CLK 0xC 51 /* Special flag to indicate clock should be of << 52 #define DP83867_CLK_O_SEL_OFF << 53 #endif 51 #endif 54 52
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