1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 2 /* 3 * Copyright 2019~2020 NXP 4 */ 5 6 #ifndef _IMX8DXL_PADS_H 7 #define _IMX8DXL_PADS_H 8 9 /* pin id */ 10 #define IMX8DXL_PCIE_CTRL0_PERST_B 11 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B 12 #define IMX8DXL_PCIE_CTRL0_WAKE_B 13 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 14 #define IMX8DXL_USB_SS3_TC0 15 #define IMX8DXL_USB_SS3_TC1 16 #define IMX8DXL_USB_SS3_TC2 17 #define IMX8DXL_USB_SS3_TC3 18 #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 19 #define IMX8DXL_EMMC0_CLK 20 #define IMX8DXL_EMMC0_CMD 21 #define IMX8DXL_EMMC0_DATA0 22 #define IMX8DXL_EMMC0_DATA1 23 #define IMX8DXL_EMMC0_DATA2 24 #define IMX8DXL_EMMC0_DATA3 25 #define IMX8DXL_EMMC0_DATA4 26 #define IMX8DXL_EMMC0_DATA5 27 #define IMX8DXL_EMMC0_DATA6 28 #define IMX8DXL_EMMC0_DATA7 29 #define IMX8DXL_EMMC0_STROBE 30 #define IMX8DXL_EMMC0_RESET_B 31 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 32 #define IMX8DXL_USDHC1_RESET_B 33 #define IMX8DXL_USDHC1_VSELECT 34 #define IMX8DXL_CTL_NAND_RE_P_N 35 #define IMX8DXL_USDHC1_WP 36 #define IMX8DXL_USDHC1_CD_B 37 #define IMX8DXL_CTL_NAND_DQS_P_N 38 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 39 #define IMX8DXL_ENET0_RGMII_TXC 40 #define IMX8DXL_ENET0_RGMII_TX_CTL 41 #define IMX8DXL_ENET0_RGMII_TXD0 42 #define IMX8DXL_ENET0_RGMII_TXD1 43 #define IMX8DXL_ENET0_RGMII_TXD2 44 #define IMX8DXL_ENET0_RGMII_TXD3 45 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENE 46 #define IMX8DXL_ENET0_RGMII_RXC 47 #define IMX8DXL_ENET0_RGMII_RX_CTL 48 #define IMX8DXL_ENET0_RGMII_RXD0 49 #define IMX8DXL_ENET0_RGMII_RXD1 50 #define IMX8DXL_ENET0_RGMII_RXD2 51 #define IMX8DXL_ENET0_RGMII_RXD3 52 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENE 53 #define IMX8DXL_ENET0_REFCLK_125M_25M 54 #define IMX8DXL_ENET0_MDIO 55 #define IMX8DXL_ENET0_MDC 56 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 57 #define IMX8DXL_ENET1_RGMII_TXC 58 #define IMX8DXL_ENET1_RGMII_TXD2 59 #define IMX8DXL_ENET1_RGMII_TX_CTL 60 #define IMX8DXL_ENET1_RGMII_TXD3 61 #define IMX8DXL_ENET1_RGMII_RXC 62 #define IMX8DXL_ENET1_RGMII_RXD3 63 #define IMX8DXL_ENET1_RGMII_RXD2 64 #define IMX8DXL_ENET1_RGMII_RXD1 65 #define IMX8DXL_ENET1_RGMII_TXD0 66 #define IMX8DXL_ENET1_RGMII_TXD1 67 #define IMX8DXL_ENET1_RGMII_RXD0 68 #define IMX8DXL_ENET1_RGMII_RX_CTL 69 #define IMX8DXL_ENET1_REFCLK_125M_25M 70 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 71 #define IMX8DXL_SPI3_SCK 72 #define IMX8DXL_SPI3_SDO 73 #define IMX8DXL_SPI3_SDI 74 #define IMX8DXL_SPI3_CS0 75 #define IMX8DXL_SPI3_CS1 76 #define IMX8DXL_MCLK_IN1 77 #define IMX8DXL_MCLK_IN0 78 #define IMX8DXL_MCLK_OUT0 79 #define IMX8DXL_UART1_TX 80 #define IMX8DXL_UART1_RX 81 #define IMX8DXL_UART1_RTS_B 82 #define IMX8DXL_UART1_CTS_B 83 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 84 #define IMX8DXL_SPI0_SCK 85 #define IMX8DXL_SPI0_SDI 86 #define IMX8DXL_SPI0_SDO 87 #define IMX8DXL_SPI0_CS1 88 #define IMX8DXL_SPI0_CS0 89 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 90 #define IMX8DXL_ADC_IN1 91 #define IMX8DXL_ADC_IN0 92 #define IMX8DXL_ADC_IN3 93 #define IMX8DXL_ADC_IN2 94 #define IMX8DXL_ADC_IN5 95 #define IMX8DXL_ADC_IN4 96 #define IMX8DXL_FLEXCAN0_RX 97 #define IMX8DXL_FLEXCAN0_TX 98 #define IMX8DXL_FLEXCAN1_RX 99 #define IMX8DXL_FLEXCAN1_TX 100 #define IMX8DXL_FLEXCAN2_RX 101 #define IMX8DXL_FLEXCAN2_TX 102 #define IMX8DXL_UART0_RX 103 #define IMX8DXL_UART0_TX 104 #define IMX8DXL_UART2_TX 105 #define IMX8DXL_UART2_RX 106 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 107 #define IMX8DXL_JTAG_TRST_B 108 #define IMX8DXL_PMIC_I2C_SCL 109 #define IMX8DXL_PMIC_I2C_SDA 110 #define IMX8DXL_PMIC_INT_B 111 #define IMX8DXL_SCU_GPIO0_00 112 #define IMX8DXL_SCU_GPIO0_01 113 #define IMX8DXL_SCU_PMIC_STANDBY 114 #define IMX8DXL_SCU_BOOT_MODE1 115 #define IMX8DXL_SCU_BOOT_MODE0 116 #define IMX8DXL_SCU_BOOT_MODE2 117 #define IMX8DXL_SNVS_TAMPER_OUT1 118 #define IMX8DXL_SNVS_TAMPER_OUT2 119 #define IMX8DXL_SNVS_TAMPER_OUT3 120 #define IMX8DXL_SNVS_TAMPER_OUT4 121 #define IMX8DXL_SNVS_TAMPER_IN0 122 #define IMX8DXL_SNVS_TAMPER_IN1 123 #define IMX8DXL_SNVS_TAMPER_IN2 124 #define IMX8DXL_SNVS_TAMPER_IN3 125 #define IMX8DXL_SPI1_SCK 126 #define IMX8DXL_SPI1_SDO 127 #define IMX8DXL_SPI1_SDI 128 #define IMX8DXL_SPI1_CS0 129 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 130 #define IMX8DXL_QSPI0A_DATA1 131 #define IMX8DXL_QSPI0A_DATA0 132 #define IMX8DXL_QSPI0A_DATA3 133 #define IMX8DXL_QSPI0A_DATA2 134 #define IMX8DXL_QSPI0A_SS0_B 135 #define IMX8DXL_QSPI0A_DQS 136 #define IMX8DXL_QSPI0A_SCLK 137 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 138 #define IMX8DXL_QSPI0B_SCLK 139 #define IMX8DXL_QSPI0B_DQS 140 #define IMX8DXL_QSPI0B_DATA1 141 #define IMX8DXL_QSPI0B_DATA0 142 #define IMX8DXL_QSPI0B_DATA3 143 #define IMX8DXL_QSPI0B_DATA2 144 #define IMX8DXL_QSPI0B_SS0_B 145 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 146 147 /* format: <pin_id mux_mode> */ 148 #define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_ 149 #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_ 150 #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_ 151 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0 152 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4 153 #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7 154 #define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_W 155 #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_I 156 #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_I 157 #define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL 158 #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 159 #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR 160 #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 161 #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 162 #define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL 163 #define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 164 #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 165 #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 166 #define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA 167 #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC 168 #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC 169 #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 170 #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 171 #define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA 172 #define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC 173 #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 174 #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 175 #define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 176 #define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B 177 #define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 178 #define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 179 #define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS 180 #define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 181 #define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 182 #define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 183 #define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 184 #define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 185 #define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 186 #define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 187 #define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 188 #define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 189 #define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 190 #define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 191 #define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 192 #define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 193 #define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 194 #define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 195 #define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 196 #define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 197 #define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 198 #define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 199 #define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 200 #define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 201 #define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 202 #define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 203 #define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 204 #define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 205 #define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 206 #define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE 207 #define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 208 #define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET 209 #define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B 210 #define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 211 #define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RES 212 #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N 213 #define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 214 #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B 215 #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 216 #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 217 #define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSE 218 #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P 219 #define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 220 #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B 221 #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 222 #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 223 #define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP 224 #define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N 225 #define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 226 #define IMX8DXL_USDHC1_WP_CONN_NAND_ALE 227 #define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 228 #define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 229 #define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B 230 #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P 231 #define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 232 #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS 233 #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 234 #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 235 #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGM 236 #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCL 237 #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCL 238 #define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_ 239 #define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO2 240 #define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CL 241 #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_ 242 #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1 243 #define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_ 244 #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2 245 #define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RG 246 #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_V 247 #define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO 248 #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_D 249 #define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RG 250 #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_W 251 #define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO 252 #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_D 253 #define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RG 254 #define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0 255 #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_C 256 #define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO 257 #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_D 258 #define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RG 259 #define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_ 260 #define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO 261 #define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_D 262 #define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGM 263 #define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B 264 #define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CL 265 #define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO0 266 #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_ 267 #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1 268 #define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_ 269 #define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RG 270 #define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_D 271 #define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO 272 #define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RG 273 #define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_D 274 #define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO 275 #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RG 276 #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RM 277 #define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_D 278 #define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO 279 #define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RG 280 #define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE 281 #define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_D 282 #define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO 283 #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENE 284 #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENE 285 #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQO 286 #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQO 287 #define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPI 288 #define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 289 #define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA 290 #define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 291 #define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 292 #define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 293 #define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 294 #define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL 295 #define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 296 #define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 297 #define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 298 #define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO0 299 #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK 300 #define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 301 #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMI 302 #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK 303 #define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D0 304 #define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGM 305 #define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO 306 #define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_ 307 #define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_R 308 #define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_ 309 #define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D0 310 #define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGM 311 #define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO 312 #define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 313 #define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMI 314 #define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO0 315 #define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D0 316 #define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGM 317 #define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO 318 #define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D0 319 #define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGM 320 #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO 321 #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO 322 #define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D0 323 #define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGM 324 #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO 325 #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO 326 #define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D0 327 #define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGM 328 #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO 329 #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO 330 #define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D0 331 #define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGM 332 #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO 333 #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO 334 #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_R 335 #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R 336 #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D1 337 #define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGM 338 #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO 339 #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO 340 #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0 341 #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L 342 #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_ 343 #define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_R 344 #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_ 345 #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_ 346 #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPD 347 #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCD 348 #define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQO 349 #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPI 350 #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPI 351 #define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 352 #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 353 #define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 354 #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 355 #define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 356 #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 357 #define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 358 #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 359 #define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 360 #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 361 #define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 362 #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 363 #define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 364 #define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 365 #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC 366 #define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 367 #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS 368 #define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 369 #define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL 370 #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET 371 #define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 372 #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 373 #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E 374 #define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 375 #define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA 376 #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN 377 #define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK 378 #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 379 #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 380 #define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 381 #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC 382 #define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI 383 #define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 384 #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS 385 #define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 386 #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK 387 #define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO 388 #define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 389 #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN 390 #define IMX8DXL_UART1_TX_ADMA_UART1_TX 391 #define IMX8DXL_UART1_TX_LSIO_PWM0_OUT 392 #define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE 393 #define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 394 #define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 395 #define IMX8DXL_UART1_RX_ADMA_UART1_RX 396 #define IMX8DXL_UART1_RX_LSIO_PWM1_OUT 397 #define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE 398 #define IMX8DXL_UART1_RX_LSIO_GPT1_CLK 399 #define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 400 #define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 401 #define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 402 #define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT 403 #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 404 #define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE 405 #define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK 406 #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 407 #define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 408 #define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT 409 #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 410 #define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE 411 #define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 412 #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 413 #define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 414 #define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 415 #define IMX8DXL_SPI0_SCK_M40_I2C0_SCL 416 #define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 417 #define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 418 #define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 419 #define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 420 #define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 421 #define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 422 #define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 423 #define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 424 #define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 425 #define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 426 #define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 427 #define IMX8DXL_SPI0_SDO_M40_I2C0_SDA 428 #define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 429 #define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 430 #define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 431 #define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 432 #define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 433 #define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD 434 #define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT 435 #define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 436 #define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 437 #define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 438 #define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 439 #define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 440 #define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 441 #define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 442 #define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 443 #define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 444 #define IMX8DXL_ADC_IN1_M40_I2C0_SDA 445 #define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 446 #define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA 447 #define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 448 #define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 449 #define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 450 #define IMX8DXL_ADC_IN0_M40_I2C0_SCL 451 #define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 452 #define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL 453 #define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 454 #define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 455 #define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 456 #define IMX8DXL_ADC_IN3_M40_UART0_TX 457 #define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 458 #define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 459 #define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 460 #define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 461 #define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 462 #define IMX8DXL_ADC_IN2_M40_UART0_RX 463 #define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 464 #define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 465 #define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 466 #define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 467 #define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 468 #define IMX8DXL_ADC_IN5_M40_TPM0_CH1 469 #define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 470 #define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY 471 #define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 472 #define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 473 #define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 474 #define IMX8DXL_ADC_IN4_M40_TPM0_CH0 475 #define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 476 #define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET 477 #define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 478 #define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 479 #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC 480 #define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B 481 #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 482 #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 483 #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 484 #define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 485 #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD 486 #define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B 487 #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 488 #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 489 #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 490 #define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 491 #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS 492 #define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 493 #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 494 #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 495 #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 496 #define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 497 #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC 498 #define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 499 #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 500 #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 501 #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 502 #define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 503 #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD 504 #define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX 505 #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS 506 #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 507 #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 508 #define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 509 #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS 510 #define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX 511 #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC 512 #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 513 #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 514 #define IMX8DXL_UART0_RX_ADMA_UART0_RX 515 #define IMX8DXL_UART0_RX_ADMA_MQS_R 516 #define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX 517 #define IMX8DXL_UART0_RX_SCU_UART0_RX 518 #define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 519 #define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 520 #define IMX8DXL_UART0_TX_ADMA_UART0_TX 521 #define IMX8DXL_UART0_TX_ADMA_MQS_L 522 #define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX 523 #define IMX8DXL_UART0_TX_SCU_UART0_TX 524 #define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 525 #define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 526 #define IMX8DXL_UART2_TX_ADMA_UART2_TX 527 #define IMX8DXL_UART2_TX_ADMA_FTM_CH1 528 #define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 529 #define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 530 #define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 531 #define IMX8DXL_UART2_RX_ADMA_UART2_RX 532 #define IMX8DXL_UART2_RX_ADMA_FTM_CH0 533 #define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 534 #define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 535 #define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 536 #define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B 537 #define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT 538 #define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL 539 #define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PM 540 #define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 541 #define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA 542 #define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PM 543 #define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 544 #define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B 545 #define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 546 #define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX 547 #define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX 548 #define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX 549 #define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 550 #define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 551 #define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX 552 #define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX 553 #define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX 554 #define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OU 555 #define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_ 556 #define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MO 557 #define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MO 558 #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MO 559 #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLO 560 #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO 561 #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO 562 #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO 563 #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO 564 #define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 565 #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO 566 #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO 567 #define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 568 #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO 569 #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO 570 #define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 571 #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO0 572 #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO2 573 #define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 574 #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO1 575 #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO2 576 #define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 577 #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO1 578 #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO2 579 #define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 580 #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO1 581 #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO2 582 #define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 583 #define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK 584 #define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 585 #define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 586 #define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO 587 #define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 588 #define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 589 #define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI 590 #define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 591 #define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 592 #define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 593 #define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 594 #define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 595 #define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 596 #define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 597 #define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 598 #define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 599 #define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 600 #define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 601 #define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 602 #define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 603 #define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 604 #define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 605 #define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 606 #define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 607 #define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 608 #define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 609 #define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 610 #define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 611 #define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 612 #define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 613 #define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 614 #define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 615 #define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 616 #define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 617 #define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 618 #define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 619 #define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 620 #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 621 #define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 622 #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B 623 624 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_ 625 #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD 626 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_ 627 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_ 628 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENE 629 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENE 630 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_P 631 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_ 632 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_ 633 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_ 634 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_P 635 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_ 636 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_P 637 #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_P 638 639 #endif 640
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