1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * MIO pin configuration defines for Xilinx Zy 4 * 5 * Copyright (C) 2020 Xilinx, Inc. 6 */ 7 8 #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 9 #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 10 11 /* Bit value for different voltage levels */ 12 #define IO_STANDARD_LVCMOS33 0 13 #define IO_STANDARD_LVCMOS18 1 14 15 /* Bit values for Slew Rates */ 16 #define SLEW_RATE_FAST 0 17 #define SLEW_RATE_SLOW 1 18 19 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 20
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