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Linux/include/dt-bindings/power/r8a7795-sysc.h

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Diff markup

Differences between /include/dt-bindings/power/r8a7795-sysc.h (Architecture alpha) and /include/dt-bindings/power/r8a7795-sysc.h (Architecture ppc)


  1 /* SPDX-License-Identifier: GPL-2.0-only */         1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*                                                  2 /*
  3  * Copyright (C) 2016 Glider bvba                   3  * Copyright (C) 2016 Glider bvba
  4  */                                                 4  */
  5 #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__        5 #ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
  6 #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__        6 #define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
  7                                                     7 
  8 /*                                                  8 /*
  9  * These power domain indices match the number      9  * These power domain indices match the numbers of the interrupt bits
 10  * representing the power areas in the various     10  * representing the power areas in the various Interrupt Registers
 11  * (e.g. SYSCISR, Interrupt Status Register)       11  * (e.g. SYSCISR, Interrupt Status Register)
 12  */                                                12  */
 13                                                    13 
 14 #define R8A7795_PD_CA57_CPU0             0         14 #define R8A7795_PD_CA57_CPU0             0
 15 #define R8A7795_PD_CA57_CPU1             1         15 #define R8A7795_PD_CA57_CPU1             1
 16 #define R8A7795_PD_CA57_CPU2             2         16 #define R8A7795_PD_CA57_CPU2             2
 17 #define R8A7795_PD_CA57_CPU3             3         17 #define R8A7795_PD_CA57_CPU3             3
 18 #define R8A7795_PD_CA53_CPU0             5         18 #define R8A7795_PD_CA53_CPU0             5
 19 #define R8A7795_PD_CA53_CPU1             6         19 #define R8A7795_PD_CA53_CPU1             6
 20 #define R8A7795_PD_CA53_CPU2             7         20 #define R8A7795_PD_CA53_CPU2             7
 21 #define R8A7795_PD_CA53_CPU3             8         21 #define R8A7795_PD_CA53_CPU3             8
 22 #define R8A7795_PD_A3VP                  9         22 #define R8A7795_PD_A3VP                  9
 23 #define R8A7795_PD_CA57_SCU             12         23 #define R8A7795_PD_CA57_SCU             12
 24 #define R8A7795_PD_CR7                  13         24 #define R8A7795_PD_CR7                  13
 25 #define R8A7795_PD_A3VC                 14         25 #define R8A7795_PD_A3VC                 14
 26 #define R8A7795_PD_3DG_A                17         26 #define R8A7795_PD_3DG_A                17
 27 #define R8A7795_PD_3DG_B                18         27 #define R8A7795_PD_3DG_B                18
 28 #define R8A7795_PD_3DG_C                19         28 #define R8A7795_PD_3DG_C                19
 29 #define R8A7795_PD_3DG_D                20         29 #define R8A7795_PD_3DG_D                20
 30 #define R8A7795_PD_CA53_SCU             21         30 #define R8A7795_PD_CA53_SCU             21
 31 #define R8A7795_PD_3DG_E                22         31 #define R8A7795_PD_3DG_E                22
 32 #define R8A7795_PD_A3IR                 24         32 #define R8A7795_PD_A3IR                 24
 33 #define R8A7795_PD_A2VC1                26         33 #define R8A7795_PD_A2VC1                26
 34                                                    34 
 35 /* Always-on power area */                         35 /* Always-on power area */
 36 #define R8A7795_PD_ALWAYS_ON            32         36 #define R8A7795_PD_ALWAYS_ON            32
 37                                                    37 
 38 #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__     38 #endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */
 39                                                    39 

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