1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3 3 4 #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ 4 #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ 5 #define __ABI_MACH_T234_POWERGATE_T234_H_ 5 #define __ABI_MACH_T234_POWERGATE_T234_H_ 6 6 7 #define TEGRA234_POWER_DOMAIN_OFA 1U 7 #define TEGRA234_POWER_DOMAIN_OFA 1U 8 #define TEGRA234_POWER_DOMAIN_AUD 2U 8 #define TEGRA234_POWER_DOMAIN_AUD 2U 9 #define TEGRA234_POWER_DOMAIN_DISP 3U 9 #define TEGRA234_POWER_DOMAIN_DISP 3U 10 #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U 10 #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U 11 #define TEGRA234_POWER_DOMAIN_PCIEX4A 6U 11 #define TEGRA234_POWER_DOMAIN_PCIEX4A 6U 12 #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U 12 #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U 13 #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U 13 #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U 14 #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U 14 #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U 15 #define TEGRA234_POWER_DOMAIN_XUSBA 10U 15 #define TEGRA234_POWER_DOMAIN_XUSBA 10U 16 #define TEGRA234_POWER_DOMAIN_XUSBB 11U 16 #define TEGRA234_POWER_DOMAIN_XUSBB 11U 17 #define TEGRA234_POWER_DOMAIN_XUSBC 12U 17 #define TEGRA234_POWER_DOMAIN_XUSBC 12U 18 #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U 18 #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U 19 #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U 19 #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U 20 #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U 20 #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U 21 #define TEGRA234_POWER_DOMAIN_PCIEX8B 16U 21 #define TEGRA234_POWER_DOMAIN_PCIEX8B 16U 22 #define TEGRA234_POWER_DOMAIN_MGBEA 17U 22 #define TEGRA234_POWER_DOMAIN_MGBEA 17U 23 #define TEGRA234_POWER_DOMAIN_MGBEB 18U 23 #define TEGRA234_POWER_DOMAIN_MGBEB 18U 24 #define TEGRA234_POWER_DOMAIN_MGBEC 19U 24 #define TEGRA234_POWER_DOMAIN_MGBEC 19U 25 #define TEGRA234_POWER_DOMAIN_MGBED 20U 25 #define TEGRA234_POWER_DOMAIN_MGBED 20U 26 #define TEGRA234_POWER_DOMAIN_ISPA 22U 26 #define TEGRA234_POWER_DOMAIN_ISPA 22U 27 #define TEGRA234_POWER_DOMAIN_NVDEC 23U 27 #define TEGRA234_POWER_DOMAIN_NVDEC 23U 28 #define TEGRA234_POWER_DOMAIN_NVJPGA 24U 28 #define TEGRA234_POWER_DOMAIN_NVJPGA 24U 29 #define TEGRA234_POWER_DOMAIN_NVENC 25U 29 #define TEGRA234_POWER_DOMAIN_NVENC 25U 30 #define TEGRA234_POWER_DOMAIN_VI 28U 30 #define TEGRA234_POWER_DOMAIN_VI 28U 31 #define TEGRA234_POWER_DOMAIN_VIC 29U 31 #define TEGRA234_POWER_DOMAIN_VIC 29U 32 #define TEGRA234_POWER_DOMAIN_PVA 30U 32 #define TEGRA234_POWER_DOMAIN_PVA 30U 33 #define TEGRA234_POWER_DOMAIN_DLAA 32U 33 #define TEGRA234_POWER_DOMAIN_DLAA 32U 34 #define TEGRA234_POWER_DOMAIN_DLAB 33U 34 #define TEGRA234_POWER_DOMAIN_DLAB 33U 35 #define TEGRA234_POWER_DOMAIN_CV 34U 35 #define TEGRA234_POWER_DOMAIN_CV 34U 36 #define TEGRA234_POWER_DOMAIN_GPU 35U 36 #define TEGRA234_POWER_DOMAIN_GPU 35U 37 #define TEGRA234_POWER_DOMAIN_NVJPGB 36U 37 #define TEGRA234_POWER_DOMAIN_NVJPGB 36U 38 38 39 #endif 39 #endif 40 40
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