1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 2 /* 3 * Device Tree binding constants for Actions S 3 * Device Tree binding constants for Actions Semi S500 Reset Management Unit 4 * 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Copyright (c) 2020 Cristian Ciocaltea <cris 6 * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> 7 */ 7 */ 8 8 9 #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H 9 #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H 10 #define __DT_BINDINGS_ACTIONS_S500_RESET_H 10 #define __DT_BINDINGS_ACTIONS_S500_RESET_H 11 11 12 #define RESET_DMAC 12 #define RESET_DMAC 0 13 #define RESET_NORIF 13 #define RESET_NORIF 1 14 #define RESET_DDR 14 #define RESET_DDR 2 15 #define RESET_NANDC 15 #define RESET_NANDC 3 16 #define RESET_SD0 16 #define RESET_SD0 4 17 #define RESET_SD1 17 #define RESET_SD1 5 18 #define RESET_PCM1 18 #define RESET_PCM1 6 19 #define RESET_DE 19 #define RESET_DE 7 20 #define RESET_LCD 20 #define RESET_LCD 8 21 #define RESET_SD2 21 #define RESET_SD2 9 22 #define RESET_DSI 22 #define RESET_DSI 10 23 #define RESET_CSI 23 #define RESET_CSI 11 24 #define RESET_BISP 24 #define RESET_BISP 12 25 #define RESET_KEY 25 #define RESET_KEY 13 26 #define RESET_GPIO 26 #define RESET_GPIO 14 27 #define RESET_AUDIO 27 #define RESET_AUDIO 15 28 #define RESET_PCM0 28 #define RESET_PCM0 16 29 #define RESET_VDE 29 #define RESET_VDE 17 30 #define RESET_VCE 30 #define RESET_VCE 18 31 #define RESET_GPU3D 31 #define RESET_GPU3D 19 32 #define RESET_NIC301 32 #define RESET_NIC301 20 33 #define RESET_LENS 33 #define RESET_LENS 21 34 #define RESET_PERIPHRESET 34 #define RESET_PERIPHRESET 22 35 #define RESET_USB2_0 35 #define RESET_USB2_0 23 36 #define RESET_TVOUT 36 #define RESET_TVOUT 24 37 #define RESET_HDMI 37 #define RESET_HDMI 25 38 #define RESET_HDCP2TX 38 #define RESET_HDCP2TX 26 39 #define RESET_UART6 39 #define RESET_UART6 27 40 #define RESET_UART0 40 #define RESET_UART0 28 41 #define RESET_UART1 41 #define RESET_UART1 29 42 #define RESET_UART2 42 #define RESET_UART2 30 43 #define RESET_SPI0 43 #define RESET_SPI0 31 44 #define RESET_SPI1 44 #define RESET_SPI1 32 45 #define RESET_SPI2 45 #define RESET_SPI2 33 46 #define RESET_SPI3 46 #define RESET_SPI3 34 47 #define RESET_I2C0 47 #define RESET_I2C0 35 48 #define RESET_I2C1 48 #define RESET_I2C1 36 49 #define RESET_USB3 49 #define RESET_USB3 37 50 #define RESET_UART3 50 #define RESET_UART3 38 51 #define RESET_UART4 51 #define RESET_UART4 39 52 #define RESET_UART5 52 #define RESET_UART5 40 53 #define RESET_I2C2 53 #define RESET_I2C2 41 54 #define RESET_I2C3 54 #define RESET_I2C3 42 55 #define RESET_ETHERNET 55 #define RESET_ETHERNET 43 56 #define RESET_CHIPID 56 #define RESET_CHIPID 44 57 #define RESET_USB2_1 57 #define RESET_USB2_1 45 58 #define RESET_WD0RESET 58 #define RESET_WD0RESET 46 59 #define RESET_WD1RESET 59 #define RESET_WD1RESET 47 60 #define RESET_WD2RESET 60 #define RESET_WD2RESET 48 61 #define RESET_WD3RESET 61 #define RESET_WD3RESET 49 62 #define RESET_DBG0RESET 62 #define RESET_DBG0RESET 50 63 #define RESET_DBG1RESET 63 #define RESET_DBG1RESET 51 64 #define RESET_DBG2RESET 64 #define RESET_DBG2RESET 52 65 #define RESET_DBG3RESET 65 #define RESET_DBG3RESET 53 66 66 67 #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H * 67 #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ 68 68
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