1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 2 /* 3 * Device Tree binding constants for Actions S 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Copyright (c) 2020 Cristian Ciocaltea <cris 7 */ 8 9 #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H 10 #define __DT_BINDINGS_ACTIONS_S500_RESET_H 11 12 #define RESET_DMAC 13 #define RESET_NORIF 14 #define RESET_DDR 15 #define RESET_NANDC 16 #define RESET_SD0 17 #define RESET_SD1 18 #define RESET_PCM1 19 #define RESET_DE 20 #define RESET_LCD 21 #define RESET_SD2 22 #define RESET_DSI 23 #define RESET_CSI 24 #define RESET_BISP 25 #define RESET_KEY 26 #define RESET_GPIO 27 #define RESET_AUDIO 28 #define RESET_PCM0 29 #define RESET_VDE 30 #define RESET_VCE 31 #define RESET_GPU3D 32 #define RESET_NIC301 33 #define RESET_LENS 34 #define RESET_PERIPHRESET 35 #define RESET_USB2_0 36 #define RESET_TVOUT 37 #define RESET_HDMI 38 #define RESET_HDCP2TX 39 #define RESET_UART6 40 #define RESET_UART0 41 #define RESET_UART1 42 #define RESET_UART2 43 #define RESET_SPI0 44 #define RESET_SPI1 45 #define RESET_SPI2 46 #define RESET_SPI3 47 #define RESET_I2C0 48 #define RESET_I2C1 49 #define RESET_USB3 50 #define RESET_UART3 51 #define RESET_UART4 52 #define RESET_UART5 53 #define RESET_I2C2 54 #define RESET_I2C3 55 #define RESET_ETHERNET 56 #define RESET_CHIPID 57 #define RESET_USB2_1 58 #define RESET_WD0RESET 59 #define RESET_WD1RESET 60 #define RESET_WD2RESET 61 #define RESET_WD3RESET 62 #define RESET_DBG0RESET 63 #define RESET_DBG1RESET 64 #define RESET_DBG2RESET 65 #define RESET_DBG3RESET 66 67 #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H * 68
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