1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * Copyright (C) 2016 Intel Corporation. All r 2 * Copyright (C) 2016 Intel Corporation. All rights reserved
4 * Copyright (C) 2016 Altera Corporation. All 3 * Copyright (C) 2016 Altera Corporation. All rights reserved
5 * 4 *
>> 5 * This program is free software; you can redistribute it and/or modify
>> 6 * it under the terms and conditions of the GNU General Public License,
>> 7 * version 2, as published by the Free Software Foundation.
>> 8 *
>> 9 * This program is distributed in the hope it will be useful, but WITHOUT
>> 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> 12 * more details.
>> 13 *
>> 14 * You should have received a copy of the GNU General Public License along with
>> 15 * this program. If not, see <http://www.gnu.org/licenses/>.
>> 16 *
6 * derived from Steffen Trumtrar's "altr,rst-m 17 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
7 */ 18 */
8 19
9 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 20 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
10 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H 21 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
11 22
12 /* MPUMODRST */ 23 /* MPUMODRST */
13 #define CPU0_RESET 0 24 #define CPU0_RESET 0
14 #define CPU1_RESET 1 25 #define CPU1_RESET 1
15 #define CPU2_RESET 2 26 #define CPU2_RESET 2
16 #define CPU3_RESET 3 27 #define CPU3_RESET 3
17 28
18 /* PER0MODRST */ 29 /* PER0MODRST */
19 #define EMAC0_RESET 32 30 #define EMAC0_RESET 32
20 #define EMAC1_RESET 33 31 #define EMAC1_RESET 33
21 #define EMAC2_RESET 34 32 #define EMAC2_RESET 34
22 #define USB0_RESET 35 33 #define USB0_RESET 35
23 #define USB1_RESET 36 34 #define USB1_RESET 36
24 #define NAND_RESET 37 35 #define NAND_RESET 37
25 /* 38 is empty */ 36 /* 38 is empty */
26 #define SDMMC_RESET 39 37 #define SDMMC_RESET 39
27 #define EMAC0_OCP_RESET 40 38 #define EMAC0_OCP_RESET 40
28 #define EMAC1_OCP_RESET 41 39 #define EMAC1_OCP_RESET 41
29 #define EMAC2_OCP_RESET 42 40 #define EMAC2_OCP_RESET 42
30 #define USB0_OCP_RESET 43 41 #define USB0_OCP_RESET 43
31 #define USB1_OCP_RESET 44 42 #define USB1_OCP_RESET 44
32 #define NAND_OCP_RESET 45 43 #define NAND_OCP_RESET 45
33 /* 46 is empty */ 44 /* 46 is empty */
34 #define SDMMC_OCP_RESET 47 45 #define SDMMC_OCP_RESET 47
35 #define DMA_RESET 48 46 #define DMA_RESET 48
36 #define SPIM0_RESET 49 47 #define SPIM0_RESET 49
37 #define SPIM1_RESET 50 48 #define SPIM1_RESET 50
38 #define SPIS0_RESET 51 49 #define SPIS0_RESET 51
39 #define SPIS1_RESET 52 50 #define SPIS1_RESET 52
40 #define DMA_OCP_RESET 53 51 #define DMA_OCP_RESET 53
41 #define EMAC_PTP_RESET 54 52 #define EMAC_PTP_RESET 54
42 /* 55 is empty*/ 53 /* 55 is empty*/
43 #define DMAIF0_RESET 56 54 #define DMAIF0_RESET 56
44 #define DMAIF1_RESET 57 55 #define DMAIF1_RESET 57
45 #define DMAIF2_RESET 58 56 #define DMAIF2_RESET 58
46 #define DMAIF3_RESET 59 57 #define DMAIF3_RESET 59
47 #define DMAIF4_RESET 60 58 #define DMAIF4_RESET 60
48 #define DMAIF5_RESET 61 59 #define DMAIF5_RESET 61
49 #define DMAIF6_RESET 62 60 #define DMAIF6_RESET 62
50 #define DMAIF7_RESET 63 61 #define DMAIF7_RESET 63
51 62
52 /* PER1MODRST */ 63 /* PER1MODRST */
53 #define WATCHDOG0_RESET 64 64 #define WATCHDOG0_RESET 64
54 #define WATCHDOG1_RESET 65 65 #define WATCHDOG1_RESET 65
55 #define WATCHDOG2_RESET 66 66 #define WATCHDOG2_RESET 66
56 #define WATCHDOG3_RESET 67 67 #define WATCHDOG3_RESET 67
57 #define L4SYSTIMER0_RESET 68 68 #define L4SYSTIMER0_RESET 68
58 #define L4SYSTIMER1_RESET 69 69 #define L4SYSTIMER1_RESET 69
59 #define SPTIMER0_RESET 70 70 #define SPTIMER0_RESET 70
60 #define SPTIMER1_RESET 71 71 #define SPTIMER1_RESET 71
61 #define I2C0_RESET 72 72 #define I2C0_RESET 72
62 #define I2C1_RESET 73 73 #define I2C1_RESET 73
63 #define I2C2_RESET 74 74 #define I2C2_RESET 74
64 #define I2C3_RESET 75 75 #define I2C3_RESET 75
65 #define I2C4_RESET 76 76 #define I2C4_RESET 76
66 #define I3C0_RESET 77 !! 77 /* 77-79 is empty */
67 #define I3C1_RESET 78 <<
68 /* 79 is empty */ <<
69 #define UART0_RESET 80 78 #define UART0_RESET 80
70 #define UART1_RESET 81 79 #define UART1_RESET 81
71 /* 82-87 is empty */ 80 /* 82-87 is empty */
72 #define GPIO0_RESET 88 81 #define GPIO0_RESET 88
73 #define GPIO1_RESET 89 82 #define GPIO1_RESET 89
74 #define WATCHDOG4_RESET 90 <<
75 83
76 /* BRGMODRST */ 84 /* BRGMODRST */
77 #define SOC2FPGA_RESET 96 85 #define SOC2FPGA_RESET 96
78 #define LWHPS2FPGA_RESET 97 86 #define LWHPS2FPGA_RESET 97
79 #define FPGA2SOC_RESET 98 87 #define FPGA2SOC_RESET 98
80 #define F2SSDRAM0_RESET 99 88 #define F2SSDRAM0_RESET 99
81 #define F2SSDRAM1_RESET 100 89 #define F2SSDRAM1_RESET 100
82 #define F2SSDRAM2_RESET 101 90 #define F2SSDRAM2_RESET 101
83 #define DDRSCH_RESET 102 91 #define DDRSCH_RESET 102
84 92
85 /* COLDMODRST */ 93 /* COLDMODRST */
86 #define CPUPO0_RESET 160 94 #define CPUPO0_RESET 160
87 #define CPUPO1_RESET 161 95 #define CPUPO1_RESET 161
88 #define CPUPO2_RESET 162 96 #define CPUPO2_RESET 162
89 #define CPUPO3_RESET 163 97 #define CPUPO3_RESET 163
90 /* 164-167 is empty */ 98 /* 164-167 is empty */
91 #define L2_RESET 168 99 #define L2_RESET 168
92 100
93 /* DBGMODRST */ 101 /* DBGMODRST */
94 #define DBG_RESET 224 102 #define DBG_RESET 224
95 #define CSDAP_RESET 225 103 #define CSDAP_RESET 225
96 104
97 /* TAPMODRST */ 105 /* TAPMODRST */
98 #define TAP_RESET 256 106 #define TAP_RESET 256
99 107
100 #endif 108 #endif
101 109
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