1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright (c) 2014, Steffen Trumtrar <s.tru 3 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 6 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 7 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 7 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 8 8 9 /* MPUMODRST */ 9 /* MPUMODRST */ 10 #define CPU0_RESET 0 10 #define CPU0_RESET 0 11 #define CPU1_RESET 1 11 #define CPU1_RESET 1 12 #define WDS_RESET 2 12 #define WDS_RESET 2 13 #define SCUPER_RESET 3 13 #define SCUPER_RESET 3 14 #define L2_RESET 4 14 #define L2_RESET 4 15 15 16 /* PERMODRST */ 16 /* PERMODRST */ 17 #define EMAC0_RESET 32 17 #define EMAC0_RESET 32 18 #define EMAC1_RESET 33 18 #define EMAC1_RESET 33 19 #define USB0_RESET 34 19 #define USB0_RESET 34 20 #define USB1_RESET 35 20 #define USB1_RESET 35 21 #define NAND_RESET 36 21 #define NAND_RESET 36 22 #define QSPI_RESET 37 22 #define QSPI_RESET 37 23 #define L4WD0_RESET 38 23 #define L4WD0_RESET 38 24 #define L4WD1_RESET 39 24 #define L4WD1_RESET 39 25 #define OSC1TIMER0_RESET 40 25 #define OSC1TIMER0_RESET 40 26 #define OSC1TIMER1_RESET 41 26 #define OSC1TIMER1_RESET 41 27 #define SPTIMER0_RESET 42 27 #define SPTIMER0_RESET 42 28 #define SPTIMER1_RESET 43 28 #define SPTIMER1_RESET 43 29 #define I2C0_RESET 44 29 #define I2C0_RESET 44 30 #define I2C1_RESET 45 30 #define I2C1_RESET 45 31 #define I2C2_RESET 46 31 #define I2C2_RESET 46 32 #define I2C3_RESET 47 32 #define I2C3_RESET 47 33 #define UART0_RESET 48 33 #define UART0_RESET 48 34 #define UART1_RESET 49 34 #define UART1_RESET 49 35 #define SPIM0_RESET 50 35 #define SPIM0_RESET 50 36 #define SPIM1_RESET 51 36 #define SPIM1_RESET 51 37 #define SPIS0_RESET 52 37 #define SPIS0_RESET 52 38 #define SPIS1_RESET 53 38 #define SPIS1_RESET 53 39 #define SDMMC_RESET 54 39 #define SDMMC_RESET 54 40 #define CAN0_RESET 55 40 #define CAN0_RESET 55 41 #define CAN1_RESET 56 41 #define CAN1_RESET 56 42 #define GPIO0_RESET 57 42 #define GPIO0_RESET 57 43 #define GPIO1_RESET 58 43 #define GPIO1_RESET 58 44 #define GPIO2_RESET 59 44 #define GPIO2_RESET 59 45 #define DMA_RESET 60 45 #define DMA_RESET 60 46 #define SDR_RESET 61 46 #define SDR_RESET 61 47 47 48 /* PER2MODRST */ 48 /* PER2MODRST */ 49 #define DMAIF0_RESET 64 49 #define DMAIF0_RESET 64 50 #define DMAIF1_RESET 65 50 #define DMAIF1_RESET 65 51 #define DMAIF2_RESET 66 51 #define DMAIF2_RESET 66 52 #define DMAIF3_RESET 67 52 #define DMAIF3_RESET 67 53 #define DMAIF4_RESET 68 53 #define DMAIF4_RESET 68 54 #define DMAIF5_RESET 69 54 #define DMAIF5_RESET 69 55 #define DMAIF6_RESET 70 55 #define DMAIF6_RESET 70 56 #define DMAIF7_RESET 71 56 #define DMAIF7_RESET 71 57 57 58 /* BRGMODRST */ 58 /* BRGMODRST */ 59 #define HPS2FPGA_RESET 96 59 #define HPS2FPGA_RESET 96 60 #define LWHPS2FPGA_RESET 97 60 #define LWHPS2FPGA_RESET 97 61 #define FPGA2HPS_RESET 98 61 #define FPGA2HPS_RESET 98 62 62 63 /* MISCMODRST*/ 63 /* MISCMODRST*/ 64 #define ROM_RESET 128 64 #define ROM_RESET 128 65 #define OCRAM_RESET 129 65 #define OCRAM_RESET 129 66 #define SYSMGR_RESET 130 66 #define SYSMGR_RESET 130 67 #define SYSMGRCOLD_RESET 131 67 #define SYSMGRCOLD_RESET 131 68 #define FPGAMGR_RESET 132 68 #define FPGAMGR_RESET 132 69 #define ACPIDMAP_RESET 133 69 #define ACPIDMAP_RESET 133 70 #define S2F_RESET 134 70 #define S2F_RESET 134 71 #define S2FCOLD_RESET 135 71 #define S2FCOLD_RESET 135 72 #define NRSTPIN_RESET 136 72 #define NRSTPIN_RESET 136 73 #define TIMESTAMPCOLD_RESET 137 73 #define TIMESTAMPCOLD_RESET 137 74 #define CLKMGRCOLD_RESET 138 74 #define CLKMGRCOLD_RESET 138 75 #define SCANMGR_RESET 139 75 #define SCANMGR_RESET 139 76 #define FRZCTRLCOLD_RESET 140 76 #define FRZCTRLCOLD_RESET 140 77 #define SYSDBG_RESET 141 77 #define SYSDBG_RESET 141 78 #define DBG_RESET 142 78 #define DBG_RESET 142 79 #define TAPCOLD_RESET 143 79 #define TAPCOLD_RESET 143 80 #define SDRCOLD_RESET 144 80 #define SDRCOLD_RESET 144 81 81 82 #endif 82 #endif 83 83
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