1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 2 /* 3 * Copyright (c) 2021 Amlogic, Inc. All rights 3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4 * Author: Zelong Dong <zelong.dong@amlogic.co 4 * Author: Zelong Dong <zelong.dong@amlogic.com> 5 * 5 * 6 */ 6 */ 7 7 8 #ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H 8 #ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H 9 #define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H 9 #define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H 10 10 11 /* RESET0 11 /* RESET0 */ 12 #define RESET_USB_DDR0 0 12 #define RESET_USB_DDR0 0 13 #define RESET_USB_DDR1 1 13 #define RESET_USB_DDR1 1 14 #define RESET_USB_DDR2 2 14 #define RESET_USB_DDR2 2 15 #define RESET_USB_DDR3 3 15 #define RESET_USB_DDR3 3 16 #define RESET_USBCTRL 4 16 #define RESET_USBCTRL 4 17 /* 5-7 17 /* 5-7 */ 18 #define RESET_USBPHY20 8 18 #define RESET_USBPHY20 8 19 #define RESET_USBPHY21 9 19 #define RESET_USBPHY21 9 20 /* 10-15 20 /* 10-15 */ 21 #define RESET_HDMITX_APB 16 21 #define RESET_HDMITX_APB 16 22 #define RESET_BRG_VCBUS_DEC 17 22 #define RESET_BRG_VCBUS_DEC 17 23 #define RESET_VCBUS 18 23 #define RESET_VCBUS 18 24 #define RESET_VID_PLL_DIV 19 24 #define RESET_VID_PLL_DIV 19 25 #define RESET_VDI6 20 25 #define RESET_VDI6 20 26 #define RESET_GE2D 21 26 #define RESET_GE2D 21 27 #define RESET_HDMITXPHY 22 27 #define RESET_HDMITXPHY 22 28 #define RESET_VID_LOCK 23 28 #define RESET_VID_LOCK 23 29 #define RESET_VENCL 24 29 #define RESET_VENCL 24 30 #define RESET_VDAC 25 30 #define RESET_VDAC 25 31 #define RESET_VENCP 26 31 #define RESET_VENCP 26 32 #define RESET_VENCI 27 32 #define RESET_VENCI 27 33 #define RESET_RDMA 28 33 #define RESET_RDMA 28 34 #define RESET_HDMI_TX 29 34 #define RESET_HDMI_TX 29 35 #define RESET_VIU 30 35 #define RESET_VIU 30 36 #define RESET_VENC 31 36 #define RESET_VENC 31 37 37 38 /* RESET1 38 /* RESET1 */ 39 #define RESET_AUDIO 32 39 #define RESET_AUDIO 32 40 #define RESET_MALI_APB 33 40 #define RESET_MALI_APB 33 41 #define RESET_MALI 34 41 #define RESET_MALI 34 42 #define RESET_DDR_APB 35 42 #define RESET_DDR_APB 35 43 #define RESET_DDR 36 43 #define RESET_DDR 36 44 #define RESET_DOS_APB 37 44 #define RESET_DOS_APB 37 45 #define RESET_DOS 38 45 #define RESET_DOS 38 46 /* 39-47 46 /* 39-47 */ 47 #define RESET_ETH 48 47 #define RESET_ETH 48 48 /* 49-51 48 /* 49-51 */ 49 #define RESET_DEMOD 52 49 #define RESET_DEMOD 52 50 /* 53-63 50 /* 53-63 */ 51 51 52 /* RESET2 52 /* RESET2 */ 53 #define RESET_ABUS_ARB 64 53 #define RESET_ABUS_ARB 64 54 #define RESET_IR_CTRL 65 54 #define RESET_IR_CTRL 65 55 #define RESET_TEMPSENSOR_DDR 66 55 #define RESET_TEMPSENSOR_DDR 66 56 #define RESET_TEMPSENSOR_PLL 67 56 #define RESET_TEMPSENSOR_PLL 67 57 /* 68-71 57 /* 68-71 */ 58 #define RESET_SMART_CARD 72 58 #define RESET_SMART_CARD 72 59 #define RESET_SPICC0 73 59 #define RESET_SPICC0 73 60 /* 74 60 /* 74 */ 61 #define RESET_RSA 75 61 #define RESET_RSA 75 62 /* 76-79 62 /* 76-79 */ 63 #define RESET_MSR_CLK 80 63 #define RESET_MSR_CLK 80 64 #define RESET_SPIFC 81 64 #define RESET_SPIFC 81 65 #define RESET_SARADC 82 65 #define RESET_SARADC 82 66 /* 83-87 66 /* 83-87 */ 67 #define RESET_ACODEC 88 67 #define RESET_ACODEC 88 68 #define RESET_CEC 89 68 #define RESET_CEC 89 69 #define RESET_AFIFO 90 69 #define RESET_AFIFO 90 70 #define RESET_WATCHDOG 91 70 #define RESET_WATCHDOG 91 71 /* 92-95 71 /* 92-95 */ 72 72 73 /* RESET3 73 /* RESET3 */ 74 /* 96-127 74 /* 96-127 */ 75 75 76 /* RESET4 76 /* RESET4 */ 77 /* 128-13 77 /* 128-131 */ 78 #define RESET_PWM_AB 132 78 #define RESET_PWM_AB 132 79 #define RESET_PWM_CD 133 79 #define RESET_PWM_CD 133 80 #define RESET_PWM_EF 134 80 #define RESET_PWM_EF 134 81 #define RESET_PWM_GH 135 81 #define RESET_PWM_GH 135 82 #define RESET_PWM_IJ 136 82 #define RESET_PWM_IJ 136 83 /* 137 83 /* 137 */ 84 #define RESET_UART_A 138 84 #define RESET_UART_A 138 85 #define RESET_UART_B 139 85 #define RESET_UART_B 139 86 #define RESET_UART_C 140 86 #define RESET_UART_C 140 87 #define RESET_UART_D 141 87 #define RESET_UART_D 141 88 #define RESET_UART_E 142 88 #define RESET_UART_E 142 89 /* 143 89 /* 143 */ 90 #define RESET_I2C_S_A 144 90 #define RESET_I2C_S_A 144 91 #define RESET_I2C_M_A 145 91 #define RESET_I2C_M_A 145 92 #define RESET_I2C_M_B 146 92 #define RESET_I2C_M_B 146 93 #define RESET_I2C_M_C 147 93 #define RESET_I2C_M_C 147 94 #define RESET_I2C_M_D 148 94 #define RESET_I2C_M_D 148 95 #define RESET_I2C_M_E 149 95 #define RESET_I2C_M_E 149 96 /* 150-15 96 /* 150-151 */ 97 #define RESET_SD_EMMC_A 152 97 #define RESET_SD_EMMC_A 152 98 #define RESET_SD_EMMC_B 153 98 #define RESET_SD_EMMC_B 153 99 #define RESET_NAND_EMMC 154 99 #define RESET_NAND_EMMC 154 100 /* 155-15 100 /* 155-159 */ 101 101 102 /* RESET5 */ 102 /* RESET5 */ 103 #define RESET_BRG_VDEC_PIPL0 160 103 #define RESET_BRG_VDEC_PIPL0 160 104 #define RESET_BRG_HEVCF_PIPL0 161 104 #define RESET_BRG_HEVCF_PIPL0 161 105 /* 162 105 /* 162 */ 106 #define RESET_BRG_HCODEC_PIPL0 163 106 #define RESET_BRG_HCODEC_PIPL0 163 107 #define RESET_BRG_GE2D_PIPL0 164 107 #define RESET_BRG_GE2D_PIPL0 164 108 #define RESET_BRG_VPU_PIPL0 165 108 #define RESET_BRG_VPU_PIPL0 165 109 #define RESET_BRG_CPU_PIPL0 166 109 #define RESET_BRG_CPU_PIPL0 166 110 #define RESET_BRG_MALI_PIPL0 167 110 #define RESET_BRG_MALI_PIPL0 167 111 /* 168 111 /* 168 */ 112 #define RESET_BRG_MALI_PIPL1 169 112 #define RESET_BRG_MALI_PIPL1 169 113 /* 170-17 113 /* 170-171 */ 114 #define RESET_BRG_HEVCF_PIPL1 172 114 #define RESET_BRG_HEVCF_PIPL1 172 115 #define RESET_BRG_HEVCB_PIPL1 173 115 #define RESET_BRG_HEVCB_PIPL1 173 116 /* 174-18 116 /* 174-183 */ 117 #define RESET_RAMA 184 117 #define RESET_RAMA 184 118 /* 185-18 118 /* 185-186 */ 119 #define RESET_BRG_NIC_VAPB 187 119 #define RESET_BRG_NIC_VAPB 187 120 #define RESET_BRG_NIC_DSU 188 120 #define RESET_BRG_NIC_DSU 188 121 #define RESET_BRG_NIC_SYSCLK 189 121 #define RESET_BRG_NIC_SYSCLK 189 122 #define RESET_BRG_NIC_MAIN 190 122 #define RESET_BRG_NIC_MAIN 190 123 #define RESET_BRG_NIC_ALL 191 123 #define RESET_BRG_NIC_ALL 191 124 124 125 #endif 125 #endif 126 126
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