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Linux/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h

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Diff markup

Differences between /include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h (Architecture ppc) and /include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h (Architecture sparc64)


  1 /*                                                  1 /*
  2  * Copyright (c) 2017 Martin Blumenstingl <mar      2  * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
  3  *                                                  3  *
  4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)       4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  5  */                                                 5  */
  6                                                     6 
  7 #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESE      7 #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
  8 #define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESE      8 #define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
  9                                                     9 
 10 #define CLKC_RESET_L2_CACHE_SOFT_RESET             10 #define CLKC_RESET_L2_CACHE_SOFT_RESET                          0
 11 #define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOF     11 #define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET           1
 12 #define CLKC_RESET_SCU_SOFT_RESET                  12 #define CLKC_RESET_SCU_SOFT_RESET                               2
 13 #define CLKC_RESET_CPU0_SOFT_RESET                 13 #define CLKC_RESET_CPU0_SOFT_RESET                              3
 14 #define CLKC_RESET_CPU1_SOFT_RESET                 14 #define CLKC_RESET_CPU1_SOFT_RESET                              4
 15 #define CLKC_RESET_CPU2_SOFT_RESET                 15 #define CLKC_RESET_CPU2_SOFT_RESET                              5
 16 #define CLKC_RESET_CPU3_SOFT_RESET                 16 #define CLKC_RESET_CPU3_SOFT_RESET                              6
 17 #define CLKC_RESET_A5_GLOBAL_RESET                 17 #define CLKC_RESET_A5_GLOBAL_RESET                              7
 18 #define CLKC_RESET_A5_AXI_SOFT_RESET               18 #define CLKC_RESET_A5_AXI_SOFT_RESET                            8
 19 #define CLKC_RESET_A5_ABP_SOFT_RESET               19 #define CLKC_RESET_A5_ABP_SOFT_RESET                            9
 20 #define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SO     20 #define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET          10
 21 #define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET         21 #define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET                      11
 22 #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET     22 #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST             12
 23 #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET     23 #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE              13
 24 #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PO     24 #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST                14
 25 #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PR     25 #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE                 15
 26                                                    26 
 27 #endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RE     27 #endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
 28                                                    28 

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