1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4 * 4 * 5 * Baikal-T1 CCU reset indices 5 * Baikal-T1 CCU reset indices 6 */ 6 */ 7 #ifndef __DT_BINDINGS_RESET_BT1_CCU_H 7 #ifndef __DT_BINDINGS_RESET_BT1_CCU_H 8 #define __DT_BINDINGS_RESET_BT1_CCU_H 8 #define __DT_BINDINGS_RESET_BT1_CCU_H 9 9 10 #define CCU_AXI_MAIN_RST 0 10 #define CCU_AXI_MAIN_RST 0 11 #define CCU_AXI_DDR_RST 1 11 #define CCU_AXI_DDR_RST 1 12 #define CCU_AXI_SATA_RST 2 12 #define CCU_AXI_SATA_RST 2 13 #define CCU_AXI_GMAC0_RST 3 13 #define CCU_AXI_GMAC0_RST 3 14 #define CCU_AXI_GMAC1_RST 4 14 #define CCU_AXI_GMAC1_RST 4 15 #define CCU_AXI_XGMAC_RST 5 15 #define CCU_AXI_XGMAC_RST 5 16 #define CCU_AXI_PCIE_M_RST 6 16 #define CCU_AXI_PCIE_M_RST 6 17 #define CCU_AXI_PCIE_S_RST 7 17 #define CCU_AXI_PCIE_S_RST 7 18 #define CCU_AXI_USB_RST 8 18 #define CCU_AXI_USB_RST 8 19 #define CCU_AXI_HWA_RST 9 19 #define CCU_AXI_HWA_RST 9 20 #define CCU_AXI_SRAM_RST 10 20 #define CCU_AXI_SRAM_RST 10 21 21 22 #define CCU_SYS_SATA_REF_RST 0 22 #define CCU_SYS_SATA_REF_RST 0 23 #define CCU_SYS_APB_RST 1 23 #define CCU_SYS_APB_RST 1 24 #define CCU_SYS_DDR_FULL_RST 2 << 25 #define CCU_SYS_DDR_INIT_RST 3 << 26 #define CCU_SYS_PCIE_PCS_PHY_RST 4 << 27 #define CCU_SYS_PCIE_PIPE0_RST 5 << 28 #define CCU_SYS_PCIE_CORE_RST 6 << 29 #define CCU_SYS_PCIE_PWR_RST 7 << 30 #define CCU_SYS_PCIE_STICKY_RST 8 << 31 #define CCU_SYS_PCIE_NSTICKY_RST 9 << 32 #define CCU_SYS_PCIE_HOT_RST 10 << 33 24 34 #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ 25 #endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ 35 26
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