1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright (C) 2017 Impinj, Inc. 3 * Copyright (C) 2017 Impinj, Inc. 4 * 4 * 5 * Author: Andrey Smirnov <andrew.smirnov@gmai 5 * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 6 */ 6 */ 7 7 8 #ifndef DT_BINDING_RESET_IMX7_H 8 #ifndef DT_BINDING_RESET_IMX7_H 9 #define DT_BINDING_RESET_IMX7_H 9 #define DT_BINDING_RESET_IMX7_H 10 10 11 #define IMX7_RESET_A7_CORE_POR_RESET0 0 11 #define IMX7_RESET_A7_CORE_POR_RESET0 0 12 #define IMX7_RESET_A7_CORE_POR_RESET1 1 12 #define IMX7_RESET_A7_CORE_POR_RESET1 1 13 #define IMX7_RESET_A7_CORE_RESET0 2 13 #define IMX7_RESET_A7_CORE_RESET0 2 14 #define IMX7_RESET_A7_CORE_RESET1 3 14 #define IMX7_RESET_A7_CORE_RESET1 3 15 #define IMX7_RESET_A7_DBG_RESET0 4 15 #define IMX7_RESET_A7_DBG_RESET0 4 16 #define IMX7_RESET_A7_DBG_RESET1 5 16 #define IMX7_RESET_A7_DBG_RESET1 5 17 #define IMX7_RESET_A7_ETM_RESET0 6 17 #define IMX7_RESET_A7_ETM_RESET0 6 18 #define IMX7_RESET_A7_ETM_RESET1 7 18 #define IMX7_RESET_A7_ETM_RESET1 7 19 #define IMX7_RESET_A7_SOC_DBG_RESET 8 19 #define IMX7_RESET_A7_SOC_DBG_RESET 8 20 #define IMX7_RESET_A7_L2RESET 9 20 #define IMX7_RESET_A7_L2RESET 9 21 #define IMX7_RESET_SW_M4C_RST 10 21 #define IMX7_RESET_SW_M4C_RST 10 22 #define IMX7_RESET_SW_M4P_RST 11 22 #define IMX7_RESET_SW_M4P_RST 11 23 #define IMX7_RESET_EIM_RST 12 23 #define IMX7_RESET_EIM_RST 12 24 #define IMX7_RESET_HSICPHY_PORT_RST 13 24 #define IMX7_RESET_HSICPHY_PORT_RST 13 25 #define IMX7_RESET_USBPHY1_POR 14 25 #define IMX7_RESET_USBPHY1_POR 14 26 #define IMX7_RESET_USBPHY1_PORT_RST 15 26 #define IMX7_RESET_USBPHY1_PORT_RST 15 27 #define IMX7_RESET_USBPHY2_POR 16 27 #define IMX7_RESET_USBPHY2_POR 16 28 #define IMX7_RESET_USBPHY2_PORT_RST 17 28 #define IMX7_RESET_USBPHY2_PORT_RST 17 29 #define IMX7_RESET_MIPI_PHY_MRST 18 29 #define IMX7_RESET_MIPI_PHY_MRST 18 30 #define IMX7_RESET_MIPI_PHY_SRST 19 30 #define IMX7_RESET_MIPI_PHY_SRST 19 31 31 32 /* 32 /* 33 * IMX7_RESET_PCIEPHY is a logical reset line 33 * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN 34 * and PCIEPHY_G_RST 34 * and PCIEPHY_G_RST 35 */ 35 */ 36 #define IMX7_RESET_PCIEPHY 20 36 #define IMX7_RESET_PCIEPHY 20 37 #define IMX7_RESET_PCIEPHY_PERST 21 37 #define IMX7_RESET_PCIEPHY_PERST 21 38 38 39 /* 39 /* 40 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictl 40 * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it 41 * can be used to inhibit PCIe LTTSM, so, in a 41 * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht 42 * of as one 42 * of as one 43 */ 43 */ 44 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 44 #define IMX7_RESET_PCIE_CTRL_APPS_EN 22 45 #define IMX7_RESET_DDRC_PRST 23 45 #define IMX7_RESET_DDRC_PRST 23 46 #define IMX7_RESET_DDRC_CORE_RST 24 46 #define IMX7_RESET_DDRC_CORE_RST 24 47 47 48 #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 48 #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 49 49 50 #define IMX7_RESET_NUM 26 50 #define IMX7_RESET_NUM 26 51 51 52 #endif 52 #endif 53 53 54 54
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