1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (C) 2018 Zodiac Inflight Innovati 4 * 5 * Author: Andrey Smirnov <andrew.smirnov@gmai 6 */ 7 8 #ifndef DT_BINDING_RESET_IMX8MQ_H 9 #define DT_BINDING_RESET_IMX8MQ_H 10 11 #define IMX8MQ_RESET_A53_CORE_POR_RESET0 12 #define IMX8MQ_RESET_A53_CORE_POR_RESET1 13 #define IMX8MQ_RESET_A53_CORE_POR_RESET2 14 #define IMX8MQ_RESET_A53_CORE_POR_RESET3 15 #define IMX8MQ_RESET_A53_CORE_RESET0 16 #define IMX8MQ_RESET_A53_CORE_RESET1 17 #define IMX8MQ_RESET_A53_CORE_RESET2 18 #define IMX8MQ_RESET_A53_CORE_RESET3 19 #define IMX8MQ_RESET_A53_DBG_RESET0 20 #define IMX8MQ_RESET_A53_DBG_RESET1 21 #define IMX8MQ_RESET_A53_DBG_RESET2 22 #define IMX8MQ_RESET_A53_DBG_RESET3 23 #define IMX8MQ_RESET_A53_ETM_RESET0 24 #define IMX8MQ_RESET_A53_ETM_RESET1 25 #define IMX8MQ_RESET_A53_ETM_RESET2 26 #define IMX8MQ_RESET_A53_ETM_RESET3 27 #define IMX8MQ_RESET_A53_SOC_DBG_RESET 28 #define IMX8MQ_RESET_A53_L2RESET 29 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 30 #define IMX8MQ_RESET_OTG1_PHY_RESET 31 #define IMX8MQ_RESET_OTG2_PHY_RESET 32 #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 33 #define IMX8MQ_RESET_MIPI_DSI_RESET_N 34 #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 35 #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 36 #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 37 #define IMX8MQ_RESET_PCIEPHY 38 #define IMX8MQ_RESET_PCIEPHY_PERST 39 #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 40 #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 41 #define IMX8MQ_RESET_HDMI_PHY_APB_RESET 42 #define IMX8MQ_RESET_DISP_RESET 43 #define IMX8MQ_RESET_GPU_RESET 44 #define IMX8MQ_RESET_VPU_RESET 45 #define IMX8MQ_RESET_PCIEPHY2 46 #define IMX8MQ_RESET_PCIEPHY2_PERST 47 #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 48 #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 49 #define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 50 #define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 51 #define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 52 #define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 53 #define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 54 #define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 55 #define IMX8MQ_RESET_DDRC1_PRST 56 #define IMX8MQ_RESET_DDRC1_CORE_RESET 57 #define IMX8MQ_RESET_DDRC1_PHY_RESET 58 #define IMX8MQ_RESET_DDRC2_PRST 59 #define IMX8MQ_RESET_DDRC2_CORE_RESET 60 #define IMX8MQ_RESET_DDRC2_PHY_RESET 61 #define IMX8MQ_RESET_SW_M4C_RST 62 #define IMX8MQ_RESET_SW_M4P_RST 63 #define IMX8MQ_RESET_M4_ENABLE 64 65 #define IMX8MQ_RESET_NUM 66 67 #endif 68
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