1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2015 MediaTek, Shunli Wang <s 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 7 #define _DT_BINDINGS_RESET_CONTROLLER_MT2701 8 9 /* INFRACFG resets */ 10 #define MT2701_INFRA_EMI_REG_RST 11 #define MT2701_INFRA_DRAMC0_A0_RST 12 #define MT2701_INFRA_FHCTL_RST 13 #define MT2701_INFRA_APCIRQ_EINT_RST 14 #define MT2701_INFRA_APXGPT_RST 15 #define MT2701_INFRA_SCPSYS_RST 16 #define MT2701_INFRA_KP_RST 17 #define MT2701_INFRA_PMIC_WRAP_RST 18 #define MT2701_INFRA_MIPI_RST 19 #define MT2701_INFRA_IRRX_RST 20 #define MT2701_INFRA_CEC_RST 21 #define MT2701_INFRA_EMI_RST 22 #define MT2701_INFRA_DRAMC0_RST 23 #define MT2701_INFRA_TRNG_RST 24 #define MT2701_INFRA_SYSIRQ_RST 25 26 /* PERICFG resets */ 27 #define MT2701_PERI_UART0_SW_RST 28 #define MT2701_PERI_UART1_SW_RST 29 #define MT2701_PERI_UART2_SW_RST 30 #define MT2701_PERI_UART3_SW_RST 31 #define MT2701_PERI_GCPU_SW_RST 32 #define MT2701_PERI_BTIF_SW_RST 33 #define MT2701_PERI_PWM_SW_RST 34 #define MT2701_PERI_AUXADC_SW_RST 35 #define MT2701_PERI_DMA_SW_RST 36 #define MT2701_PERI_NFI_SW_RST 37 #define MT2701_PERI_NLI_SW_RST 38 #define MT2701_PERI_THERM_SW_RST 39 #define MT2701_PERI_MSDC2_SW_RST 40 #define MT2701_PERI_MSDC0_SW_RST 41 #define MT2701_PERI_MSDC1_SW_RST 42 #define MT2701_PERI_I2C0_SW_RST 43 #define MT2701_PERI_I2C1_SW_RST 44 #define MT2701_PERI_I2C2_SW_RST 45 #define MT2701_PERI_I2C3_SW_RST 46 #define MT2701_PERI_USB_SW_RST 47 #define MT2701_PERI_ETH_SW_RST 48 #define MT2701_PERI_SPI0_SW_RST 49 50 /* TOPRGU resets */ 51 #define MT2701_TOPRGU_INFRA_RST 52 #define MT2701_TOPRGU_MM_RST 53 #define MT2701_TOPRGU_MFG_RST 54 #define MT2701_TOPRGU_ETHDMA_RST 55 #define MT2701_TOPRGU_VDEC_RST 56 #define MT2701_TOPRGU_VENC_IMG_RST 57 #define MT2701_TOPRGU_DDRPHY_RST 58 #define MT2701_TOPRGU_MD_RST 59 #define MT2701_TOPRGU_INFRA_AO_RST 60 #define MT2701_TOPRGU_CONN_RST 61 #define MT2701_TOPRGU_APMIXED_RST 62 #define MT2701_TOPRGU_HIFSYS_RST 63 #define MT2701_TOPRGU_CONN_MCU_RST 64 #define MT2701_TOPRGU_BDP_DISP_RST 65 66 /* HIFSYS resets */ 67 #define MT2701_HIFSYS_UHOST0_RST 68 #define MT2701_HIFSYS_UHOST1_RST 69 #define MT2701_HIFSYS_UPHY0_RST 70 #define MT2701_HIFSYS_UPHY1_RST 71 #define MT2701_HIFSYS_PCIE0_RST 72 #define MT2701_HIFSYS_PCIE1_RST 73 #define MT2701_HIFSYS_PCIE2_RST 74 75 /* ETHSYS resets */ 76 #define MT2701_ETHSYS_SYS_RST 77 #define MT2701_ETHSYS_MCM_RST 78 #define MT2701_ETHSYS_FE_RST 79 #define MT2701_ETHSYS_GMAC_RST 80 #define MT2701_ETHSYS_PPE_RST 81 82 /* G3DSYS resets */ 83 #define MT2701_G3DSYS_CORE_RST 84 85 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT270 86
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