1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Runyang Chen <runyang.chen@mediatek 5 */ 6 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8188 9 10 #define MT8188_TOPRGU_CONN_MCU_SW_RST 11 #define MT8188_TOPRGU_INFRA_GRST_SW_RST 12 #define MT8188_TOPRGU_IPU0_SW_RST 13 #define MT8188_TOPRGU_IPU1_SW_RST 14 #define MT8188_TOPRGU_IPU2_SW_RST 15 #define MT8188_TOPRGU_AUD_ASRC_SW_RST 16 #define MT8188_TOPRGU_INFRA_SW_RST 17 #define MT8188_TOPRGU_MMSYS_SW_RST 18 #define MT8188_TOPRGU_MFG_SW_RST 19 #define MT8188_TOPRGU_VENC_SW_RST 20 #define MT8188_TOPRGU_VDEC_SW_RST 21 #define MT8188_TOPRGU_CAM_VCORE_SW_RST 22 #define MT8188_TOPRGU_SCP_SW_RST 23 #define MT8188_TOPRGU_APMIXEDSYS_SW_RST 24 #define MT8188_TOPRGU_AUDIO_SW_RST 25 #define MT8188_TOPRGU_CAMSYS_SW_RST 26 #define MT8188_TOPRGU_MJC_SW_RST 27 #define MT8188_TOPRGU_PERI_SW_RST 28 #define MT8188_TOPRGU_PERI_AO_SW_RST 29 #define MT8188_TOPRGU_PCIE_SW_RST 30 #define MT8188_TOPRGU_ADSPSYS_SW_RST 31 #define MT8188_TOPRGU_DPTX_SW_RST 32 #define MT8188_TOPRGU_SPMI_MST_SW_RST 33 34 #define MT8188_TOPRGU_SW_RST_NUM 35 36 /* INFRA resets */ 37 #define MT8188_INFRA_RST1_THERMAL_MCU_RST 38 #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 39 #define MT8188_INFRA_RST3_PTP_CTRL_RST 40 41 #define MT8188_VDO0_RST_DISP_OVL0 42 #define MT8188_VDO0_RST_FAKE_ENG0 43 #define MT8188_VDO0_RST_DISP_CCORR0 44 #define MT8188_VDO0_RST_DISP_MUTEX0 45 #define MT8188_VDO0_RST_DISP_GAMMA0 46 #define MT8188_VDO0_RST_DISP_DITHER0 47 #define MT8188_VDO0_RST_DISP_WDMA0 48 #define MT8188_VDO0_RST_DISP_RDMA0 49 #define MT8188_VDO0_RST_DSI0 50 #define MT8188_VDO0_RST_DSI1 51 #define MT8188_VDO0_RST_DSC_WRAP0 52 #define MT8188_VDO0_RST_VPP_MERGE0 53 #define MT8188_VDO0_RST_DP_INTF0 54 #define MT8188_VDO0_RST_DISP_AAL0 55 #define MT8188_VDO0_RST_INLINEROT0 56 #define MT8188_VDO0_RST_APB_BUS 57 #define MT8188_VDO0_RST_DISP_COLOR0 58 #define MT8188_VDO0_RST_MDP_WROT0 59 #define MT8188_VDO0_RST_DISP_RSZ0 60 61 #define MT8188_VDO1_RST_SMI_LARB2 62 #define MT8188_VDO1_RST_SMI_LARB3 63 #define MT8188_VDO1_RST_GALS 64 #define MT8188_VDO1_RST_FAKE_ENG0 65 #define MT8188_VDO1_RST_FAKE_ENG1 66 #define MT8188_VDO1_RST_MDP_RDMA0 67 #define MT8188_VDO1_RST_MDP_RDMA1 68 #define MT8188_VDO1_RST_MDP_RDMA2 69 #define MT8188_VDO1_RST_MDP_RDMA3 70 #define MT8188_VDO1_RST_VPP_MERGE0 71 #define MT8188_VDO1_RST_VPP_MERGE1 72 #define MT8188_VDO1_RST_VPP_MERGE2 73 #define MT8188_VDO1_RST_VPP_MERGE3 74 #define MT8188_VDO1_RST_VPP_MERGE4 75 #define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 76 #define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 77 #define MT8188_VDO1_RST_DISP_MUTEX 78 #define MT8188_VDO1_RST_MDP_RDMA4 79 #define MT8188_VDO1_RST_MDP_RDMA5 80 #define MT8188_VDO1_RST_MDP_RDMA6 81 #define MT8188_VDO1_RST_MDP_RDMA7 82 #define MT8188_VDO1_RST_DP_INTF1_MMCK 83 #define MT8188_VDO1_RST_DPI0_MM_CK 84 #define MT8188_VDO1_RST_DPI1_MM_CK 85 #define MT8188_VDO1_RST_MERGE0_DL_ASYNC 86 #define MT8188_VDO1_RST_MERGE1_DL_ASYNC 87 #define MT8188_VDO1_RST_MERGE2_DL_ASYNC 88 #define MT8188_VDO1_RST_MERGE3_DL_ASYNC 89 #define MT8188_VDO1_RST_MERGE4_DL_ASYNC 90 #define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_AS 91 #define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ 92 #define MT8188_VDO1_RST_PADDING0 93 #define MT8188_VDO1_RST_PADDING1 94 #define MT8188_VDO1_RST_PADDING2 95 #define MT8188_VDO1_RST_PADDING3 96 #define MT8188_VDO1_RST_PADDING4 97 #define MT8188_VDO1_RST_PADDING5 98 #define MT8188_VDO1_RST_PADDING6 99 #define MT8188_VDO1_RST_PADDING7 100 #define MT8188_VDO1_RST_DISP_RSZ0 101 #define MT8188_VDO1_RST_DISP_RSZ1 102 #define MT8188_VDO1_RST_DISP_RSZ2 103 #define MT8188_VDO1_RST_DISP_RSZ3 104 #define MT8188_VDO1_RST_HDR_VDO_FE0 105 #define MT8188_VDO1_RST_HDR_GFX_FE0 106 #define MT8188_VDO1_RST_HDR_VDO_BE 107 #define MT8188_VDO1_RST_HDR_VDO_FE1 108 #define MT8188_VDO1_RST_HDR_GFX_FE1 109 #define MT8188_VDO1_RST_DISP_MIXER 110 #define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 111 #define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 112 #define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 113 #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 114 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 115 116 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT818 117
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