1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ 2 /* 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Runyang Chen <runyang.chen@mediatek 4 * Author: Runyang Chen <runyang.chen@mediatek.com> 5 */ 5 */ 6 6 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8188 8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8188 9 9 10 #define MT8188_TOPRGU_CONN_MCU_SW_RST 10 #define MT8188_TOPRGU_CONN_MCU_SW_RST 0 11 #define MT8188_TOPRGU_INFRA_GRST_SW_RST 11 #define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 12 #define MT8188_TOPRGU_IPU0_SW_RST 12 #define MT8188_TOPRGU_IPU0_SW_RST 2 13 #define MT8188_TOPRGU_IPU1_SW_RST 13 #define MT8188_TOPRGU_IPU1_SW_RST 3 14 #define MT8188_TOPRGU_IPU2_SW_RST 14 #define MT8188_TOPRGU_IPU2_SW_RST 4 15 #define MT8188_TOPRGU_AUD_ASRC_SW_RST 15 #define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 16 #define MT8188_TOPRGU_INFRA_SW_RST 16 #define MT8188_TOPRGU_INFRA_SW_RST 6 17 #define MT8188_TOPRGU_MMSYS_SW_RST 17 #define MT8188_TOPRGU_MMSYS_SW_RST 7 18 #define MT8188_TOPRGU_MFG_SW_RST 18 #define MT8188_TOPRGU_MFG_SW_RST 8 19 #define MT8188_TOPRGU_VENC_SW_RST 19 #define MT8188_TOPRGU_VENC_SW_RST 9 20 #define MT8188_TOPRGU_VDEC_SW_RST 20 #define MT8188_TOPRGU_VDEC_SW_RST 10 21 #define MT8188_TOPRGU_CAM_VCORE_SW_RST 21 #define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 22 #define MT8188_TOPRGU_SCP_SW_RST 22 #define MT8188_TOPRGU_SCP_SW_RST 12 23 #define MT8188_TOPRGU_APMIXEDSYS_SW_RST 23 #define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 24 #define MT8188_TOPRGU_AUDIO_SW_RST 24 #define MT8188_TOPRGU_AUDIO_SW_RST 14 25 #define MT8188_TOPRGU_CAMSYS_SW_RST 25 #define MT8188_TOPRGU_CAMSYS_SW_RST 15 26 #define MT8188_TOPRGU_MJC_SW_RST 26 #define MT8188_TOPRGU_MJC_SW_RST 16 27 #define MT8188_TOPRGU_PERI_SW_RST 27 #define MT8188_TOPRGU_PERI_SW_RST 17 28 #define MT8188_TOPRGU_PERI_AO_SW_RST 28 #define MT8188_TOPRGU_PERI_AO_SW_RST 18 29 #define MT8188_TOPRGU_PCIE_SW_RST 29 #define MT8188_TOPRGU_PCIE_SW_RST 19 30 #define MT8188_TOPRGU_ADSPSYS_SW_RST 30 #define MT8188_TOPRGU_ADSPSYS_SW_RST 21 31 #define MT8188_TOPRGU_DPTX_SW_RST 31 #define MT8188_TOPRGU_DPTX_SW_RST 22 32 #define MT8188_TOPRGU_SPMI_MST_SW_RST 32 #define MT8188_TOPRGU_SPMI_MST_SW_RST 23 33 33 34 #define MT8188_TOPRGU_SW_RST_NUM 34 #define MT8188_TOPRGU_SW_RST_NUM 24 35 35 36 /* INFRA resets */ 36 /* INFRA resets */ 37 #define MT8188_INFRA_RST1_THERMAL_MCU_RST 37 #define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 38 #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 38 #define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 39 #define MT8188_INFRA_RST3_PTP_CTRL_RST 39 #define MT8188_INFRA_RST3_PTP_CTRL_RST 2 40 40 41 #define MT8188_VDO0_RST_DISP_OVL0 41 #define MT8188_VDO0_RST_DISP_OVL0 0 42 #define MT8188_VDO0_RST_FAKE_ENG0 42 #define MT8188_VDO0_RST_FAKE_ENG0 1 43 #define MT8188_VDO0_RST_DISP_CCORR0 43 #define MT8188_VDO0_RST_DISP_CCORR0 2 44 #define MT8188_VDO0_RST_DISP_MUTEX0 44 #define MT8188_VDO0_RST_DISP_MUTEX0 3 45 #define MT8188_VDO0_RST_DISP_GAMMA0 45 #define MT8188_VDO0_RST_DISP_GAMMA0 4 46 #define MT8188_VDO0_RST_DISP_DITHER0 46 #define MT8188_VDO0_RST_DISP_DITHER0 5 47 #define MT8188_VDO0_RST_DISP_WDMA0 47 #define MT8188_VDO0_RST_DISP_WDMA0 6 48 #define MT8188_VDO0_RST_DISP_RDMA0 48 #define MT8188_VDO0_RST_DISP_RDMA0 7 49 #define MT8188_VDO0_RST_DSI0 49 #define MT8188_VDO0_RST_DSI0 8 50 #define MT8188_VDO0_RST_DSI1 50 #define MT8188_VDO0_RST_DSI1 9 51 #define MT8188_VDO0_RST_DSC_WRAP0 51 #define MT8188_VDO0_RST_DSC_WRAP0 10 52 #define MT8188_VDO0_RST_VPP_MERGE0 52 #define MT8188_VDO0_RST_VPP_MERGE0 11 53 #define MT8188_VDO0_RST_DP_INTF0 53 #define MT8188_VDO0_RST_DP_INTF0 12 54 #define MT8188_VDO0_RST_DISP_AAL0 54 #define MT8188_VDO0_RST_DISP_AAL0 13 55 #define MT8188_VDO0_RST_INLINEROT0 55 #define MT8188_VDO0_RST_INLINEROT0 14 56 #define MT8188_VDO0_RST_APB_BUS 56 #define MT8188_VDO0_RST_APB_BUS 15 57 #define MT8188_VDO0_RST_DISP_COLOR0 57 #define MT8188_VDO0_RST_DISP_COLOR0 16 58 #define MT8188_VDO0_RST_MDP_WROT0 58 #define MT8188_VDO0_RST_MDP_WROT0 17 59 #define MT8188_VDO0_RST_DISP_RSZ0 59 #define MT8188_VDO0_RST_DISP_RSZ0 18 60 60 61 #define MT8188_VDO1_RST_SMI_LARB2 61 #define MT8188_VDO1_RST_SMI_LARB2 0 62 #define MT8188_VDO1_RST_SMI_LARB3 62 #define MT8188_VDO1_RST_SMI_LARB3 1 63 #define MT8188_VDO1_RST_GALS 63 #define MT8188_VDO1_RST_GALS 2 64 #define MT8188_VDO1_RST_FAKE_ENG0 64 #define MT8188_VDO1_RST_FAKE_ENG0 3 65 #define MT8188_VDO1_RST_FAKE_ENG1 65 #define MT8188_VDO1_RST_FAKE_ENG1 4 66 #define MT8188_VDO1_RST_MDP_RDMA0 66 #define MT8188_VDO1_RST_MDP_RDMA0 5 67 #define MT8188_VDO1_RST_MDP_RDMA1 67 #define MT8188_VDO1_RST_MDP_RDMA1 6 68 #define MT8188_VDO1_RST_MDP_RDMA2 68 #define MT8188_VDO1_RST_MDP_RDMA2 7 69 #define MT8188_VDO1_RST_MDP_RDMA3 69 #define MT8188_VDO1_RST_MDP_RDMA3 8 70 #define MT8188_VDO1_RST_VPP_MERGE0 70 #define MT8188_VDO1_RST_VPP_MERGE0 9 71 #define MT8188_VDO1_RST_VPP_MERGE1 71 #define MT8188_VDO1_RST_VPP_MERGE1 10 72 #define MT8188_VDO1_RST_VPP_MERGE2 72 #define MT8188_VDO1_RST_VPP_MERGE2 11 73 #define MT8188_VDO1_RST_VPP_MERGE3 73 #define MT8188_VDO1_RST_VPP_MERGE3 12 74 #define MT8188_VDO1_RST_VPP_MERGE4 74 #define MT8188_VDO1_RST_VPP_MERGE4 13 75 #define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 75 #define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 76 #define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 76 #define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 77 #define MT8188_VDO1_RST_DISP_MUTEX 77 #define MT8188_VDO1_RST_DISP_MUTEX 16 78 #define MT8188_VDO1_RST_MDP_RDMA4 78 #define MT8188_VDO1_RST_MDP_RDMA4 17 79 #define MT8188_VDO1_RST_MDP_RDMA5 79 #define MT8188_VDO1_RST_MDP_RDMA5 18 80 #define MT8188_VDO1_RST_MDP_RDMA6 80 #define MT8188_VDO1_RST_MDP_RDMA6 19 81 #define MT8188_VDO1_RST_MDP_RDMA7 81 #define MT8188_VDO1_RST_MDP_RDMA7 20 82 #define MT8188_VDO1_RST_DP_INTF1_MMCK 82 #define MT8188_VDO1_RST_DP_INTF1_MMCK 21 83 #define MT8188_VDO1_RST_DPI0_MM_CK 83 #define MT8188_VDO1_RST_DPI0_MM_CK 22 84 #define MT8188_VDO1_RST_DPI1_MM_CK 84 #define MT8188_VDO1_RST_DPI1_MM_CK 23 85 #define MT8188_VDO1_RST_MERGE0_DL_ASYNC 85 #define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 86 #define MT8188_VDO1_RST_MERGE1_DL_ASYNC 86 #define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 87 #define MT8188_VDO1_RST_MERGE2_DL_ASYNC 87 #define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 88 #define MT8188_VDO1_RST_MERGE3_DL_ASYNC 88 #define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 89 #define MT8188_VDO1_RST_MERGE4_DL_ASYNC 89 #define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 90 #define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_AS 90 #define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 91 #define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ 91 #define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 92 #define MT8188_VDO1_RST_PADDING0 92 #define MT8188_VDO1_RST_PADDING0 31 93 #define MT8188_VDO1_RST_PADDING1 93 #define MT8188_VDO1_RST_PADDING1 32 94 #define MT8188_VDO1_RST_PADDING2 94 #define MT8188_VDO1_RST_PADDING2 33 95 #define MT8188_VDO1_RST_PADDING3 95 #define MT8188_VDO1_RST_PADDING3 34 96 #define MT8188_VDO1_RST_PADDING4 96 #define MT8188_VDO1_RST_PADDING4 35 97 #define MT8188_VDO1_RST_PADDING5 97 #define MT8188_VDO1_RST_PADDING5 36 98 #define MT8188_VDO1_RST_PADDING6 98 #define MT8188_VDO1_RST_PADDING6 37 99 #define MT8188_VDO1_RST_PADDING7 99 #define MT8188_VDO1_RST_PADDING7 38 100 #define MT8188_VDO1_RST_DISP_RSZ0 100 #define MT8188_VDO1_RST_DISP_RSZ0 39 101 #define MT8188_VDO1_RST_DISP_RSZ1 101 #define MT8188_VDO1_RST_DISP_RSZ1 40 102 #define MT8188_VDO1_RST_DISP_RSZ2 102 #define MT8188_VDO1_RST_DISP_RSZ2 41 103 #define MT8188_VDO1_RST_DISP_RSZ3 103 #define MT8188_VDO1_RST_DISP_RSZ3 42 104 #define MT8188_VDO1_RST_HDR_VDO_FE0 104 #define MT8188_VDO1_RST_HDR_VDO_FE0 43 105 #define MT8188_VDO1_RST_HDR_GFX_FE0 105 #define MT8188_VDO1_RST_HDR_GFX_FE0 44 106 #define MT8188_VDO1_RST_HDR_VDO_BE 106 #define MT8188_VDO1_RST_HDR_VDO_BE 45 107 #define MT8188_VDO1_RST_HDR_VDO_FE1 107 #define MT8188_VDO1_RST_HDR_VDO_FE1 46 108 #define MT8188_VDO1_RST_HDR_GFX_FE1 108 #define MT8188_VDO1_RST_HDR_GFX_FE1 47 109 #define MT8188_VDO1_RST_DISP_MIXER 109 #define MT8188_VDO1_RST_DISP_MIXER 48 110 #define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 110 #define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 111 #define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 111 #define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 112 #define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 112 #define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 113 #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 113 #define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 114 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 114 #define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 115 115 116 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT818 116 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ 117 117
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