1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright 2015 Linaro Limited 3 * Copyright 2015 Linaro Limited 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H 6 #ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H 7 #define _DT_BINDINGS_RESET_MSM_GCC_8916_H 7 #define _DT_BINDINGS_RESET_MSM_GCC_8916_H 8 8 9 #define GCC_BLSP1_BCR 0 9 #define GCC_BLSP1_BCR 0 10 #define GCC_BLSP1_QUP1_BCR 1 10 #define GCC_BLSP1_QUP1_BCR 1 11 #define GCC_BLSP1_UART1_BCR 2 11 #define GCC_BLSP1_UART1_BCR 2 12 #define GCC_BLSP1_QUP2_BCR 3 12 #define GCC_BLSP1_QUP2_BCR 3 13 #define GCC_BLSP1_UART2_BCR 4 13 #define GCC_BLSP1_UART2_BCR 4 14 #define GCC_BLSP1_QUP3_BCR 5 14 #define GCC_BLSP1_QUP3_BCR 5 15 #define GCC_BLSP1_QUP4_BCR 6 15 #define GCC_BLSP1_QUP4_BCR 6 16 #define GCC_BLSP1_QUP5_BCR 7 16 #define GCC_BLSP1_QUP5_BCR 7 17 #define GCC_BLSP1_QUP6_BCR 8 17 #define GCC_BLSP1_QUP6_BCR 8 18 #define GCC_IMEM_BCR 9 18 #define GCC_IMEM_BCR 9 19 #define GCC_SMMU_BCR 10 19 #define GCC_SMMU_BCR 10 20 #define GCC_APSS_TCU_BCR 11 20 #define GCC_APSS_TCU_BCR 11 21 #define GCC_SMMU_XPU_BCR 12 21 #define GCC_SMMU_XPU_BCR 12 22 #define GCC_PCNOC_TBU_BCR 13 22 #define GCC_PCNOC_TBU_BCR 13 23 #define GCC_PRNG_BCR 14 23 #define GCC_PRNG_BCR 14 24 #define GCC_BOOT_ROM_BCR 15 24 #define GCC_BOOT_ROM_BCR 15 25 #define GCC_CRYPTO_BCR 16 25 #define GCC_CRYPTO_BCR 16 26 #define GCC_SEC_CTRL_BCR 17 26 #define GCC_SEC_CTRL_BCR 17 27 #define GCC_AUDIO_CORE_BCR 18 27 #define GCC_AUDIO_CORE_BCR 18 28 #define GCC_ULT_AUDIO_BCR 19 28 #define GCC_ULT_AUDIO_BCR 19 29 #define GCC_DEHR_BCR 20 29 #define GCC_DEHR_BCR 20 30 #define GCC_SYSTEM_NOC_BCR 21 30 #define GCC_SYSTEM_NOC_BCR 21 31 #define GCC_PCNOC_BCR 22 31 #define GCC_PCNOC_BCR 22 32 #define GCC_TCSR_BCR 23 32 #define GCC_TCSR_BCR 23 33 #define GCC_QDSS_BCR 24 33 #define GCC_QDSS_BCR 24 34 #define GCC_DCD_BCR 25 34 #define GCC_DCD_BCR 25 35 #define GCC_MSG_RAM_BCR 26 35 #define GCC_MSG_RAM_BCR 26 36 #define GCC_MPM_BCR 27 36 #define GCC_MPM_BCR 27 37 #define GCC_SPMI_BCR 28 37 #define GCC_SPMI_BCR 28 38 #define GCC_SPDM_BCR 29 38 #define GCC_SPDM_BCR 29 39 #define GCC_MM_SPDM_BCR 30 39 #define GCC_MM_SPDM_BCR 30 40 #define GCC_BIMC_BCR 31 40 #define GCC_BIMC_BCR 31 41 #define GCC_RBCPR_BCR 32 41 #define GCC_RBCPR_BCR 32 42 #define GCC_TLMM_BCR 33 42 #define GCC_TLMM_BCR 33 43 #define GCC_USB_HS_BCR 34 43 #define GCC_USB_HS_BCR 34 44 #define GCC_USB2A_PHY_BCR 35 44 #define GCC_USB2A_PHY_BCR 35 45 #define GCC_SDCC1_BCR 36 45 #define GCC_SDCC1_BCR 36 46 #define GCC_SDCC2_BCR 37 46 #define GCC_SDCC2_BCR 37 47 #define GCC_PDM_BCR 38 47 #define GCC_PDM_BCR 38 48 #define GCC_SNOC_BUS_TIMEOUT0_BCR 39 48 #define GCC_SNOC_BUS_TIMEOUT0_BCR 39 49 #define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 49 #define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 50 #define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 50 #define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 51 #define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 51 #define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 52 #define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 52 #define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 53 #define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 53 #define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 54 #define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 54 #define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 55 #define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 55 #define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 56 #define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 56 #define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 57 #define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 57 #define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 58 #define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 58 #define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 59 #define GCC_MMSS_BCR 50 59 #define GCC_MMSS_BCR 50 60 #define GCC_VENUS0_BCR 51 60 #define GCC_VENUS0_BCR 51 61 #define GCC_MDSS_BCR 52 61 #define GCC_MDSS_BCR 52 62 #define GCC_CAMSS_PHY0_BCR 53 62 #define GCC_CAMSS_PHY0_BCR 53 63 #define GCC_CAMSS_CSI0_BCR 54 63 #define GCC_CAMSS_CSI0_BCR 54 64 #define GCC_CAMSS_CSI0PHY_BCR 55 64 #define GCC_CAMSS_CSI0PHY_BCR 55 65 #define GCC_CAMSS_CSI0RDI_BCR 56 65 #define GCC_CAMSS_CSI0RDI_BCR 56 66 #define GCC_CAMSS_CSI0PIX_BCR 57 66 #define GCC_CAMSS_CSI0PIX_BCR 57 67 #define GCC_CAMSS_PHY1_BCR 58 67 #define GCC_CAMSS_PHY1_BCR 58 68 #define GCC_CAMSS_CSI1_BCR 59 68 #define GCC_CAMSS_CSI1_BCR 59 69 #define GCC_CAMSS_CSI1PHY_BCR 60 69 #define GCC_CAMSS_CSI1PHY_BCR 60 70 #define GCC_CAMSS_CSI1RDI_BCR 61 70 #define GCC_CAMSS_CSI1RDI_BCR 61 71 #define GCC_CAMSS_CSI1PIX_BCR 62 71 #define GCC_CAMSS_CSI1PIX_BCR 62 72 #define GCC_CAMSS_ISPIF_BCR 63 72 #define GCC_CAMSS_ISPIF_BCR 63 73 #define GCC_CAMSS_CCI_BCR 64 73 #define GCC_CAMSS_CCI_BCR 64 74 #define GCC_CAMSS_MCLK0_BCR 65 74 #define GCC_CAMSS_MCLK0_BCR 65 75 #define GCC_CAMSS_MCLK1_BCR 66 75 #define GCC_CAMSS_MCLK1_BCR 66 76 #define GCC_CAMSS_GP0_BCR 67 76 #define GCC_CAMSS_GP0_BCR 67 77 #define GCC_CAMSS_GP1_BCR 68 77 #define GCC_CAMSS_GP1_BCR 68 78 #define GCC_CAMSS_TOP_BCR 69 78 #define GCC_CAMSS_TOP_BCR 69 79 #define GCC_CAMSS_MICRO_BCR 70 79 #define GCC_CAMSS_MICRO_BCR 70 80 #define GCC_CAMSS_JPEG_BCR 71 80 #define GCC_CAMSS_JPEG_BCR 71 81 #define GCC_CAMSS_VFE_BCR 72 81 #define GCC_CAMSS_VFE_BCR 72 82 #define GCC_CAMSS_CSI_VFE0_BCR 73 82 #define GCC_CAMSS_CSI_VFE0_BCR 73 83 #define GCC_OXILI_BCR 74 83 #define GCC_OXILI_BCR 74 84 #define GCC_GMEM_BCR 75 84 #define GCC_GMEM_BCR 75 85 #define GCC_CAMSS_AHB_BCR 76 85 #define GCC_CAMSS_AHB_BCR 76 86 #define GCC_MDP_TBU_BCR 77 86 #define GCC_MDP_TBU_BCR 77 87 #define GCC_GFX_TBU_BCR 78 87 #define GCC_GFX_TBU_BCR 78 88 #define GCC_GFX_TCU_BCR 79 88 #define GCC_GFX_TCU_BCR 79 89 #define GCC_MSS_TBU_AXI_BCR 80 89 #define GCC_MSS_TBU_AXI_BCR 80 90 #define GCC_MSS_TBU_GSS_AXI_BCR 81 90 #define GCC_MSS_TBU_GSS_AXI_BCR 81 91 #define GCC_MSS_TBU_Q6_AXI_BCR 82 91 #define GCC_MSS_TBU_Q6_AXI_BCR 82 92 #define GCC_GTCU_AHB_BCR 83 92 #define GCC_GTCU_AHB_BCR 83 93 #define GCC_SMMU_CFG_BCR 84 93 #define GCC_SMMU_CFG_BCR 84 94 #define GCC_VFE_TBU_BCR 85 94 #define GCC_VFE_TBU_BCR 85 95 #define GCC_VENUS_TBU_BCR 86 95 #define GCC_VENUS_TBU_BCR 86 96 #define GCC_JPEG_TBU_BCR 87 96 #define GCC_JPEG_TBU_BCR 87 97 #define GCC_PRONTO_TBU_BCR 88 97 #define GCC_PRONTO_TBU_BCR 88 98 #define GCC_SMMU_CATS_BCR 89 98 #define GCC_SMMU_CATS_BCR 89 99 99 100 #endif 100 #endif 101 101
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