1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 2 /* 3 * Copyright (c) 2013, The Linux Foundation. A 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H 6 #ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H 7 #define _DT_BINDINGS_RESET_MSM_GCC_8960_H 7 #define _DT_BINDINGS_RESET_MSM_GCC_8960_H 8 8 9 #define SFAB_MSS_Q6_SW_RESET 9 #define SFAB_MSS_Q6_SW_RESET 0 10 #define SFAB_MSS_Q6_FW_RESET 10 #define SFAB_MSS_Q6_FW_RESET 1 11 #define QDSS_STM_RESET 11 #define QDSS_STM_RESET 2 12 #define AFAB_SMPSS_S_RESET 12 #define AFAB_SMPSS_S_RESET 3 13 #define AFAB_SMPSS_M1_RESET 13 #define AFAB_SMPSS_M1_RESET 4 14 #define AFAB_SMPSS_M0_RESET 14 #define AFAB_SMPSS_M0_RESET 5 15 #define AFAB_EBI1_CH0_RESET 15 #define AFAB_EBI1_CH0_RESET 6 16 #define AFAB_EBI1_CH1_RESET 16 #define AFAB_EBI1_CH1_RESET 7 17 #define SFAB_ADM0_M0_RESET 17 #define SFAB_ADM0_M0_RESET 8 18 #define SFAB_ADM0_M1_RESET 18 #define SFAB_ADM0_M1_RESET 9 19 #define SFAB_ADM0_M2_RESET 19 #define SFAB_ADM0_M2_RESET 10 20 #define ADM0_C2_RESET 20 #define ADM0_C2_RESET 11 21 #define ADM0_C1_RESET 21 #define ADM0_C1_RESET 12 22 #define ADM0_C0_RESET 22 #define ADM0_C0_RESET 13 23 #define ADM0_PBUS_RESET 23 #define ADM0_PBUS_RESET 14 24 #define ADM0_RESET 24 #define ADM0_RESET 15 25 #define QDSS_CLKS_SW_RESET 25 #define QDSS_CLKS_SW_RESET 16 26 #define QDSS_POR_RESET 26 #define QDSS_POR_RESET 17 27 #define QDSS_TSCTR_RESET 27 #define QDSS_TSCTR_RESET 18 28 #define QDSS_HRESET_RESET 28 #define QDSS_HRESET_RESET 19 29 #define QDSS_AXI_RESET 29 #define QDSS_AXI_RESET 20 30 #define QDSS_DBG_RESET 30 #define QDSS_DBG_RESET 21 31 #define PCIE_A_RESET 31 #define PCIE_A_RESET 22 32 #define PCIE_AUX_RESET 32 #define PCIE_AUX_RESET 23 33 #define PCIE_H_RESET 33 #define PCIE_H_RESET 24 34 #define SFAB_PCIE_M_RESET 34 #define SFAB_PCIE_M_RESET 25 35 #define SFAB_PCIE_S_RESET 35 #define SFAB_PCIE_S_RESET 26 36 #define SFAB_MSS_M_RESET 36 #define SFAB_MSS_M_RESET 27 37 #define SFAB_USB3_M_RESET 37 #define SFAB_USB3_M_RESET 28 38 #define SFAB_RIVA_M_RESET 38 #define SFAB_RIVA_M_RESET 29 39 #define SFAB_LPASS_RESET 39 #define SFAB_LPASS_RESET 30 40 #define SFAB_AFAB_M_RESET 40 #define SFAB_AFAB_M_RESET 31 41 #define AFAB_SFAB_M0_RESET 41 #define AFAB_SFAB_M0_RESET 32 42 #define AFAB_SFAB_M1_RESET 42 #define AFAB_SFAB_M1_RESET 33 43 #define SFAB_SATA_S_RESET 43 #define SFAB_SATA_S_RESET 34 44 #define SFAB_DFAB_M_RESET 44 #define SFAB_DFAB_M_RESET 35 45 #define DFAB_SFAB_M_RESET 45 #define DFAB_SFAB_M_RESET 36 46 #define DFAB_SWAY0_RESET 46 #define DFAB_SWAY0_RESET 37 47 #define DFAB_SWAY1_RESET 47 #define DFAB_SWAY1_RESET 38 48 #define DFAB_ARB0_RESET 48 #define DFAB_ARB0_RESET 39 49 #define DFAB_ARB1_RESET 49 #define DFAB_ARB1_RESET 40 50 #define PPSS_PROC_RESET 50 #define PPSS_PROC_RESET 41 51 #define PPSS_RESET 51 #define PPSS_RESET 42 52 #define DMA_BAM_RESET 52 #define DMA_BAM_RESET 43 53 #define SPS_TIC_H_RESET 53 #define SPS_TIC_H_RESET 44 54 #define SLIMBUS_H_RESET 54 #define SLIMBUS_H_RESET 45 55 #define SFAB_CFPB_M_RESET 55 #define SFAB_CFPB_M_RESET 46 56 #define SFAB_CFPB_S_RESET 56 #define SFAB_CFPB_S_RESET 47 57 #define TSIF_H_RESET 57 #define TSIF_H_RESET 48 58 #define CE1_H_RESET 58 #define CE1_H_RESET 49 59 #define CE1_CORE_RESET 59 #define CE1_CORE_RESET 50 60 #define CE1_SLEEP_RESET 60 #define CE1_SLEEP_RESET 51 61 #define CE2_H_RESET 61 #define CE2_H_RESET 52 62 #define CE2_CORE_RESET 62 #define CE2_CORE_RESET 53 63 #define SFAB_SFPB_M_RESET 63 #define SFAB_SFPB_M_RESET 54 64 #define SFAB_SFPB_S_RESET 64 #define SFAB_SFPB_S_RESET 55 65 #define RPM_PROC_RESET 65 #define RPM_PROC_RESET 56 66 #define PMIC_SSBI2_RESET 66 #define PMIC_SSBI2_RESET 57 67 #define SDC1_RESET 67 #define SDC1_RESET 58 68 #define SDC2_RESET 68 #define SDC2_RESET 59 69 #define SDC3_RESET 69 #define SDC3_RESET 60 70 #define SDC4_RESET 70 #define SDC4_RESET 61 71 #define SDC5_RESET 71 #define SDC5_RESET 62 72 #define DFAB_A2_RESET 72 #define DFAB_A2_RESET 63 73 #define USB_HS1_RESET 73 #define USB_HS1_RESET 64 74 #define USB_HSIC_RESET 74 #define USB_HSIC_RESET 65 75 #define USB_FS1_XCVR_RESET 75 #define USB_FS1_XCVR_RESET 66 76 #define USB_FS1_RESET 76 #define USB_FS1_RESET 67 77 #define USB_FS2_XCVR_RESET 77 #define USB_FS2_XCVR_RESET 68 78 #define USB_FS2_RESET 78 #define USB_FS2_RESET 69 79 #define GSBI1_RESET 79 #define GSBI1_RESET 70 80 #define GSBI2_RESET 80 #define GSBI2_RESET 71 81 #define GSBI3_RESET 81 #define GSBI3_RESET 72 82 #define GSBI4_RESET 82 #define GSBI4_RESET 73 83 #define GSBI5_RESET 83 #define GSBI5_RESET 74 84 #define GSBI6_RESET 84 #define GSBI6_RESET 75 85 #define GSBI7_RESET 85 #define GSBI7_RESET 76 86 #define GSBI8_RESET 86 #define GSBI8_RESET 77 87 #define GSBI9_RESET 87 #define GSBI9_RESET 78 88 #define GSBI10_RESET 88 #define GSBI10_RESET 79 89 #define GSBI11_RESET 89 #define GSBI11_RESET 80 90 #define GSBI12_RESET 90 #define GSBI12_RESET 81 91 #define SPDM_RESET 91 #define SPDM_RESET 82 92 #define TLMM_H_RESET 92 #define TLMM_H_RESET 83 93 #define SFAB_MSS_S_RESET 93 #define SFAB_MSS_S_RESET 84 94 #define MSS_SLP_RESET 94 #define MSS_SLP_RESET 85 95 #define MSS_Q6SW_JTAG_RESET 95 #define MSS_Q6SW_JTAG_RESET 86 96 #define MSS_Q6FW_JTAG_RESET 96 #define MSS_Q6FW_JTAG_RESET 87 97 #define MSS_RESET 97 #define MSS_RESET 88 98 #define SATA_H_RESET 98 #define SATA_H_RESET 89 99 #define SATA_RXOOB_RESE 99 #define SATA_RXOOB_RESE 90 100 #define SATA_PMALIVE_RESET 100 #define SATA_PMALIVE_RESET 91 101 #define SATA_SFAB_M_RESET 101 #define SATA_SFAB_M_RESET 92 102 #define TSSC_RESET 102 #define TSSC_RESET 93 103 #define PDM_RESET 103 #define PDM_RESET 94 104 #define MPM_H_RESET 104 #define MPM_H_RESET 95 105 #define MPM_RESET 105 #define MPM_RESET 96 106 #define SFAB_SMPSS_S_RESET 106 #define SFAB_SMPSS_S_RESET 97 107 #define PRNG_RESET 107 #define PRNG_RESET 98 108 #define RIVA_RESET 108 #define RIVA_RESET 99 109 #define USB_HS3_RESET 109 #define USB_HS3_RESET 100 110 #define USB_HS4_RESET 110 #define USB_HS4_RESET 101 111 #define CE3_RESET 111 #define CE3_RESET 102 112 #define PCIE_EXT_PCI_RESET 112 #define PCIE_EXT_PCI_RESET 103 113 #define PCIE_PHY_RESET 113 #define PCIE_PHY_RESET 104 114 #define PCIE_PCI_RESET 114 #define PCIE_PCI_RESET 105 115 #define PCIE_POR_RESET 115 #define PCIE_POR_RESET 106 116 #define PCIE_HCLK_RESET 116 #define PCIE_HCLK_RESET 107 117 #define PCIE_ACLK_RESET 117 #define PCIE_ACLK_RESET 108 118 #define CE3_H_RESET 118 #define CE3_H_RESET 109 119 #define SFAB_CE3_M_RESET 119 #define SFAB_CE3_M_RESET 110 120 #define SFAB_CE3_S_RESET 120 #define SFAB_CE3_S_RESET 111 121 #define SATA_RESET 121 #define SATA_RESET 112 122 #define CE3_SLEEP_RESET 122 #define CE3_SLEEP_RESET 113 123 #define GSS_SLP_RESET 123 #define GSS_SLP_RESET 114 124 #define GSS_RESET 124 #define GSS_RESET 115 125 125 126 #endif 126 #endif 127 127
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