1 /* SPDX-License-Identifier: (GPL-2.0-or-later 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 2 /* 2 /* 3 * Realtek RTD1195 reset controllers 3 * Realtek RTD1195 reset controllers 4 * 4 * 5 * Copyright (c) 2017 Andreas Färber 5 * Copyright (c) 2017 Andreas Färber 6 */ 6 */ 7 #ifndef DT_BINDINGS_RESET_RTD1195_H 7 #ifndef DT_BINDINGS_RESET_RTD1195_H 8 #define DT_BINDINGS_RESET_RTD1195_H 8 #define DT_BINDINGS_RESET_RTD1195_H 9 9 10 /* soft reset 1 */ 10 /* soft reset 1 */ 11 #define RTD1195_RSTN_MISC 0 11 #define RTD1195_RSTN_MISC 0 12 #define RTD1195_RSTN_RNG 1 12 #define RTD1195_RSTN_RNG 1 13 #define RTD1195_RSTN_USB3_POW 2 13 #define RTD1195_RSTN_USB3_POW 2 14 #define RTD1195_RSTN_GSPI 3 14 #define RTD1195_RSTN_GSPI 3 15 #define RTD1195_RSTN_USB3_P0_MDIO 4 15 #define RTD1195_RSTN_USB3_P0_MDIO 4 16 #define RTD1195_RSTN_VE_H265 5 16 #define RTD1195_RSTN_VE_H265 5 17 #define RTD1195_RSTN_USB 6 17 #define RTD1195_RSTN_USB 6 18 #define RTD1195_RSTN_USB_PHY0 8 18 #define RTD1195_RSTN_USB_PHY0 8 19 #define RTD1195_RSTN_USB_PHY1 9 19 #define RTD1195_RSTN_USB_PHY1 9 20 #define RTD1195_RSTN_HDMIRX 11 20 #define RTD1195_RSTN_HDMIRX 11 21 #define RTD1195_RSTN_HDMI 12 21 #define RTD1195_RSTN_HDMI 12 22 #define RTD1195_RSTN_ETN 14 22 #define RTD1195_RSTN_ETN 14 23 #define RTD1195_RSTN_AIO 15 23 #define RTD1195_RSTN_AIO 15 24 #define RTD1195_RSTN_GPU 16 24 #define RTD1195_RSTN_GPU 16 25 #define RTD1195_RSTN_VE_H264 17 25 #define RTD1195_RSTN_VE_H264 17 26 #define RTD1195_RSTN_VE_JPEG 18 26 #define RTD1195_RSTN_VE_JPEG 18 27 #define RTD1195_RSTN_TVE 19 27 #define RTD1195_RSTN_TVE 19 28 #define RTD1195_RSTN_VO 20 28 #define RTD1195_RSTN_VO 20 29 #define RTD1195_RSTN_LVDS 21 29 #define RTD1195_RSTN_LVDS 21 30 #define RTD1195_RSTN_SE 22 30 #define RTD1195_RSTN_SE 22 31 #define RTD1195_RSTN_DCU 23 31 #define RTD1195_RSTN_DCU 23 32 #define RTD1195_RSTN_DC_PHY 24 32 #define RTD1195_RSTN_DC_PHY 24 33 #define RTD1195_RSTN_CP 25 33 #define RTD1195_RSTN_CP 25 34 #define RTD1195_RSTN_MD 26 34 #define RTD1195_RSTN_MD 26 35 #define RTD1195_RSTN_TP 27 35 #define RTD1195_RSTN_TP 27 36 #define RTD1195_RSTN_AE 28 36 #define RTD1195_RSTN_AE 28 37 #define RTD1195_RSTN_NF 29 37 #define RTD1195_RSTN_NF 29 38 #define RTD1195_RSTN_MIPI 30 38 #define RTD1195_RSTN_MIPI 30 39 39 40 /* soft reset 2 */ 40 /* soft reset 2 */ 41 #define RTD1195_RSTN_ACPU 0 41 #define RTD1195_RSTN_ACPU 0 42 #define RTD1195_RSTN_VCPU 1 42 #define RTD1195_RSTN_VCPU 1 43 #define RTD1195_RSTN_PCR 9 43 #define RTD1195_RSTN_PCR 9 44 #define RTD1195_RSTN_CR 10 44 #define RTD1195_RSTN_CR 10 45 #define RTD1195_RSTN_EMMC 11 45 #define RTD1195_RSTN_EMMC 11 46 #define RTD1195_RSTN_SDIO 12 46 #define RTD1195_RSTN_SDIO 12 47 #define RTD1195_RSTN_I2C_5 18 47 #define RTD1195_RSTN_I2C_5 18 48 #define RTD1195_RSTN_RTC 20 48 #define RTD1195_RSTN_RTC 20 49 #define RTD1195_RSTN_I2C_4 23 49 #define RTD1195_RSTN_I2C_4 23 50 #define RTD1195_RSTN_I2C_3 24 50 #define RTD1195_RSTN_I2C_3 24 51 #define RTD1195_RSTN_I2C_2 25 51 #define RTD1195_RSTN_I2C_2 25 52 #define RTD1195_RSTN_I2C_1 26 52 #define RTD1195_RSTN_I2C_1 26 53 #define RTD1195_RSTN_UR1 28 53 #define RTD1195_RSTN_UR1 28 54 54 55 /* soft reset 3 */ 55 /* soft reset 3 */ 56 #define RTD1195_RSTN_SB2 0 56 #define RTD1195_RSTN_SB2 0 57 57 58 /* iso soft reset */ 58 /* iso soft reset */ 59 #define RTD1195_ISO_RSTN_VFD 0 59 #define RTD1195_ISO_RSTN_VFD 0 60 #define RTD1195_ISO_RSTN_IR 1 60 #define RTD1195_ISO_RSTN_IR 1 61 #define RTD1195_ISO_RSTN_CEC0 2 61 #define RTD1195_ISO_RSTN_CEC0 2 62 #define RTD1195_ISO_RSTN_CEC1 3 62 #define RTD1195_ISO_RSTN_CEC1 3 63 #define RTD1195_ISO_RSTN_DP 4 63 #define RTD1195_ISO_RSTN_DP 4 64 #define RTD1195_ISO_RSTN_CBUSTX 5 64 #define RTD1195_ISO_RSTN_CBUSTX 5 65 #define RTD1195_ISO_RSTN_CBUSRX 6 65 #define RTD1195_ISO_RSTN_CBUSRX 6 66 #define RTD1195_ISO_RSTN_EFUSE 7 66 #define RTD1195_ISO_RSTN_EFUSE 7 67 #define RTD1195_ISO_RSTN_UR0 8 67 #define RTD1195_ISO_RSTN_UR0 8 68 #define RTD1195_ISO_RSTN_GMAC 9 68 #define RTD1195_ISO_RSTN_GMAC 9 69 #define RTD1195_ISO_RSTN_GPHY 10 69 #define RTD1195_ISO_RSTN_GPHY 10 70 #define RTD1195_ISO_RSTN_I2C_0 11 70 #define RTD1195_ISO_RSTN_I2C_0 11 71 #define RTD1195_ISO_RSTN_I2C_6 12 71 #define RTD1195_ISO_RSTN_I2C_6 12 72 #define RTD1195_ISO_RSTN_CBUS 13 72 #define RTD1195_ISO_RSTN_CBUS 13 73 73 74 #endif 74 #endif 75 75
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