1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 2 /* 3 * Copyright (c) 2020 Yangtao Li <frank@allwin 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ 6 #ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ 7 #define _DT_BINDINGS_RESET_SUN50I_A100_H_ 7 #define _DT_BINDINGS_RESET_SUN50I_A100_H_ 8 8 9 #define RST_MBUS 0 9 #define RST_MBUS 0 10 #define RST_BUS_DE 1 10 #define RST_BUS_DE 1 11 #define RST_BUS_G2D 2 11 #define RST_BUS_G2D 2 12 #define RST_BUS_GPU 3 12 #define RST_BUS_GPU 3 13 #define RST_BUS_CE 4 13 #define RST_BUS_CE 4 14 #define RST_BUS_VE 5 14 #define RST_BUS_VE 5 15 #define RST_BUS_DMA 6 15 #define RST_BUS_DMA 6 16 #define RST_BUS_MSGBOX 7 16 #define RST_BUS_MSGBOX 7 17 #define RST_BUS_SPINLOCK 8 17 #define RST_BUS_SPINLOCK 8 18 #define RST_BUS_HSTIMER 9 18 #define RST_BUS_HSTIMER 9 19 #define RST_BUS_DBG 10 19 #define RST_BUS_DBG 10 20 #define RST_BUS_PSI 11 20 #define RST_BUS_PSI 11 21 #define RST_BUS_PWM 12 21 #define RST_BUS_PWM 12 22 #define RST_BUS_DRAM 13 22 #define RST_BUS_DRAM 13 23 #define RST_BUS_NAND 14 23 #define RST_BUS_NAND 14 24 #define RST_BUS_MMC0 15 24 #define RST_BUS_MMC0 15 25 #define RST_BUS_MMC1 16 25 #define RST_BUS_MMC1 16 26 #define RST_BUS_MMC2 17 26 #define RST_BUS_MMC2 17 27 #define RST_BUS_UART0 18 27 #define RST_BUS_UART0 18 28 #define RST_BUS_UART1 19 28 #define RST_BUS_UART1 19 29 #define RST_BUS_UART2 20 29 #define RST_BUS_UART2 20 30 #define RST_BUS_UART3 21 30 #define RST_BUS_UART3 21 31 #define RST_BUS_UART4 22 31 #define RST_BUS_UART4 22 32 #define RST_BUS_I2C0 23 32 #define RST_BUS_I2C0 23 33 #define RST_BUS_I2C1 24 33 #define RST_BUS_I2C1 24 34 #define RST_BUS_I2C2 25 34 #define RST_BUS_I2C2 25 35 #define RST_BUS_I2C3 26 35 #define RST_BUS_I2C3 26 36 #define RST_BUS_SPI0 27 36 #define RST_BUS_SPI0 27 37 #define RST_BUS_SPI1 28 37 #define RST_BUS_SPI1 28 38 #define RST_BUS_SPI2 29 38 #define RST_BUS_SPI2 29 39 #define RST_BUS_EMAC 30 39 #define RST_BUS_EMAC 30 40 #define RST_BUS_IR_RX 31 40 #define RST_BUS_IR_RX 31 41 #define RST_BUS_IR_TX 32 41 #define RST_BUS_IR_TX 32 42 #define RST_BUS_GPADC 33 42 #define RST_BUS_GPADC 33 43 #define RST_BUS_THS 34 43 #define RST_BUS_THS 34 44 #define RST_BUS_I2S0 35 44 #define RST_BUS_I2S0 35 45 #define RST_BUS_I2S1 36 45 #define RST_BUS_I2S1 36 46 #define RST_BUS_I2S2 37 46 #define RST_BUS_I2S2 37 47 #define RST_BUS_I2S3 38 47 #define RST_BUS_I2S3 38 48 #define RST_BUS_SPDIF 39 48 #define RST_BUS_SPDIF 39 49 #define RST_BUS_DMIC 40 49 #define RST_BUS_DMIC 40 50 #define RST_BUS_AUDIO_CODEC 41 50 #define RST_BUS_AUDIO_CODEC 41 51 #define RST_USB_PHY0 42 51 #define RST_USB_PHY0 42 52 #define RST_USB_PHY1 43 52 #define RST_USB_PHY1 43 53 #define RST_BUS_OHCI0 44 53 #define RST_BUS_OHCI0 44 54 #define RST_BUS_OHCI1 45 54 #define RST_BUS_OHCI1 45 55 #define RST_BUS_EHCI0 46 55 #define RST_BUS_EHCI0 46 56 #define RST_BUS_EHCI1 47 56 #define RST_BUS_EHCI1 47 57 #define RST_BUS_OTG 48 57 #define RST_BUS_OTG 48 58 #define RST_BUS_LRADC 49 58 #define RST_BUS_LRADC 49 59 #define RST_BUS_DPSS_TOP0 50 59 #define RST_BUS_DPSS_TOP0 50 60 #define RST_BUS_DPSS_TOP1 51 60 #define RST_BUS_DPSS_TOP1 51 61 #define RST_BUS_MIPI_DSI 52 61 #define RST_BUS_MIPI_DSI 52 62 #define RST_BUS_TCON_LCD 53 62 #define RST_BUS_TCON_LCD 53 63 #define RST_BUS_LVDS 54 63 #define RST_BUS_LVDS 54 64 #define RST_BUS_LEDC 55 64 #define RST_BUS_LEDC 55 65 #define RST_BUS_CSI 56 65 #define RST_BUS_CSI 56 66 #define RST_BUS_CSI_ISP 57 66 #define RST_BUS_CSI_ISP 57 67 67 68 #endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ 68 #endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ 69 69
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