1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* Copyright (c) 2018, NVIDIA CORPORATION. All 3 4 #ifndef __ABI_MACH_T194_RESET_H 5 #define __ABI_MACH_T194_RESET_H 6 7 #define TEGRA194_RESET_ACTMON 8 #define TEGRA194_RESET_ADSP_ALL 9 #define TEGRA194_RESET_AFI 10 #define TEGRA194_RESET_CAN1 11 #define TEGRA194_RESET_CAN2 12 #define TEGRA194_RESET_DLA0 13 #define TEGRA194_RESET_DLA1 14 #define TEGRA194_RESET_DPAUX 15 #define TEGRA194_RESET_DPAUX1 16 #define TEGRA194_RESET_DPAUX2 17 #define TEGRA194_RESET_DPAUX3 18 #define TEGRA194_RESET_EQOS 19 #define TEGRA194_RESET_GPCDMA 20 #define TEGRA194_RESET_GPU 21 #define TEGRA194_RESET_HDA 22 #define TEGRA194_RESET_HDA2CODEC_2X 23 #define TEGRA194_RESET_HDA2HDMICODEC 24 #define TEGRA194_RESET_HOST1X 25 #define TEGRA194_RESET_I2C1 26 #define TEGRA194_RESET_I2C10 27 #define TEGRA194_RESET_RSVD_26 28 #define TEGRA194_RESET_RSVD_27 29 #define TEGRA194_RESET_RSVD_28 30 #define TEGRA194_RESET_I2C2 31 #define TEGRA194_RESET_I2C3 32 #define TEGRA194_RESET_I2C4 33 #define TEGRA194_RESET_I2C6 34 #define TEGRA194_RESET_I2C7 35 #define TEGRA194_RESET_I2C8 36 #define TEGRA194_RESET_I2C9 37 #define TEGRA194_RESET_ISP 38 #define TEGRA194_RESET_MIPI_CAL 39 #define TEGRA194_RESET_MPHY_CLK_CTL 40 #define TEGRA194_RESET_MPHY_L0_RX 41 #define TEGRA194_RESET_MPHY_L0_TX 42 #define TEGRA194_RESET_MPHY_L1_RX 43 #define TEGRA194_RESET_MPHY_L1_TX 44 #define TEGRA194_RESET_NVCSI 45 #define TEGRA194_RESET_NVDEC 46 #define TEGRA194_RESET_NVDISPLAY0_HEAD0 47 #define TEGRA194_RESET_NVDISPLAY0_HEAD1 48 #define TEGRA194_RESET_NVDISPLAY0_HEAD2 49 #define TEGRA194_RESET_NVDISPLAY0_HEAD3 50 #define TEGRA194_RESET_NVDISPLAY0_MISC 51 #define TEGRA194_RESET_NVDISPLAY0_WGRP0 52 #define TEGRA194_RESET_NVDISPLAY0_WGRP1 53 #define TEGRA194_RESET_NVDISPLAY0_WGRP2 54 #define TEGRA194_RESET_NVDISPLAY0_WGRP3 55 #define TEGRA194_RESET_NVDISPLAY0_WGRP4 56 #define TEGRA194_RESET_NVDISPLAY0_WGRP5 57 #define TEGRA194_RESET_RSVD_56 58 #define TEGRA194_RESET_RSVD_57 59 #define TEGRA194_RESET_RSVD_58 60 #define TEGRA194_RESET_NVENC 61 #define TEGRA194_RESET_NVENC1 62 #define TEGRA194_RESET_NVJPG 63 #define TEGRA194_RESET_PCIE 64 #define TEGRA194_RESET_PCIEXCLK 65 #define TEGRA194_RESET_RSVD_64 66 #define TEGRA194_RESET_RSVD_65 67 #define TEGRA194_RESET_PVA0_ALL 68 #define TEGRA194_RESET_PVA1_ALL 69 #define TEGRA194_RESET_PWM1 70 #define TEGRA194_RESET_PWM2 71 #define TEGRA194_RESET_PWM3 72 #define TEGRA194_RESET_PWM4 73 #define TEGRA194_RESET_PWM5 74 #define TEGRA194_RESET_PWM6 75 #define TEGRA194_RESET_PWM7 76 #define TEGRA194_RESET_PWM8 77 #define TEGRA194_RESET_QSPI0 78 #define TEGRA194_RESET_QSPI1 79 #define TEGRA194_RESET_SATA 80 #define TEGRA194_RESET_SATACOLD 81 #define TEGRA194_RESET_SCE_ALL 82 #define TEGRA194_RESET_RCE_ALL 83 #define TEGRA194_RESET_SDMMC1 84 #define TEGRA194_RESET_RSVD_83 85 #define TEGRA194_RESET_SDMMC3 86 #define TEGRA194_RESET_SDMMC4 87 #define TEGRA194_RESET_SE 88 #define TEGRA194_RESET_SOR0 89 #define TEGRA194_RESET_SOR1 90 #define TEGRA194_RESET_SOR2 91 #define TEGRA194_RESET_SOR3 92 #define TEGRA194_RESET_SPI1 93 #define TEGRA194_RESET_SPI2 94 #define TEGRA194_RESET_SPI3 95 #define TEGRA194_RESET_SPI4 96 #define TEGRA194_RESET_TACH 97 #define TEGRA194_RESET_RSVD_96 98 #define TEGRA194_RESET_TSCTNVI 99 #define TEGRA194_RESET_TSEC 100 #define TEGRA194_RESET_TSECB 101 #define TEGRA194_RESET_UARTA 102 #define TEGRA194_RESET_UARTB 103 #define TEGRA194_RESET_UARTC 104 #define TEGRA194_RESET_UARTD 105 #define TEGRA194_RESET_UARTE 106 #define TEGRA194_RESET_UARTF 107 #define TEGRA194_RESET_UARTG 108 #define TEGRA194_RESET_UARTH 109 #define TEGRA194_RESET_UFSHC 110 #define TEGRA194_RESET_UFSHC_AXI_M 111 #define TEGRA194_RESET_UFSHC_LP_SEQ 112 #define TEGRA194_RESET_RSVD_111 113 #define TEGRA194_RESET_VI 114 #define TEGRA194_RESET_VIC 115 #define TEGRA194_RESET_XUSB_PADCTL 116 #define TEGRA194_RESET_NVDEC1 117 #define TEGRA194_RESET_PEX0_CORE_0 118 #define TEGRA194_RESET_PEX0_CORE_1 119 #define TEGRA194_RESET_PEX0_CORE_2 120 #define TEGRA194_RESET_PEX0_CORE_3 121 #define TEGRA194_RESET_PEX0_CORE_4 122 #define TEGRA194_RESET_PEX0_CORE_0_APB 123 #define TEGRA194_RESET_PEX0_CORE_1_APB 124 #define TEGRA194_RESET_PEX0_CORE_2_APB 125 #define TEGRA194_RESET_PEX0_CORE_3_APB 126 #define TEGRA194_RESET_PEX0_CORE_4_APB 127 #define TEGRA194_RESET_PEX0_COMMON_APB 128 #define TEGRA194_RESET_PEX1_CORE_5 129 #define TEGRA194_RESET_PEX1_CORE_5_APB 130 #define TEGRA194_RESET_CVNAS 131 #define TEGRA194_RESET_CVNAS_FCM 132 #define TEGRA194_RESET_DMIC5 133 #define TEGRA194_RESET_APE 134 #define TEGRA194_RESET_PEX_USB_UPHY 135 #define TEGRA194_RESET_PEX_USB_UPHY_L0 136 #define TEGRA194_RESET_PEX_USB_UPHY_L1 137 #define TEGRA194_RESET_PEX_USB_UPHY_L2 138 #define TEGRA194_RESET_PEX_USB_UPHY_L3 139 #define TEGRA194_RESET_PEX_USB_UPHY_L4 140 #define TEGRA194_RESET_PEX_USB_UPHY_L5 141 #define TEGRA194_RESET_PEX_USB_UPHY_L6 142 #define TEGRA194_RESET_PEX_USB_UPHY_L7 143 #define TEGRA194_RESET_PEX_USB_UPHY_L8 144 #define TEGRA194_RESET_PEX_USB_UPHY_L9 145 #define TEGRA194_RESET_PEX_USB_UPHY_L10 146 #define TEGRA194_RESET_PEX_USB_UPHY_L11 147 #define TEGRA194_RESET_PEX_USB_UPHY_PLL0 148 #define TEGRA194_RESET_PEX_USB_UPHY_PLL1 149 #define TEGRA194_RESET_PEX_USB_UPHY_PLL2 150 #define TEGRA194_RESET_PEX_USB_UPHY_PLL3 151 152 #endif 153
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