1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION
3
4 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
5 #define DT_BINDINGS_RESET_TEGRA234_RESET_H
6
7 /**
8 * @file
9 * @defgroup bpmp_reset_ids Reset ID's
10 * @brief Identifiers for Resets controllable
11 * @{
12 */
13 #define TEGRA234_RESET_ACTMON
14 #define TEGRA234_RESET_ADSP_ALL
15 #define TEGRA234_RESET_DSI_CORE
16 #define TEGRA234_RESET_CAN1
17 #define TEGRA234_RESET_CAN2
18 #define TEGRA234_RESET_DLA0
19 #define TEGRA234_RESET_DLA1
20 #define TEGRA234_RESET_DPAUX
21 #define TEGRA234_RESET_OFA
22 #define TEGRA234_RESET_NVJPG1
23 #define TEGRA234_RESET_PEX1_CORE_6
24 #define TEGRA234_RESET_PEX1_CORE_6_APB
25 #define TEGRA234_RESET_PEX1_COMMON_APB
26 #define TEGRA234_RESET_PEX2_CORE_7
27 #define TEGRA234_RESET_PEX2_CORE_7_APB
28 #define TEGRA234_RESET_NVDISPLAY
29 #define TEGRA234_RESET_EQOS
30 #define TEGRA234_RESET_GPCDMA
31 #define TEGRA234_RESET_GPU
32 #define TEGRA234_RESET_HDA
33 #define TEGRA234_RESET_HDACODEC
34 #define TEGRA234_RESET_EQOS_MACSEC
35 #define TEGRA234_RESET_EQOS_MACSEC_SECURE
36 #define TEGRA234_RESET_I2C1
37 #define TEGRA234_RESET_PEX2_CORE_8
38 #define TEGRA234_RESET_PEX2_CORE_8_APB
39 #define TEGRA234_RESET_PEX2_CORE_9
40 #define TEGRA234_RESET_PEX2_CORE_9_APB
41 #define TEGRA234_RESET_I2C2
42 #define TEGRA234_RESET_I2C3
43 #define TEGRA234_RESET_I2C4
44 #define TEGRA234_RESET_I2C6
45 #define TEGRA234_RESET_I2C7
46 #define TEGRA234_RESET_I2C8
47 #define TEGRA234_RESET_I2C9
48 #define TEGRA234_RESET_ISP
49 #define TEGRA234_RESET_MIPI_CAL
50 #define TEGRA234_RESET_MPHY_CLK_CTL
51 #define TEGRA234_RESET_MPHY_L0_RX
52 #define TEGRA234_RESET_MPHY_L0_TX
53 #define TEGRA234_RESET_MPHY_L1_RX
54 #define TEGRA234_RESET_MPHY_L1_TX
55 #define TEGRA234_RESET_NVCSI
56 #define TEGRA234_RESET_NVDEC
57 #define TEGRA234_RESET_MGBE0_PCS
58 #define TEGRA234_RESET_MGBE0_MAC
59 #define TEGRA234_RESET_MGBE0_MACSEC
60 #define TEGRA234_RESET_MGBE0_MACSEC_SECURE
61 #define TEGRA234_RESET_MGBE1_PCS
62 #define TEGRA234_RESET_MGBE1_MAC
63 #define TEGRA234_RESET_MGBE1_MACSEC
64 #define TEGRA234_RESET_MGBE1_MACSEC_SECURE
65 #define TEGRA234_RESET_MGBE2_PCS
66 #define TEGRA234_RESET_MGBE2_MAC
67 #define TEGRA234_RESET_MGBE2_MACSEC
68 #define TEGRA234_RESET_PEX2_CORE_10
69 #define TEGRA234_RESET_PEX2_CORE_10_APB
70 #define TEGRA234_RESET_PEX2_COMMON_APB
71 #define TEGRA234_RESET_NVENC
72 #define TEGRA234_RESET_MGBE2_MACSEC_SECURE
73 #define TEGRA234_RESET_NVJPG
74 #define TEGRA234_RESET_LA
75 #define TEGRA234_RESET_HWPM
76 #define TEGRA234_RESET_PVA0_ALL
77 #define TEGRA234_RESET_CEC
78 #define TEGRA234_RESET_PWM1
79 #define TEGRA234_RESET_PWM2
80 #define TEGRA234_RESET_PWM3
81 #define TEGRA234_RESET_PWM4
82 #define TEGRA234_RESET_PWM5
83 #define TEGRA234_RESET_PWM6
84 #define TEGRA234_RESET_PWM7
85 #define TEGRA234_RESET_PWM8
86 #define TEGRA234_RESET_QSPI0
87 #define TEGRA234_RESET_QSPI1
88 #define TEGRA234_RESET_I2S7
89 #define TEGRA234_RESET_I2S8
90 #define TEGRA234_RESET_SCE_ALL
91 #define TEGRA234_RESET_RCE_ALL
92 #define TEGRA234_RESET_SDMMC1
93 #define TEGRA234_RESET_RSVD_83
94 #define TEGRA234_RESET_RSVD_84
95 #define TEGRA234_RESET_SDMMC4
96 #define TEGRA234_RESET_MGBE3_PCS
97 #define TEGRA234_RESET_MGBE3_MAC
98 #define TEGRA234_RESET_MGBE3_MACSEC
99 #define TEGRA234_RESET_MGBE3_MACSEC_SECURE
100 #define TEGRA234_RESET_SPI1
101 #define TEGRA234_RESET_SPI2
102 #define TEGRA234_RESET_SPI3
103 #define TEGRA234_RESET_SPI4
104 #define TEGRA234_RESET_TACH0
105 #define TEGRA234_RESET_TACH1
106 #define TEGRA234_RESET_SPI5
107 #define TEGRA234_RESET_TSEC
108 #define TEGRA234_RESET_UARTI
109 #define TEGRA234_RESET_UARTA
110 #define TEGRA234_RESET_UARTB
111 #define TEGRA234_RESET_UARTC
112 #define TEGRA234_RESET_UARTD
113 #define TEGRA234_RESET_UARTE
114 #define TEGRA234_RESET_UARTF
115 #define TEGRA234_RESET_UARTJ
116 #define TEGRA234_RESET_UARTH
117 #define TEGRA234_RESET_UFSHC
118 #define TEGRA234_RESET_UFSHC_AXI_M
119 #define TEGRA234_RESET_UFSHC_LP_SEQ
120 #define TEGRA234_RESET_RSVD_111
121 #define TEGRA234_RESET_VI
122 #define TEGRA234_RESET_VIC
123 #define TEGRA234_RESET_XUSB_PADCTL
124 #define TEGRA234_RESET_VI2
125 #define TEGRA234_RESET_PEX0_CORE_0
126 #define TEGRA234_RESET_PEX0_CORE_1
127 #define TEGRA234_RESET_PEX0_CORE_2
128 #define TEGRA234_RESET_PEX0_CORE_3
129 #define TEGRA234_RESET_PEX0_CORE_4
130 #define TEGRA234_RESET_PEX0_CORE_0_APB
131 #define TEGRA234_RESET_PEX0_CORE_1_APB
132 #define TEGRA234_RESET_PEX0_CORE_2_APB
133 #define TEGRA234_RESET_PEX0_CORE_3_APB
134 #define TEGRA234_RESET_PEX0_CORE_4_APB
135 #define TEGRA234_RESET_PEX0_COMMON_APB
136 #define TEGRA234_RESET_RSVD_127
137 #define TEGRA234_RESET_NVHS_UPHY_PLL1
138 #define TEGRA234_RESET_PEX1_CORE_5
139 #define TEGRA234_RESET_PEX1_CORE_5_APB
140 #define TEGRA234_RESET_GBE_UPHY
141 #define TEGRA234_RESET_GBE_UPHY_PM
142 #define TEGRA234_RESET_NVHS_UPHY
143 #define TEGRA234_RESET_NVHS_UPHY_PLL0
144 #define TEGRA234_RESET_NVHS_UPHY_L0
145 #define TEGRA234_RESET_NVHS_UPHY_L1
146 #define TEGRA234_RESET_NVHS_UPHY_L2
147 #define TEGRA234_RESET_NVHS_UPHY_L3
148 #define TEGRA234_RESET_NVHS_UPHY_L4
149 #define TEGRA234_RESET_NVHS_UPHY_L5
150 #define TEGRA234_RESET_NVHS_UPHY_L6
151 #define TEGRA234_RESET_NVHS_UPHY_L7
152 #define TEGRA234_RESET_NVHS_UPHY_PM
153 #define TEGRA234_RESET_DMIC5
154 #define TEGRA234_RESET_APE
155 #define TEGRA234_RESET_PEX_USB_UPHY
156 #define TEGRA234_RESET_PEX_USB_UPHY_L0
157 #define TEGRA234_RESET_PEX_USB_UPHY_L1
158 #define TEGRA234_RESET_PEX_USB_UPHY_L2
159 #define TEGRA234_RESET_PEX_USB_UPHY_L3
160 #define TEGRA234_RESET_PEX_USB_UPHY_L4
161 #define TEGRA234_RESET_PEX_USB_UPHY_L5
162 #define TEGRA234_RESET_PEX_USB_UPHY_L6
163 #define TEGRA234_RESET_PEX_USB_UPHY_L7
164 #define TEGRA234_RESET_PEX_USB_UPHY_PLL0
165 #define TEGRA234_RESET_PEX_USB_UPHY_PLL1
166 #define TEGRA234_RESET_PEX_USB_UPHY_PLL2
167 #define TEGRA234_RESET_PEX_USB_UPHY_PLL3
168 #define TEGRA234_RESET_GBE_UPHY_L0
169 #define TEGRA234_RESET_GBE_UPHY_L1
170 #define TEGRA234_RESET_GBE_UPHY_L2
171 #define TEGRA234_RESET_GBE_UPHY_L3
172 #define TEGRA234_RESET_GBE_UPHY_L4
173 #define TEGRA234_RESET_GBE_UPHY_L5
174 #define TEGRA234_RESET_GBE_UPHY_L6
175 #define TEGRA234_RESET_GBE_UPHY_L7
176 #define TEGRA234_RESET_GBE_UPHY_PLL0
177 #define TEGRA234_RESET_GBE_UPHY_PLL1
178 #define TEGRA234_RESET_GBE_UPHY_PLL2
179
180 /** @} */
181
182 #endif
183
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