Linux/include/dt-bindings/reset/tegra234-reset.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION 2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3 3 4 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H 4 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H 5 #define DT_BINDINGS_RESET_TEGRA234_RESET_H 5 #define DT_BINDINGS_RESET_TEGRA234_RESET_H 6 6 7 /** 7 /** 8 * @file 8 * @file 9 * @defgroup bpmp_reset_ids Reset ID's 9 * @defgroup bpmp_reset_ids Reset ID's 10 * @brief Identifiers for Resets controllable 10 * @brief Identifiers for Resets controllable by firmware 11 * @{ 11 * @{ 12 */ 12 */ 13 #define TEGRA234_RESET_ACTMON << 14 #define TEGRA234_RESET_ADSP_ALL << 15 #define TEGRA234_RESET_DSI_CORE << 16 #define TEGRA234_RESET_CAN1 << 17 #define TEGRA234_RESET_CAN2 << 18 #define TEGRA234_RESET_DLA0 << 19 #define TEGRA234_RESET_DLA1 << 20 #define TEGRA234_RESET_DPAUX << 21 #define TEGRA234_RESET_OFA << 22 #define TEGRA234_RESET_NVJPG1 << 23 #define TEGRA234_RESET_PEX1_CORE_6 13 #define TEGRA234_RESET_PEX1_CORE_6 11U 24 #define TEGRA234_RESET_PEX1_CORE_6_APB 14 #define TEGRA234_RESET_PEX1_CORE_6_APB 12U 25 #define TEGRA234_RESET_PEX1_COMMON_APB 15 #define TEGRA234_RESET_PEX1_COMMON_APB 13U 26 #define TEGRA234_RESET_PEX2_CORE_7 16 #define TEGRA234_RESET_PEX2_CORE_7 14U 27 #define TEGRA234_RESET_PEX2_CORE_7_APB 17 #define TEGRA234_RESET_PEX2_CORE_7_APB 15U 28 #define TEGRA234_RESET_NVDISPLAY << 29 #define TEGRA234_RESET_EQOS << 30 #define TEGRA234_RESET_GPCDMA 18 #define TEGRA234_RESET_GPCDMA 18U 31 #define TEGRA234_RESET_GPU << 32 #define TEGRA234_RESET_HDA 19 #define TEGRA234_RESET_HDA 20U 33 #define TEGRA234_RESET_HDACODEC 20 #define TEGRA234_RESET_HDACODEC 21U 34 #define TEGRA234_RESET_EQOS_MACSEC << 35 #define TEGRA234_RESET_EQOS_MACSEC_SECURE << 36 #define TEGRA234_RESET_I2C1 21 #define TEGRA234_RESET_I2C1 24U 37 #define TEGRA234_RESET_PEX2_CORE_8 22 #define TEGRA234_RESET_PEX2_CORE_8 25U 38 #define TEGRA234_RESET_PEX2_CORE_8_APB 23 #define TEGRA234_RESET_PEX2_CORE_8_APB 26U 39 #define TEGRA234_RESET_PEX2_CORE_9 24 #define TEGRA234_RESET_PEX2_CORE_9 27U 40 #define TEGRA234_RESET_PEX2_CORE_9_APB 25 #define TEGRA234_RESET_PEX2_CORE_9_APB 28U 41 #define TEGRA234_RESET_I2C2 26 #define TEGRA234_RESET_I2C2 29U 42 #define TEGRA234_RESET_I2C3 27 #define TEGRA234_RESET_I2C3 30U 43 #define TEGRA234_RESET_I2C4 28 #define TEGRA234_RESET_I2C4 31U 44 #define TEGRA234_RESET_I2C6 29 #define TEGRA234_RESET_I2C6 32U 45 #define TEGRA234_RESET_I2C7 30 #define TEGRA234_RESET_I2C7 33U 46 #define TEGRA234_RESET_I2C8 31 #define TEGRA234_RESET_I2C8 34U 47 #define TEGRA234_RESET_I2C9 32 #define TEGRA234_RESET_I2C9 35U 48 #define TEGRA234_RESET_ISP << 49 #define TEGRA234_RESET_MIPI_CAL << 50 #define TEGRA234_RESET_MPHY_CLK_CTL << 51 #define TEGRA234_RESET_MPHY_L0_RX << 52 #define TEGRA234_RESET_MPHY_L0_TX << 53 #define TEGRA234_RESET_MPHY_L1_RX << 54 #define TEGRA234_RESET_MPHY_L1_TX << 55 #define TEGRA234_RESET_NVCSI << 56 #define TEGRA234_RESET_NVDEC << 57 #define TEGRA234_RESET_MGBE0_PCS 33 #define TEGRA234_RESET_MGBE0_PCS 45U 58 #define TEGRA234_RESET_MGBE0_MAC 34 #define TEGRA234_RESET_MGBE0_MAC 46U 59 #define TEGRA234_RESET_MGBE0_MACSEC << 60 #define TEGRA234_RESET_MGBE0_MACSEC_SECURE << 61 #define TEGRA234_RESET_MGBE1_PCS 35 #define TEGRA234_RESET_MGBE1_PCS 49U 62 #define TEGRA234_RESET_MGBE1_MAC 36 #define TEGRA234_RESET_MGBE1_MAC 50U 63 #define TEGRA234_RESET_MGBE1_MACSEC << 64 #define TEGRA234_RESET_MGBE1_MACSEC_SECURE << 65 #define TEGRA234_RESET_MGBE2_PCS 37 #define TEGRA234_RESET_MGBE2_PCS 53U 66 #define TEGRA234_RESET_MGBE2_MAC 38 #define TEGRA234_RESET_MGBE2_MAC 54U 67 #define TEGRA234_RESET_MGBE2_MACSEC << 68 #define TEGRA234_RESET_PEX2_CORE_10 39 #define TEGRA234_RESET_PEX2_CORE_10 56U 69 #define TEGRA234_RESET_PEX2_CORE_10_APB 40 #define TEGRA234_RESET_PEX2_CORE_10_APB 57U 70 #define TEGRA234_RESET_PEX2_COMMON_APB 41 #define TEGRA234_RESET_PEX2_COMMON_APB 58U 71 #define TEGRA234_RESET_NVENC << 72 #define TEGRA234_RESET_MGBE2_MACSEC_SECURE << 73 #define TEGRA234_RESET_NVJPG << 74 #define TEGRA234_RESET_LA << 75 #define TEGRA234_RESET_HWPM << 76 #define TEGRA234_RESET_PVA0_ALL << 77 #define TEGRA234_RESET_CEC << 78 #define TEGRA234_RESET_PWM1 42 #define TEGRA234_RESET_PWM1 68U 79 #define TEGRA234_RESET_PWM2 43 #define TEGRA234_RESET_PWM2 69U 80 #define TEGRA234_RESET_PWM3 44 #define TEGRA234_RESET_PWM3 70U 81 #define TEGRA234_RESET_PWM4 45 #define TEGRA234_RESET_PWM4 71U 82 #define TEGRA234_RESET_PWM5 46 #define TEGRA234_RESET_PWM5 72U 83 #define TEGRA234_RESET_PWM6 47 #define TEGRA234_RESET_PWM6 73U 84 #define TEGRA234_RESET_PWM7 48 #define TEGRA234_RESET_PWM7 74U 85 #define TEGRA234_RESET_PWM8 49 #define TEGRA234_RESET_PWM8 75U 86 #define TEGRA234_RESET_QSPI0 50 #define TEGRA234_RESET_QSPI0 76U 87 #define TEGRA234_RESET_QSPI1 51 #define TEGRA234_RESET_QSPI1 77U 88 #define TEGRA234_RESET_I2S7 << 89 #define TEGRA234_RESET_I2S8 << 90 #define TEGRA234_RESET_SCE_ALL << 91 #define TEGRA234_RESET_RCE_ALL << 92 #define TEGRA234_RESET_SDMMC1 << 93 #define TEGRA234_RESET_RSVD_83 << 94 #define TEGRA234_RESET_RSVD_84 << 95 #define TEGRA234_RESET_SDMMC4 52 #define TEGRA234_RESET_SDMMC4 85U 96 #define TEGRA234_RESET_MGBE3_PCS 53 #define TEGRA234_RESET_MGBE3_PCS 87U 97 #define TEGRA234_RESET_MGBE3_MAC 54 #define TEGRA234_RESET_MGBE3_MAC 88U 98 #define TEGRA234_RESET_MGBE3_MACSEC << 99 #define TEGRA234_RESET_MGBE3_MACSEC_SECURE << 100 #define TEGRA234_RESET_SPI1 << 101 #define TEGRA234_RESET_SPI2 << 102 #define TEGRA234_RESET_SPI3 << 103 #define TEGRA234_RESET_SPI4 << 104 #define TEGRA234_RESET_TACH0 << 105 #define TEGRA234_RESET_TACH1 << 106 #define TEGRA234_RESET_SPI5 << 107 #define TEGRA234_RESET_TSEC << 108 #define TEGRA234_RESET_UARTI << 109 #define TEGRA234_RESET_UARTA 55 #define TEGRA234_RESET_UARTA 100U 110 #define TEGRA234_RESET_UARTB !! 56 #define TEGRA234_RESET_VIC 113U 111 #define TEGRA234_RESET_UARTC << 112 #define TEGRA234_RESET_UARTD << 113 #define TEGRA234_RESET_UARTE << 114 #define TEGRA234_RESET_UARTF << 115 #define TEGRA234_RESET_UARTJ << 116 #define TEGRA234_RESET_UARTH << 117 #define TEGRA234_RESET_UFSHC << 118 #define TEGRA234_RESET_UFSHC_AXI_M << 119 #define TEGRA234_RESET_UFSHC_LP_SEQ << 120 #define TEGRA234_RESET_RSVD_111 << 121 #define TEGRA234_RESET_VI << 122 #define TEGRA234_RESET_VIC << 123 #define TEGRA234_RESET_XUSB_PADCTL << 124 #define TEGRA234_RESET_VI2 << 125 #define TEGRA234_RESET_PEX0_CORE_0 57 #define TEGRA234_RESET_PEX0_CORE_0 116U 126 #define TEGRA234_RESET_PEX0_CORE_1 58 #define TEGRA234_RESET_PEX0_CORE_1 117U 127 #define TEGRA234_RESET_PEX0_CORE_2 59 #define TEGRA234_RESET_PEX0_CORE_2 118U 128 #define TEGRA234_RESET_PEX0_CORE_3 60 #define TEGRA234_RESET_PEX0_CORE_3 119U 129 #define TEGRA234_RESET_PEX0_CORE_4 61 #define TEGRA234_RESET_PEX0_CORE_4 120U 130 #define TEGRA234_RESET_PEX0_CORE_0_APB 62 #define TEGRA234_RESET_PEX0_CORE_0_APB 121U 131 #define TEGRA234_RESET_PEX0_CORE_1_APB 63 #define TEGRA234_RESET_PEX0_CORE_1_APB 122U 132 #define TEGRA234_RESET_PEX0_CORE_2_APB 64 #define TEGRA234_RESET_PEX0_CORE_2_APB 123U 133 #define TEGRA234_RESET_PEX0_CORE_3_APB 65 #define TEGRA234_RESET_PEX0_CORE_3_APB 124U 134 #define TEGRA234_RESET_PEX0_CORE_4_APB 66 #define TEGRA234_RESET_PEX0_CORE_4_APB 125U 135 #define TEGRA234_RESET_PEX0_COMMON_APB 67 #define TEGRA234_RESET_PEX0_COMMON_APB 126U 136 #define TEGRA234_RESET_RSVD_127 << 137 #define TEGRA234_RESET_NVHS_UPHY_PLL1 << 138 #define TEGRA234_RESET_PEX1_CORE_5 68 #define TEGRA234_RESET_PEX1_CORE_5 129U 139 #define TEGRA234_RESET_PEX1_CORE_5_APB 69 #define TEGRA234_RESET_PEX1_CORE_5_APB 130U 140 #define TEGRA234_RESET_GBE_UPHY << 141 #define TEGRA234_RESET_GBE_UPHY_PM << 142 #define TEGRA234_RESET_NVHS_UPHY << 143 #define TEGRA234_RESET_NVHS_UPHY_PLL0 << 144 #define TEGRA234_RESET_NVHS_UPHY_L0 << 145 #define TEGRA234_RESET_NVHS_UPHY_L1 << 146 #define TEGRA234_RESET_NVHS_UPHY_L2 << 147 #define TEGRA234_RESET_NVHS_UPHY_L3 << 148 #define TEGRA234_RESET_NVHS_UPHY_L4 << 149 #define TEGRA234_RESET_NVHS_UPHY_L5 << 150 #define TEGRA234_RESET_NVHS_UPHY_L6 << 151 #define TEGRA234_RESET_NVHS_UPHY_L7 << 152 #define TEGRA234_RESET_NVHS_UPHY_PM << 153 #define TEGRA234_RESET_DMIC5 << 154 #define TEGRA234_RESET_APE << 155 #define TEGRA234_RESET_PEX_USB_UPHY << 156 #define TEGRA234_RESET_PEX_USB_UPHY_L0 << 157 #define TEGRA234_RESET_PEX_USB_UPHY_L1 << 158 #define TEGRA234_RESET_PEX_USB_UPHY_L2 << 159 #define TEGRA234_RESET_PEX_USB_UPHY_L3 << 160 #define TEGRA234_RESET_PEX_USB_UPHY_L4 << 161 #define TEGRA234_RESET_PEX_USB_UPHY_L5 << 162 #define TEGRA234_RESET_PEX_USB_UPHY_L6 << 163 #define TEGRA234_RESET_PEX_USB_UPHY_L7 << 164 #define TEGRA234_RESET_PEX_USB_UPHY_PLL0 << 165 #define TEGRA234_RESET_PEX_USB_UPHY_PLL1 << 166 #define TEGRA234_RESET_PEX_USB_UPHY_PLL2 << 167 #define TEGRA234_RESET_PEX_USB_UPHY_PLL3 << 168 #define TEGRA234_RESET_GBE_UPHY_L0 << 169 #define TEGRA234_RESET_GBE_UPHY_L1 << 170 #define TEGRA234_RESET_GBE_UPHY_L2 << 171 #define TEGRA234_RESET_GBE_UPHY_L3 << 172 #define TEGRA234_RESET_GBE_UPHY_L4 << 173 #define TEGRA234_RESET_GBE_UPHY_L5 << 174 #define TEGRA234_RESET_GBE_UPHY_L6 << 175 #define TEGRA234_RESET_GBE_UPHY_L7 << 176 #define TEGRA234_RESET_GBE_UPHY_PLL0 << 177 #define TEGRA234_RESET_GBE_UPHY_PLL1 << 178 #define TEGRA234_RESET_GBE_UPHY_PLL2 << 179 70 180 /** @} */ 71 /** @} */ 181 72 182 #endif 73 #endif 183 74

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

TOMOYO Linux Cross Reference
Linux/include/dt-bindings/reset/tegra234-reset.h

Diff markup

Differences between /include/dt-bindings/reset/tegra234-reset.h (Version linux-6.12-rc7) and /include/dt-bindings/reset/tegra234-reset.h (Version linux-6.0.19)

TOMOYO Linux Cross Reference Linux/include/dt-bindings/reset/tegra234-reset.h

Diff markup

Differences between /include/dt-bindings/reset/tegra234-reset.h (Version linux-6.12-rc7) and /include/dt-bindings/reset/tegra234-reset.h (Version linux-6.0.19)

TOMOYO Linux Cross Reference
Linux/include/dt-bindings/reset/tegra234-reset.h