1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * Copyright (C) 2020 Xilinx, Inc. 4 */ 5 6 #ifndef _DT_BINDINGS_VERSAL_RESETS_H 7 #define _DT_BINDINGS_VERSAL_RESETS_H 8 9 #define VERSAL_RST_PMC_POR 10 #define VERSAL_RST_PMC 11 #define VERSAL_RST_PS_POR 12 #define VERSAL_RST_PL_POR 13 #define VERSAL_RST_NOC_POR 14 #define VERSAL_RST_FPD_POR 15 #define VERSAL_RST_ACPU_0_POR 16 #define VERSAL_RST_ACPU_1_POR 17 #define VERSAL_RST_OCM2_POR 18 #define VERSAL_RST_PS_SRST 19 #define VERSAL_RST_PL_SRST 20 #define VERSAL_RST_NOC 21 #define VERSAL_RST_NPI 22 #define VERSAL_RST_SYS_RST_1 23 #define VERSAL_RST_SYS_RST_2 24 #define VERSAL_RST_SYS_RST_3 25 #define VERSAL_RST_FPD 26 #define VERSAL_RST_PL0 27 #define VERSAL_RST_PL1 28 #define VERSAL_RST_PL2 29 #define VERSAL_RST_PL3 30 #define VERSAL_RST_APU 31 #define VERSAL_RST_ACPU_0 32 #define VERSAL_RST_ACPU_1 33 #define VERSAL_RST_ACPU_L2 34 #define VERSAL_RST_ACPU_GIC 35 #define VERSAL_RST_RPU_ISLAND 36 #define VERSAL_RST_RPU_AMBA 37 #define VERSAL_RST_R5_0 38 #define VERSAL_RST_R5_1 39 #define VERSAL_RST_SYSMON_PMC_SEQ_RST 40 #define VERSAL_RST_SYSMON_PMC_CFG_RST 41 #define VERSAL_RST_SYSMON_FPD_CFG_RST 42 #define VERSAL_RST_SYSMON_FPD_SEQ_RST 43 #define VERSAL_RST_SYSMON_LPD 44 #define VERSAL_RST_PDMA_RST1 45 #define VERSAL_RST_PDMA_RST0 46 #define VERSAL_RST_ADMA 47 #define VERSAL_RST_TIMESTAMP 48 #define VERSAL_RST_OCM 49 #define VERSAL_RST_OCM2_RST 50 #define VERSAL_RST_IPI 51 #define VERSAL_RST_SBI 52 #define VERSAL_RST_LPD 53 #define VERSAL_RST_QSPI 54 #define VERSAL_RST_OSPI 55 #define VERSAL_RST_SDIO_0 56 #define VERSAL_RST_SDIO_1 57 #define VERSAL_RST_I2C_PMC 58 #define VERSAL_RST_GPIO_PMC 59 #define VERSAL_RST_GEM_0 60 #define VERSAL_RST_GEM_1 61 #define VERSAL_RST_SPARE 62 #define VERSAL_RST_USB_0 63 #define VERSAL_RST_UART_0 64 #define VERSAL_RST_UART_1 65 #define VERSAL_RST_SPI_0 66 #define VERSAL_RST_SPI_1 67 #define VERSAL_RST_CAN_FD_0 68 #define VERSAL_RST_CAN_FD_1 69 #define VERSAL_RST_I2C_0 70 #define VERSAL_RST_I2C_1 71 #define VERSAL_RST_GPIO_LPD 72 #define VERSAL_RST_TTC_0 73 #define VERSAL_RST_TTC_1 74 #define VERSAL_RST_TTC_2 75 #define VERSAL_RST_TTC_3 76 #define VERSAL_RST_SWDT_FPD 77 #define VERSAL_RST_SWDT_LPD 78 #define VERSAL_RST_USB 79 #define VERSAL_RST_DPC 80 #define VERSAL_RST_PMCDBG 81 #define VERSAL_RST_DBG_TRACE 82 #define VERSAL_RST_DBG_FPD 83 #define VERSAL_RST_DBG_TSTMP 84 #define VERSAL_RST_RPU0_DBG 85 #define VERSAL_RST_RPU1_DBG 86 #define VERSAL_RST_HSDP 87 #define VERSAL_RST_DBG_LPD 88 #define VERSAL_RST_CPM_POR 89 #define VERSAL_RST_CPM 90 #define VERSAL_RST_CPMDBG 91 #define VERSAL_RST_PCIE_CFG 92 #define VERSAL_RST_PCIE_CORE0 93 #define VERSAL_RST_PCIE_CORE1 94 #define VERSAL_RST_PCIE_DMA 95 #define VERSAL_RST_CMN 96 #define VERSAL_RST_L2_0 97 #define VERSAL_RST_L2_1 98 #define VERSAL_RST_ADDR_REMAP 99 #define VERSAL_RST_CPI0 100 #define VERSAL_RST_CPI1 101 #define VERSAL_RST_XRAM 102 #define VERSAL_RST_AIE_ARRAY 103 #define VERSAL_RST_AIE_SHIM 104 105 #endif 106
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