1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 2 /* 3 * Copyright (C) 2018 Xilinx, Inc. 3 * Copyright (C) 2018 Xilinx, Inc. 4 */ 4 */ 5 5 6 #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H 6 #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H 7 #define _DT_BINDINGS_ZYNQMP_RESETS_H 7 #define _DT_BINDINGS_ZYNQMP_RESETS_H 8 8 9 #define ZYNQMP_RESET_PCIE_CFG 9 #define ZYNQMP_RESET_PCIE_CFG 0 10 #define ZYNQMP_RESET_PCIE_BRIDGE 10 #define ZYNQMP_RESET_PCIE_BRIDGE 1 11 #define ZYNQMP_RESET_PCIE_CTRL 11 #define ZYNQMP_RESET_PCIE_CTRL 2 12 #define ZYNQMP_RESET_DP 12 #define ZYNQMP_RESET_DP 3 13 #define ZYNQMP_RESET_SWDT_CRF 13 #define ZYNQMP_RESET_SWDT_CRF 4 14 #define ZYNQMP_RESET_AFI_FM5 14 #define ZYNQMP_RESET_AFI_FM5 5 15 #define ZYNQMP_RESET_AFI_FM4 15 #define ZYNQMP_RESET_AFI_FM4 6 16 #define ZYNQMP_RESET_AFI_FM3 16 #define ZYNQMP_RESET_AFI_FM3 7 17 #define ZYNQMP_RESET_AFI_FM2 17 #define ZYNQMP_RESET_AFI_FM2 8 18 #define ZYNQMP_RESET_AFI_FM1 18 #define ZYNQMP_RESET_AFI_FM1 9 19 #define ZYNQMP_RESET_AFI_FM0 19 #define ZYNQMP_RESET_AFI_FM0 10 20 #define ZYNQMP_RESET_GDMA 20 #define ZYNQMP_RESET_GDMA 11 21 #define ZYNQMP_RESET_GPU_PP1 21 #define ZYNQMP_RESET_GPU_PP1 12 22 #define ZYNQMP_RESET_GPU_PP0 22 #define ZYNQMP_RESET_GPU_PP0 13 23 #define ZYNQMP_RESET_GPU 23 #define ZYNQMP_RESET_GPU 14 24 #define ZYNQMP_RESET_GT 24 #define ZYNQMP_RESET_GT 15 25 #define ZYNQMP_RESET_SATA 25 #define ZYNQMP_RESET_SATA 16 26 #define ZYNQMP_RESET_ACPU3_PWRON 26 #define ZYNQMP_RESET_ACPU3_PWRON 17 27 #define ZYNQMP_RESET_ACPU2_PWRON 27 #define ZYNQMP_RESET_ACPU2_PWRON 18 28 #define ZYNQMP_RESET_ACPU1_PWRON 28 #define ZYNQMP_RESET_ACPU1_PWRON 19 29 #define ZYNQMP_RESET_ACPU0_PWRON 29 #define ZYNQMP_RESET_ACPU0_PWRON 20 30 #define ZYNQMP_RESET_APU_L2 30 #define ZYNQMP_RESET_APU_L2 21 31 #define ZYNQMP_RESET_ACPU3 31 #define ZYNQMP_RESET_ACPU3 22 32 #define ZYNQMP_RESET_ACPU2 32 #define ZYNQMP_RESET_ACPU2 23 33 #define ZYNQMP_RESET_ACPU1 33 #define ZYNQMP_RESET_ACPU1 24 34 #define ZYNQMP_RESET_ACPU0 34 #define ZYNQMP_RESET_ACPU0 25 35 #define ZYNQMP_RESET_DDR 35 #define ZYNQMP_RESET_DDR 26 36 #define ZYNQMP_RESET_APM_FPD 36 #define ZYNQMP_RESET_APM_FPD 27 37 #define ZYNQMP_RESET_SOFT 37 #define ZYNQMP_RESET_SOFT 28 38 #define ZYNQMP_RESET_GEM0 38 #define ZYNQMP_RESET_GEM0 29 39 #define ZYNQMP_RESET_GEM1 39 #define ZYNQMP_RESET_GEM1 30 40 #define ZYNQMP_RESET_GEM2 40 #define ZYNQMP_RESET_GEM2 31 41 #define ZYNQMP_RESET_GEM3 41 #define ZYNQMP_RESET_GEM3 32 42 #define ZYNQMP_RESET_QSPI 42 #define ZYNQMP_RESET_QSPI 33 43 #define ZYNQMP_RESET_UART0 43 #define ZYNQMP_RESET_UART0 34 44 #define ZYNQMP_RESET_UART1 44 #define ZYNQMP_RESET_UART1 35 45 #define ZYNQMP_RESET_SPI0 45 #define ZYNQMP_RESET_SPI0 36 46 #define ZYNQMP_RESET_SPI1 46 #define ZYNQMP_RESET_SPI1 37 47 #define ZYNQMP_RESET_SDIO0 47 #define ZYNQMP_RESET_SDIO0 38 48 #define ZYNQMP_RESET_SDIO1 48 #define ZYNQMP_RESET_SDIO1 39 49 #define ZYNQMP_RESET_CAN0 49 #define ZYNQMP_RESET_CAN0 40 50 #define ZYNQMP_RESET_CAN1 50 #define ZYNQMP_RESET_CAN1 41 51 #define ZYNQMP_RESET_I2C0 51 #define ZYNQMP_RESET_I2C0 42 52 #define ZYNQMP_RESET_I2C1 52 #define ZYNQMP_RESET_I2C1 43 53 #define ZYNQMP_RESET_TTC0 53 #define ZYNQMP_RESET_TTC0 44 54 #define ZYNQMP_RESET_TTC1 54 #define ZYNQMP_RESET_TTC1 45 55 #define ZYNQMP_RESET_TTC2 55 #define ZYNQMP_RESET_TTC2 46 56 #define ZYNQMP_RESET_TTC3 56 #define ZYNQMP_RESET_TTC3 47 57 #define ZYNQMP_RESET_SWDT_CRL 57 #define ZYNQMP_RESET_SWDT_CRL 48 58 #define ZYNQMP_RESET_NAND 58 #define ZYNQMP_RESET_NAND 49 59 #define ZYNQMP_RESET_ADMA 59 #define ZYNQMP_RESET_ADMA 50 60 #define ZYNQMP_RESET_GPIO 60 #define ZYNQMP_RESET_GPIO 51 61 #define ZYNQMP_RESET_IOU_CC 61 #define ZYNQMP_RESET_IOU_CC 52 62 #define ZYNQMP_RESET_TIMESTAMP 62 #define ZYNQMP_RESET_TIMESTAMP 53 63 #define ZYNQMP_RESET_RPU_R50 63 #define ZYNQMP_RESET_RPU_R50 54 64 #define ZYNQMP_RESET_RPU_R51 64 #define ZYNQMP_RESET_RPU_R51 55 65 #define ZYNQMP_RESET_RPU_AMBA 65 #define ZYNQMP_RESET_RPU_AMBA 56 66 #define ZYNQMP_RESET_OCM 66 #define ZYNQMP_RESET_OCM 57 67 #define ZYNQMP_RESET_RPU_PGE 67 #define ZYNQMP_RESET_RPU_PGE 58 68 #define ZYNQMP_RESET_USB0_CORERESET 68 #define ZYNQMP_RESET_USB0_CORERESET 59 69 #define ZYNQMP_RESET_USB1_CORERESET 69 #define ZYNQMP_RESET_USB1_CORERESET 60 70 #define ZYNQMP_RESET_USB0_HIBERRESET 70 #define ZYNQMP_RESET_USB0_HIBERRESET 61 71 #define ZYNQMP_RESET_USB1_HIBERRESET 71 #define ZYNQMP_RESET_USB1_HIBERRESET 62 72 #define ZYNQMP_RESET_USB0_APB 72 #define ZYNQMP_RESET_USB0_APB 63 73 #define ZYNQMP_RESET_USB1_APB 73 #define ZYNQMP_RESET_USB1_APB 64 74 #define ZYNQMP_RESET_IPI 74 #define ZYNQMP_RESET_IPI 65 75 #define ZYNQMP_RESET_APM_LPD 75 #define ZYNQMP_RESET_APM_LPD 66 76 #define ZYNQMP_RESET_RTC 76 #define ZYNQMP_RESET_RTC 67 77 #define ZYNQMP_RESET_SYSMON 77 #define ZYNQMP_RESET_SYSMON 68 78 #define ZYNQMP_RESET_AFI_FM6 78 #define ZYNQMP_RESET_AFI_FM6 69 79 #define ZYNQMP_RESET_LPD_SWDT 79 #define ZYNQMP_RESET_LPD_SWDT 70 80 #define ZYNQMP_RESET_FPD 80 #define ZYNQMP_RESET_FPD 71 81 #define ZYNQMP_RESET_RPU_DBG1 81 #define ZYNQMP_RESET_RPU_DBG1 72 82 #define ZYNQMP_RESET_RPU_DBG0 82 #define ZYNQMP_RESET_RPU_DBG0 73 83 #define ZYNQMP_RESET_DBG_LPD 83 #define ZYNQMP_RESET_DBG_LPD 74 84 #define ZYNQMP_RESET_DBG_FPD 84 #define ZYNQMP_RESET_DBG_FPD 75 85 #define ZYNQMP_RESET_APLL 85 #define ZYNQMP_RESET_APLL 76 86 #define ZYNQMP_RESET_DPLL 86 #define ZYNQMP_RESET_DPLL 77 87 #define ZYNQMP_RESET_VPLL 87 #define ZYNQMP_RESET_VPLL 78 88 #define ZYNQMP_RESET_IOPLL 88 #define ZYNQMP_RESET_IOPLL 79 89 #define ZYNQMP_RESET_RPLL 89 #define ZYNQMP_RESET_RPLL 80 90 #define ZYNQMP_RESET_GPO3_PL_0 90 #define ZYNQMP_RESET_GPO3_PL_0 81 91 #define ZYNQMP_RESET_GPO3_PL_1 91 #define ZYNQMP_RESET_GPO3_PL_1 82 92 #define ZYNQMP_RESET_GPO3_PL_2 92 #define ZYNQMP_RESET_GPO3_PL_2 83 93 #define ZYNQMP_RESET_GPO3_PL_3 93 #define ZYNQMP_RESET_GPO3_PL_3 84 94 #define ZYNQMP_RESET_GPO3_PL_4 94 #define ZYNQMP_RESET_GPO3_PL_4 85 95 #define ZYNQMP_RESET_GPO3_PL_5 95 #define ZYNQMP_RESET_GPO3_PL_5 86 96 #define ZYNQMP_RESET_GPO3_PL_6 96 #define ZYNQMP_RESET_GPO3_PL_6 87 97 #define ZYNQMP_RESET_GPO3_PL_7 97 #define ZYNQMP_RESET_GPO3_PL_7 88 98 #define ZYNQMP_RESET_GPO3_PL_8 98 #define ZYNQMP_RESET_GPO3_PL_8 89 99 #define ZYNQMP_RESET_GPO3_PL_9 99 #define ZYNQMP_RESET_GPO3_PL_9 90 100 #define ZYNQMP_RESET_GPO3_PL_10 100 #define ZYNQMP_RESET_GPO3_PL_10 91 101 #define ZYNQMP_RESET_GPO3_PL_11 101 #define ZYNQMP_RESET_GPO3_PL_11 92 102 #define ZYNQMP_RESET_GPO3_PL_12 102 #define ZYNQMP_RESET_GPO3_PL_12 93 103 #define ZYNQMP_RESET_GPO3_PL_13 103 #define ZYNQMP_RESET_GPO3_PL_13 94 104 #define ZYNQMP_RESET_GPO3_PL_14 104 #define ZYNQMP_RESET_GPO3_PL_14 95 105 #define ZYNQMP_RESET_GPO3_PL_15 105 #define ZYNQMP_RESET_GPO3_PL_15 96 106 #define ZYNQMP_RESET_GPO3_PL_16 106 #define ZYNQMP_RESET_GPO3_PL_16 97 107 #define ZYNQMP_RESET_GPO3_PL_17 107 #define ZYNQMP_RESET_GPO3_PL_17 98 108 #define ZYNQMP_RESET_GPO3_PL_18 108 #define ZYNQMP_RESET_GPO3_PL_18 99 109 #define ZYNQMP_RESET_GPO3_PL_19 109 #define ZYNQMP_RESET_GPO3_PL_19 100 110 #define ZYNQMP_RESET_GPO3_PL_20 110 #define ZYNQMP_RESET_GPO3_PL_20 101 111 #define ZYNQMP_RESET_GPO3_PL_21 111 #define ZYNQMP_RESET_GPO3_PL_21 102 112 #define ZYNQMP_RESET_GPO3_PL_22 112 #define ZYNQMP_RESET_GPO3_PL_22 103 113 #define ZYNQMP_RESET_GPO3_PL_23 113 #define ZYNQMP_RESET_GPO3_PL_23 104 114 #define ZYNQMP_RESET_GPO3_PL_24 114 #define ZYNQMP_RESET_GPO3_PL_24 105 115 #define ZYNQMP_RESET_GPO3_PL_25 115 #define ZYNQMP_RESET_GPO3_PL_25 106 116 #define ZYNQMP_RESET_GPO3_PL_26 116 #define ZYNQMP_RESET_GPO3_PL_26 107 117 #define ZYNQMP_RESET_GPO3_PL_27 117 #define ZYNQMP_RESET_GPO3_PL_27 108 118 #define ZYNQMP_RESET_GPO3_PL_28 118 #define ZYNQMP_RESET_GPO3_PL_28 109 119 #define ZYNQMP_RESET_GPO3_PL_29 119 #define ZYNQMP_RESET_GPO3_PL_29 110 120 #define ZYNQMP_RESET_GPO3_PL_30 120 #define ZYNQMP_RESET_GPO3_PL_30 111 121 #define ZYNQMP_RESET_GPO3_PL_31 121 #define ZYNQMP_RESET_GPO3_PL_31 112 122 #define ZYNQMP_RESET_RPU_LS 122 #define ZYNQMP_RESET_RPU_LS 113 123 #define ZYNQMP_RESET_PS_ONLY 123 #define ZYNQMP_RESET_PS_ONLY 114 124 #define ZYNQMP_RESET_PL 124 #define ZYNQMP_RESET_PL 115 125 #define ZYNQMP_RESET_PS_PL0 125 #define ZYNQMP_RESET_PS_PL0 116 126 #define ZYNQMP_RESET_PS_PL1 126 #define ZYNQMP_RESET_PS_PL1 117 127 #define ZYNQMP_RESET_PS_PL2 127 #define ZYNQMP_RESET_PS_PL2 118 128 #define ZYNQMP_RESET_PS_PL3 128 #define ZYNQMP_RESET_PS_PL3 119 129 129 130 #endif 130 #endif 131 131
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