1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * linux/include/asm-arm/hardware/amba_kmi.h 2 * linux/include/asm-arm/hardware/amba_kmi.h
4 * 3 *
5 * Internal header file for AMBA KMI ports 4 * Internal header file for AMBA KMI ports
6 * 5 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd 6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License as published by
>> 10 * the Free Software Foundation; either version 2 of the License, or
>> 11 * (at your option) any later version.
>> 12 *
>> 13 * This program is distributed in the hope that it will be useful,
>> 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 16 * GNU General Public License for more details.
>> 17 *
>> 18 * You should have received a copy of the GNU General Public License
>> 19 * along with this program; if not, write to the Free Software
>> 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> 21 *
8 * 22 *
9 * ------------------------------------------- 23 * ---------------------------------------------------------------------------
10 * From ARM PrimeCell(tm) PS2 Keyboard/Mouse 24 * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
11 * Reference Manual - ARM DDI 0143B - see htt 25 * Reference Manual - ARM DDI 0143B - see http://www.arm.com/
12 * ------------------------------------------- 26 * ---------------------------------------------------------------------------
13 */ 27 */
14 #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H 28 #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
15 #define ASM_ARM_HARDWARE_AMBA_KMI_H 29 #define ASM_ARM_HARDWARE_AMBA_KMI_H
16 30
17 /* 31 /*
18 * KMI control register: 32 * KMI control register:
19 * KMICR_TYPE 0 = PS2/AT mode, 1 = No l 33 * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
20 * KMICR_RXINTREN 1 = enable RX interrupts 34 * KMICR_RXINTREN 1 = enable RX interrupts
21 * KMICR_TXINTREN 1 = enable TX interrupts 35 * KMICR_TXINTREN 1 = enable TX interrupts
22 * KMICR_EN 1 = enable KMI 36 * KMICR_EN 1 = enable KMI
23 * KMICR_FD 1 = force KMI data low 37 * KMICR_FD 1 = force KMI data low
24 * KMICR_FC 1 = force KMI clock low 38 * KMICR_FC 1 = force KMI clock low
25 */ 39 */
26 #define KMICR (KMI_BASE + 0x00) 40 #define KMICR (KMI_BASE + 0x00)
27 #define KMICR_TYPE (1 << 5) 41 #define KMICR_TYPE (1 << 5)
28 #define KMICR_RXINTREN (1 << 4) 42 #define KMICR_RXINTREN (1 << 4)
29 #define KMICR_TXINTREN (1 << 3) 43 #define KMICR_TXINTREN (1 << 3)
30 #define KMICR_EN (1 << 2) 44 #define KMICR_EN (1 << 2)
31 #define KMICR_FD (1 << 1) 45 #define KMICR_FD (1 << 1)
32 #define KMICR_FC (1 << 0) 46 #define KMICR_FC (1 << 0)
33 47
34 /* 48 /*
35 * KMI status register: 49 * KMI status register:
36 * KMISTAT_TXEMPTY 1 = transmitter register 50 * KMISTAT_TXEMPTY 1 = transmitter register empty
37 * KMISTAT_TXBUSY 1 = currently sending dat 51 * KMISTAT_TXBUSY 1 = currently sending data
38 * KMISTAT_RXFULL 1 = receiver register rea 52 * KMISTAT_RXFULL 1 = receiver register ready to be read
39 * KMISTAT_RXBUSY 1 = currently receiving d 53 * KMISTAT_RXBUSY 1 = currently receiving data
40 * KMISTAT_RXPARITY parity of last databyte r 54 * KMISTAT_RXPARITY parity of last databyte received
41 * KMISTAT_IC current level of KMI cloc 55 * KMISTAT_IC current level of KMI clock input
42 * KMISTAT_ID current level of KMI data 56 * KMISTAT_ID current level of KMI data input
43 */ 57 */
44 #define KMISTAT (KMI_BASE + 0x04) 58 #define KMISTAT (KMI_BASE + 0x04)
45 #define KMISTAT_TXEMPTY (1 << 6) 59 #define KMISTAT_TXEMPTY (1 << 6)
46 #define KMISTAT_TXBUSY (1 << 5) 60 #define KMISTAT_TXBUSY (1 << 5)
47 #define KMISTAT_RXFULL (1 << 4) 61 #define KMISTAT_RXFULL (1 << 4)
48 #define KMISTAT_RXBUSY (1 << 3) 62 #define KMISTAT_RXBUSY (1 << 3)
49 #define KMISTAT_RXPARITY (1 << 2) 63 #define KMISTAT_RXPARITY (1 << 2)
50 #define KMISTAT_IC (1 << 1) 64 #define KMISTAT_IC (1 << 1)
51 #define KMISTAT_ID (1 << 0) 65 #define KMISTAT_ID (1 << 0)
52 66
53 /* 67 /*
54 * KMI data register 68 * KMI data register
55 */ 69 */
56 #define KMIDATA (KMI_BASE + 0x08) 70 #define KMIDATA (KMI_BASE + 0x08)
57 71
58 /* 72 /*
59 * KMI clock divisor: to generate 8MHz interna 73 * KMI clock divisor: to generate 8MHz internal clock
60 * div = (ref / 8MHz) - 1; 0 <= div <= 15 74 * div = (ref / 8MHz) - 1; 0 <= div <= 15
61 */ 75 */
62 #define KMICLKDIV (KMI_BASE + 0x0c) 76 #define KMICLKDIV (KMI_BASE + 0x0c)
63 77
64 /* 78 /*
65 * KMI interrupt register: 79 * KMI interrupt register:
66 * KMIIR_TXINTR 1 = transmit interrupt as 80 * KMIIR_TXINTR 1 = transmit interrupt asserted
67 * KMIIR_RXINTR 1 = receive interrupt ass 81 * KMIIR_RXINTR 1 = receive interrupt asserted
68 */ 82 */
69 #define KMIIR (KMI_BASE + 0x10) 83 #define KMIIR (KMI_BASE + 0x10)
70 #define KMIIR_TXINTR (1 << 1) 84 #define KMIIR_TXINTR (1 << 1)
71 #define KMIIR_RXINTR (1 << 0) 85 #define KMIIR_RXINTR (1 << 0)
72 86
73 /* 87 /*
74 * The size of the KMI primecell 88 * The size of the KMI primecell
75 */ 89 */
76 #define KMI_SIZE (0x100) 90 #define KMI_SIZE (0x100)
77 91
78 #endif 92 #endif
79 93
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