1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * linux/include/asm-arm/hardware/serial_amba 3 * linux/include/asm-arm/hardware/serial_amba.h
4 * 4 *
5 * Internal header file for AMBA serial ports 5 * Internal header file for AMBA serial ports
6 * 6 *
7 * Copyright (C) ARM Limited 7 * Copyright (C) ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd 8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 */ 9 */
10 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H 10 #ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
11 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H 11 #define ASM_ARM_HARDWARE_SERIAL_AMBA_H
12 12
13 #ifndef __ASSEMBLY__ <<
14 #include <linux/bitfield.h> <<
15 #include <linux/bits.h> <<
16 #endif <<
17 <<
18 #include <linux/types.h> 13 #include <linux/types.h>
19 14
20 /* ------------------------------------------- 15 /* -------------------------------------------------------------------------------
21 * From AMBA UART (PL010) Block Specification 16 * From AMBA UART (PL010) Block Specification
22 * ------------------------------------------- 17 * -------------------------------------------------------------------------------
23 * UART Register Offsets. 18 * UART Register Offsets.
24 */ 19 */
25 #define UART01x_DR 0x00 /* Dat 20 #define UART01x_DR 0x00 /* Data read or written from the interface. */
26 #define UART01x_RSR 0x04 /* Rec 21 #define UART01x_RSR 0x04 /* Receive status register (Read). */
27 #define UART01x_ECR 0x04 /* Err 22 #define UART01x_ECR 0x04 /* Error clear register (Write). */
28 #define UART010_LCRH 0x08 /* Lin 23 #define UART010_LCRH 0x08 /* Line control register, high byte. */
29 #define ST_UART011_DMAWM 0x08 /* DMA 24 #define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
30 #define UART010_LCRM 0x0C /* Lin 25 #define UART010_LCRM 0x0C /* Line control register, middle byte. */
31 #define ST_UART011_TIMEOUT 0x0C /* Tim 26 #define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
32 #define UART010_LCRL 0x10 /* Lin 27 #define UART010_LCRL 0x10 /* Line control register, low byte. */
33 #define UART010_CR 0x14 /* Con 28 #define UART010_CR 0x14 /* Control register. */
34 #define UART01x_FR 0x18 /* Fla 29 #define UART01x_FR 0x18 /* Flag register (Read only). */
35 #define UART010_IIR 0x1C /* Int 30 #define UART010_IIR 0x1C /* Interrupt identification register (Read). */
36 #define UART010_ICR 0x1C /* Int 31 #define UART010_ICR 0x1C /* Interrupt clear register (Write). */
37 #define ST_UART011_LCRH_RX 0x1C /* Rx 32 #define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
38 #define UART01x_ILPR 0x20 /* IrD 33 #define UART01x_ILPR 0x20 /* IrDA low power counter register. */
39 #define UART011_IBRD 0x24 /* Int 34 #define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
40 #define UART011_FBRD 0x28 /* Fra 35 #define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
41 #define UART011_LCRH 0x2c /* Lin 36 #define UART011_LCRH 0x2c /* Line control register. */
42 #define ST_UART011_LCRH_TX 0x2c /* Tx 37 #define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
43 #define UART011_CR 0x30 /* Con 38 #define UART011_CR 0x30 /* Control register. */
44 #define UART011_IFLS 0x34 /* Int 39 #define UART011_IFLS 0x34 /* Interrupt fifo level select. */
45 #define UART011_IMSC 0x38 /* Int 40 #define UART011_IMSC 0x38 /* Interrupt mask. */
46 #define UART011_RIS 0x3c /* Raw 41 #define UART011_RIS 0x3c /* Raw interrupt status. */
47 #define UART011_MIS 0x40 /* Mas 42 #define UART011_MIS 0x40 /* Masked interrupt status. */
48 #define UART011_ICR 0x44 /* Int 43 #define UART011_ICR 0x44 /* Interrupt clear register. */
49 #define UART011_DMACR 0x48 /* DMA 44 #define UART011_DMACR 0x48 /* DMA control register. */
50 #define ST_UART011_XFCR 0x50 /* XON 45 #define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
51 #define ST_UART011_XON1 0x54 /* XON 46 #define ST_UART011_XON1 0x54 /* XON1 register. */
52 #define ST_UART011_XON2 0x58 /* XON 47 #define ST_UART011_XON2 0x58 /* XON2 register. */
53 #define ST_UART011_XOFF1 0x5C /* XON 48 #define ST_UART011_XOFF1 0x5C /* XON1 register. */
54 #define ST_UART011_XOFF2 0x60 /* XON 49 #define ST_UART011_XOFF2 0x60 /* XON2 register. */
55 #define ST_UART011_ITCR 0x80 /* Int 50 #define ST_UART011_ITCR 0x80 /* Integration test control register. */
56 #define ST_UART011_ITIP 0x84 /* Int 51 #define ST_UART011_ITIP 0x84 /* Integration test input register. */
57 #define ST_UART011_ABCR 0x100 /* Aut 52 #define ST_UART011_ABCR 0x100 /* Autobaud control register. */
58 #define ST_UART011_ABIMSC 0x15C /* Aut 53 #define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
59 54
60 /* 55 /*
61 * ZTE UART register offsets. This UART has a 56 * ZTE UART register offsets. This UART has a radically different address
62 * allocation from the ARM and ST variants, so 57 * allocation from the ARM and ST variants, so we list all registers here.
63 * We assume unlisted registers do not exist. 58 * We assume unlisted registers do not exist.
64 */ 59 */
65 #define ZX_UART011_DR 0x04 60 #define ZX_UART011_DR 0x04
66 #define ZX_UART011_FR 0x14 61 #define ZX_UART011_FR 0x14
67 #define ZX_UART011_IBRD 0x24 62 #define ZX_UART011_IBRD 0x24
68 #define ZX_UART011_FBRD 0x28 63 #define ZX_UART011_FBRD 0x28
69 #define ZX_UART011_LCRH 0x30 64 #define ZX_UART011_LCRH 0x30
70 #define ZX_UART011_CR 0x34 65 #define ZX_UART011_CR 0x34
71 #define ZX_UART011_IFLS 0x38 66 #define ZX_UART011_IFLS 0x38
72 #define ZX_UART011_IMSC 0x40 67 #define ZX_UART011_IMSC 0x40
73 #define ZX_UART011_RIS 0x44 68 #define ZX_UART011_RIS 0x44
74 #define ZX_UART011_MIS 0x48 69 #define ZX_UART011_MIS 0x48
75 #define ZX_UART011_ICR 0x4c 70 #define ZX_UART011_ICR 0x4c
76 #define ZX_UART011_DMACR 0x50 71 #define ZX_UART011_DMACR 0x50
77 72
78 #define UART011_DR_OE BIT(11) !! 73 #define UART011_DR_OE (1 << 11)
79 #define UART011_DR_BE BIT(10) !! 74 #define UART011_DR_BE (1 << 10)
80 #define UART011_DR_PE BIT(9) !! 75 #define UART011_DR_PE (1 << 9)
81 #define UART011_DR_FE BIT(8) !! 76 #define UART011_DR_FE (1 << 8)
82 !! 77
83 #define UART01x_RSR_OE BIT(3) !! 78 #define UART01x_RSR_OE 0x08
84 #define UART01x_RSR_BE BIT(2) !! 79 #define UART01x_RSR_BE 0x04
85 #define UART01x_RSR_PE BIT(1) !! 80 #define UART01x_RSR_PE 0x02
86 #define UART01x_RSR_FE BIT(0) !! 81 #define UART01x_RSR_FE 0x01
87 !! 82
88 #define UART011_FR_RI BIT(8) !! 83 #define UART011_FR_RI 0x100
89 #define UART011_FR_TXFE BIT(7) !! 84 #define UART011_FR_TXFE 0x080
90 #define UART011_FR_RXFF BIT(6) !! 85 #define UART011_FR_RXFF 0x040
91 #define UART01x_FR_TXFF (1 << 5) !! 86 #define UART01x_FR_TXFF 0x020
92 #define UART01x_FR_RXFE BIT(4) !! 87 #define UART01x_FR_RXFE 0x010
93 #define UART01x_FR_BUSY (1 << 3) !! 88 #define UART01x_FR_BUSY 0x008
94 #define UART01x_FR_DCD BIT(2) !! 89 #define UART01x_FR_DCD 0x004
95 #define UART01x_FR_DSR BIT(1) !! 90 #define UART01x_FR_DSR 0x002
96 #define UART01x_FR_CTS BIT(0) !! 91 #define UART01x_FR_CTS 0x001
97 #define UART01x_FR_TMSK (UART01x_FR_TX 92 #define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
98 93
99 /* 94 /*
100 * Some bits of Flag Register on ZTE device ha 95 * Some bits of Flag Register on ZTE device have different position from
101 * standard ones. 96 * standard ones.
102 */ 97 */
103 #define ZX_UART01x_FR_BUSY BIT(8) !! 98 #define ZX_UART01x_FR_BUSY 0x100
104 #define ZX_UART01x_FR_DSR BIT(3) !! 99 #define ZX_UART01x_FR_DSR 0x008
105 #define ZX_UART01x_FR_CTS BIT(1) !! 100 #define ZX_UART01x_FR_CTS 0x002
106 #define ZX_UART011_FR_RI BIT(0) !! 101 #define ZX_UART011_FR_RI 0x001
107 !! 102
108 #define UART011_CR_CTSEN BIT(15) /* CTS !! 103 #define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
109 #define UART011_CR_RTSEN BIT(14) /* RTS !! 104 #define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
110 #define UART011_CR_OUT2 BIT(13) /* OUT !! 105 #define UART011_CR_OUT2 0x2000 /* OUT2 */
111 #define UART011_CR_OUT1 BIT(12) /* OUT !! 106 #define UART011_CR_OUT1 0x1000 /* OUT1 */
112 #define UART011_CR_RTS BIT(11) /* RTS !! 107 #define UART011_CR_RTS 0x0800 /* RTS */
113 #define UART011_CR_DTR BIT(10) /* DTR !! 108 #define UART011_CR_DTR 0x0400 /* DTR */
114 #define UART011_CR_RXE BIT(9) /* rec !! 109 #define UART011_CR_RXE 0x0200 /* receive enable */
115 #define UART011_CR_TXE BIT(8) /* tra !! 110 #define UART011_CR_TXE 0x0100 /* transmit enable */
116 #define UART011_CR_LBE BIT(7) /* loo !! 111 #define UART011_CR_LBE 0x0080 /* loopback enable */
117 #define UART010_CR_RTIE BIT(6) !! 112 #define UART010_CR_RTIE 0x0040
118 #define UART010_CR_TIE BIT(5) !! 113 #define UART010_CR_TIE 0x0020
119 #define UART010_CR_RIE BIT(4) !! 114 #define UART010_CR_RIE 0x0010
120 #define UART010_CR_MSIE BIT(3) !! 115 #define UART010_CR_MSIE 0x0008
121 #define ST_UART011_CR_OVSFACT BIT(3) /* Ove !! 116 #define ST_UART011_CR_OVSFACT 0x0008 /* Oversampling factor */
122 #define UART01x_CR_IIRLP BIT(2) /* SIR !! 117 #define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
123 #define UART01x_CR_SIREN BIT(1) /* SIR !! 118 #define UART01x_CR_SIREN 0x0002 /* SIR enable */
124 #define UART01x_CR_UARTEN BIT(0) /* UAR !! 119 #define UART01x_CR_UARTEN 0x0001 /* UART enable */
125 !! 120
126 #define UART011_LCRH_SPS BIT(7) !! 121 #define UART011_LCRH_SPS 0x80
127 #define UART01x_LCRH_WLEN_8 0x60 122 #define UART01x_LCRH_WLEN_8 0x60
128 #define UART01x_LCRH_WLEN_7 0x40 123 #define UART01x_LCRH_WLEN_7 0x40
129 #define UART01x_LCRH_WLEN_6 0x20 124 #define UART01x_LCRH_WLEN_6 0x20
130 #define UART01x_LCRH_WLEN_5 0x00 125 #define UART01x_LCRH_WLEN_5 0x00
131 #define UART01x_LCRH_FEN BIT(4) !! 126 #define UART01x_LCRH_FEN 0x10
132 #define UART01x_LCRH_STP2 BIT(3) !! 127 #define UART01x_LCRH_STP2 0x08
133 #define UART01x_LCRH_EPS BIT(2) !! 128 #define UART01x_LCRH_EPS 0x04
134 #define UART01x_LCRH_PEN BIT(1) !! 129 #define UART01x_LCRH_PEN 0x02
135 #define UART01x_LCRH_BRK BIT(0) !! 130 #define UART01x_LCRH_BRK 0x01
136 !! 131
137 #define ST_UART011_DMAWM_RX GENMASK(5, 3) !! 132 #define ST_UART011_DMAWM_RX_1 (0 << 3)
138 #define ST_UART011_DMAWM_RX_1 FIELD_PREP_CON !! 133 #define ST_UART011_DMAWM_RX_2 (1 << 3)
139 #define ST_UART011_DMAWM_RX_2 FIELD_PREP_CON !! 134 #define ST_UART011_DMAWM_RX_4 (2 << 3)
140 #define ST_UART011_DMAWM_RX_4 FIELD_PREP_CON !! 135 #define ST_UART011_DMAWM_RX_8 (3 << 3)
141 #define ST_UART011_DMAWM_RX_8 FIELD_PREP_CON !! 136 #define ST_UART011_DMAWM_RX_16 (4 << 3)
142 #define ST_UART011_DMAWM_RX_16 FIELD_PREP_CON !! 137 #define ST_UART011_DMAWM_RX_32 (5 << 3)
143 #define ST_UART011_DMAWM_RX_32 FIELD_PREP_CON !! 138 #define ST_UART011_DMAWM_RX_48 (6 << 3)
144 #define ST_UART011_DMAWM_RX_48 FIELD_PREP_CON !! 139 #define ST_UART011_DMAWM_TX_1 0
145 #define ST_UART011_DMAWM_TX GENMASK(2, 0) !! 140 #define ST_UART011_DMAWM_TX_2 1
146 #define ST_UART011_DMAWM_TX_1 FIELD_PREP_CON !! 141 #define ST_UART011_DMAWM_TX_4 2
147 #define ST_UART011_DMAWM_TX_2 FIELD_PREP_CON !! 142 #define ST_UART011_DMAWM_TX_8 3
148 #define ST_UART011_DMAWM_TX_4 FIELD_PREP_CON !! 143 #define ST_UART011_DMAWM_TX_16 4
149 #define ST_UART011_DMAWM_TX_8 FIELD_PREP_CON !! 144 #define ST_UART011_DMAWM_TX_32 5
150 #define ST_UART011_DMAWM_TX_16 FIELD_PREP_CON !! 145 #define ST_UART011_DMAWM_TX_48 6
151 #define ST_UART011_DMAWM_TX_32 FIELD_PREP_CON !! 146
152 #define ST_UART011_DMAWM_TX_48 FIELD_PREP_CON !! 147 #define UART010_IIR_RTIS 0x08
153 !! 148 #define UART010_IIR_TIS 0x04
154 #define UART010_IIR_RTIS BIT(3) !! 149 #define UART010_IIR_RIS 0x02
155 #define UART010_IIR_TIS BIT(2) !! 150 #define UART010_IIR_MIS 0x01
156 #define UART010_IIR_RIS BIT(1) !! 151
157 #define UART010_IIR_MIS BIT(0) !! 152 #define UART011_IFLS_RX1_8 (0 << 3)
158 !! 153 #define UART011_IFLS_RX2_8 (1 << 3)
159 #define UART011_IFLS_RXIFLSEL GENMASK(5, 3) !! 154 #define UART011_IFLS_RX4_8 (2 << 3)
160 #define UART011_IFLS_RX1_8 FIELD_PREP_CON !! 155 #define UART011_IFLS_RX6_8 (3 << 3)
161 #define UART011_IFLS_RX2_8 FIELD_PREP_CON !! 156 #define UART011_IFLS_RX7_8 (4 << 3)
162 #define UART011_IFLS_RX4_8 FIELD_PREP_CON !! 157 #define UART011_IFLS_TX1_8 (0 << 0)
163 #define UART011_IFLS_RX6_8 FIELD_PREP_CON !! 158 #define UART011_IFLS_TX2_8 (1 << 0)
164 #define UART011_IFLS_RX7_8 FIELD_PREP_CON !! 159 #define UART011_IFLS_TX4_8 (2 << 0)
165 #define UART011_IFLS_TXIFLSEL GENMASK(2, 0) !! 160 #define UART011_IFLS_TX6_8 (3 << 0)
166 #define UART011_IFLS_TX1_8 FIELD_PREP_CON !! 161 #define UART011_IFLS_TX7_8 (4 << 0)
167 #define UART011_IFLS_TX2_8 FIELD_PREP_CON <<
168 #define UART011_IFLS_TX4_8 FIELD_PREP_CON <<
169 #define UART011_IFLS_TX6_8 FIELD_PREP_CON <<
170 #define UART011_IFLS_TX7_8 FIELD_PREP_CON <<
171 /* special values for ST vendor with deeper fi 162 /* special values for ST vendor with deeper fifo */
172 #define UART011_IFLS_RX_HALF FIELD_PREP_CON !! 163 #define UART011_IFLS_RX_HALF (5 << 3)
173 #define UART011_IFLS_TX_HALF FIELD_PREP_CON !! 164 #define UART011_IFLS_TX_HALF (5 << 0)
174 165
175 #define UART011_OEIM BIT(10) /* ove !! 166 #define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
176 #define UART011_BEIM BIT(9) /* bre !! 167 #define UART011_BEIM (1 << 9) /* break error interrupt mask */
177 #define UART011_PEIM BIT(8) /* par !! 168 #define UART011_PEIM (1 << 8) /* parity error interrupt mask */
178 #define UART011_FEIM BIT(7) /* fra !! 169 #define UART011_FEIM (1 << 7) /* framing error interrupt mask */
179 #define UART011_RTIM BIT(6) /* rec !! 170 #define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
180 #define UART011_TXIM BIT(5) /* tra !! 171 #define UART011_TXIM (1 << 5) /* transmit interrupt mask */
181 #define UART011_RXIM BIT(4) /* rec !! 172 #define UART011_RXIM (1 << 4) /* receive interrupt mask */
182 #define UART011_DSRMIM BIT(3) /* DSR !! 173 #define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
183 #define UART011_DCDMIM BIT(2) /* DCD !! 174 #define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
184 #define UART011_CTSMIM BIT(1) /* CTS !! 175 #define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
185 #define UART011_RIMIM BIT(0) /* RI !! 176 #define UART011_RIMIM (1 << 0) /* RI interrupt mask */
186 !! 177
187 #define UART011_OEIS BIT(10) /* ove !! 178 #define UART011_OEIS (1 << 10) /* overrun error interrupt status */
188 #define UART011_BEIS BIT(9) /* bre !! 179 #define UART011_BEIS (1 << 9) /* break error interrupt status */
189 #define UART011_PEIS BIT(8) /* par !! 180 #define UART011_PEIS (1 << 8) /* parity error interrupt status */
190 #define UART011_FEIS BIT(7) /* fra !! 181 #define UART011_FEIS (1 << 7) /* framing error interrupt status */
191 #define UART011_RTIS BIT(6) /* rec !! 182 #define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
192 #define UART011_TXIS BIT(5) /* tra !! 183 #define UART011_TXIS (1 << 5) /* transmit interrupt status */
193 #define UART011_RXIS BIT(4) /* rec !! 184 #define UART011_RXIS (1 << 4) /* receive interrupt status */
194 #define UART011_DSRMIS BIT(3) /* DSR !! 185 #define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
195 #define UART011_DCDMIS BIT(2) /* DCD !! 186 #define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
196 #define UART011_CTSMIS BIT(1) /* CTS !! 187 #define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
197 #define UART011_RIMIS BIT(0) /* RI !! 188 #define UART011_RIMIS (1 << 0) /* RI interrupt status */
198 !! 189
199 #define UART011_OEIC BIT(10) /* ove !! 190 #define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
200 #define UART011_BEIC BIT(9) /* bre !! 191 #define UART011_BEIC (1 << 9) /* break error interrupt clear */
201 #define UART011_PEIC BIT(8) /* par !! 192 #define UART011_PEIC (1 << 8) /* parity error interrupt clear */
202 #define UART011_FEIC BIT(7) /* fra !! 193 #define UART011_FEIC (1 << 7) /* framing error interrupt clear */
203 #define UART011_RTIC BIT(6) /* rec !! 194 #define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
204 #define UART011_TXIC BIT(5) /* tra !! 195 #define UART011_TXIC (1 << 5) /* transmit interrupt clear */
205 #define UART011_RXIC BIT(4) /* rec !! 196 #define UART011_RXIC (1 << 4) /* receive interrupt clear */
206 #define UART011_DSRMIC BIT(3) /* DSR !! 197 #define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
207 #define UART011_DCDMIC BIT(2) /* DCD !! 198 #define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
208 #define UART011_CTSMIC BIT(1) /* CTS !! 199 #define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
209 #define UART011_RIMIC BIT(0) /* RI !! 200 #define UART011_RIMIC (1 << 0) /* RI interrupt clear */
210 !! 201
211 #define UART011_DMAONERR BIT(2) /* dis !! 202 #define UART011_DMAONERR (1 << 2) /* disable dma on error */
212 #define UART011_TXDMAE BIT(1) /* ena !! 203 #define UART011_TXDMAE (1 << 1) /* enable transmit dma */
213 #define UART011_RXDMAE BIT(0) /* ena !! 204 #define UART011_RXDMAE (1 << 0) /* enable receive dma */
214 205
215 #define UART01x_RSR_ANY (UART01x_RSR_O !! 206 #define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
216 #define UART01x_FR_MODEM_ANY (UART01x_FR_DC !! 207 #define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
217 208
218 #ifndef __ASSEMBLY__ 209 #ifndef __ASSEMBLY__
219 struct amba_device; /* in uncompress this is i 210 struct amba_device; /* in uncompress this is included but amba/bus.h is not */
220 struct amba_pl010_data { 211 struct amba_pl010_data {
221 void (*set_mctrl)(struct amba_device * 212 void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
222 }; 213 };
223 214
224 struct dma_chan; 215 struct dma_chan;
225 struct amba_pl011_data { 216 struct amba_pl011_data {
226 bool (*dma_filter)(struct dma_chan *ch 217 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
227 void *dma_rx_param; 218 void *dma_rx_param;
228 void *dma_tx_param; 219 void *dma_tx_param;
229 bool dma_rx_poll_enable; 220 bool dma_rx_poll_enable;
230 unsigned int dma_rx_poll_rate; 221 unsigned int dma_rx_poll_rate;
231 unsigned int dma_rx_poll_timeout; 222 unsigned int dma_rx_poll_timeout;
232 void (*init)(void); !! 223 void (*init) (void);
233 void (*exit)(void); !! 224 void (*exit) (void);
234 }; 225 };
235 #endif 226 #endif
236 227
237 #endif 228 #endif
238 229
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