1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_BRCMPHY_H 2 #ifndef _LINUX_BRCMPHY_H
3 #define _LINUX_BRCMPHY_H 3 #define _LINUX_BRCMPHY_H
4 4
5 #include <linux/phy.h> 5 #include <linux/phy.h>
6 6
7 /* All Broadcom Ethernet switches have a pseud 7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers 8 * to configure the switch internal registers via MDIO accesses.
9 */ 9 */
10 #define BRCM_PSEUDO_PHY_ADDR 30 10 #define BRCM_PSEUDO_PHY_ADDR 30
11 11
12 #define PHY_ID_BCM50610 0x0143 12 #define PHY_ID_BCM50610 0x0143bd60
13 #define PHY_ID_BCM50610M 0x0143 13 #define PHY_ID_BCM50610M 0x0143bd70
14 #define PHY_ID_BCM5221 0x0040 <<
15 #define PHY_ID_BCM5241 0x0143 14 #define PHY_ID_BCM5241 0x0143bc30
16 #define PHY_ID_BCMAC131 0x0143 15 #define PHY_ID_BCMAC131 0x0143bc70
17 #define PHY_ID_BCM5481 0x0143 16 #define PHY_ID_BCM5481 0x0143bca0
18 #define PHY_ID_BCM5395 0x0143 17 #define PHY_ID_BCM5395 0x0143bcf0
19 #define PHY_ID_BCM53125 0x0362 18 #define PHY_ID_BCM53125 0x03625f20
20 #define PHY_ID_BCM53128 0x0362 <<
21 #define PHY_ID_BCM54810 0x0362 19 #define PHY_ID_BCM54810 0x03625d00
22 #define PHY_ID_BCM54811 0x0362 20 #define PHY_ID_BCM54811 0x03625cc0
23 #define PHY_ID_BCM5482 0x0143 21 #define PHY_ID_BCM5482 0x0143bcb0
24 #define PHY_ID_BCM5411 0x0020 22 #define PHY_ID_BCM5411 0x00206070
25 #define PHY_ID_BCM5421 0x0020 23 #define PHY_ID_BCM5421 0x002060e0
26 #define PHY_ID_BCM54210E 0x600d 24 #define PHY_ID_BCM54210E 0x600d84a0
27 #define PHY_ID_BCM5464 0x0020 25 #define PHY_ID_BCM5464 0x002060b0
28 #define PHY_ID_BCM5461 0x0020 26 #define PHY_ID_BCM5461 0x002060c0
29 #define PHY_ID_BCM54612E 0x0362 27 #define PHY_ID_BCM54612E 0x03625e60
30 #define PHY_ID_BCM54616S 0x0362 28 #define PHY_ID_BCM54616S 0x03625d10
31 #define PHY_ID_BCM54140 0xae02 29 #define PHY_ID_BCM54140 0xae025009
32 #define PHY_ID_BCM57780 0x0362 30 #define PHY_ID_BCM57780 0x03625d90
33 #define PHY_ID_BCM89610 0x0362 31 #define PHY_ID_BCM89610 0x03625cd0
34 32
35 #define PHY_ID_BCM72113 0x3590 <<
36 #define PHY_ID_BCM72116 0x3590 <<
37 #define PHY_ID_BCM72165 0x3590 <<
38 #define PHY_ID_BCM7250 0xae02 33 #define PHY_ID_BCM7250 0xae025280
39 #define PHY_ID_BCM7255 0xae02 34 #define PHY_ID_BCM7255 0xae025120
40 #define PHY_ID_BCM7260 0xae02 35 #define PHY_ID_BCM7260 0xae025190
41 #define PHY_ID_BCM7268 0xae02 36 #define PHY_ID_BCM7268 0xae025090
42 #define PHY_ID_BCM7271 0xae02 37 #define PHY_ID_BCM7271 0xae0253b0
43 #define PHY_ID_BCM7278 0xae02 38 #define PHY_ID_BCM7278 0xae0251a0
44 #define PHY_ID_BCM7364 0xae02 39 #define PHY_ID_BCM7364 0xae025260
45 #define PHY_ID_BCM7366 0x600d 40 #define PHY_ID_BCM7366 0x600d8490
46 #define PHY_ID_BCM7346 0x600d 41 #define PHY_ID_BCM7346 0x600d8650
47 #define PHY_ID_BCM7362 0x600d 42 #define PHY_ID_BCM7362 0x600d84b0
48 #define PHY_ID_BCM74165 0x3590 <<
49 #define PHY_ID_BCM7425 0x600d 43 #define PHY_ID_BCM7425 0x600d86b0
50 #define PHY_ID_BCM7429 0x600d 44 #define PHY_ID_BCM7429 0x600d8730
51 #define PHY_ID_BCM7435 0x600d 45 #define PHY_ID_BCM7435 0x600d8750
52 #define PHY_ID_BCM74371 0xae02 46 #define PHY_ID_BCM74371 0xae0252e0
53 #define PHY_ID_BCM7439 0x600d 47 #define PHY_ID_BCM7439 0x600d8480
54 #define PHY_ID_BCM7439_2 0xae02 48 #define PHY_ID_BCM7439_2 0xae025080
55 #define PHY_ID_BCM7445 0x600d 49 #define PHY_ID_BCM7445 0x600d8510
56 #define PHY_ID_BCM7712 0x3590 <<
57 50
58 #define PHY_ID_BCM_CYGNUS 0xae02 51 #define PHY_ID_BCM_CYGNUS 0xae025200
59 #define PHY_ID_BCM_OMEGA 0xae02 52 #define PHY_ID_BCM_OMEGA 0xae025100
60 53
61 #define PHY_BCM_OUI_MASK 0xffff 54 #define PHY_BCM_OUI_MASK 0xfffffc00
62 #define PHY_BCM_OUI_1 0x0020 55 #define PHY_BCM_OUI_1 0x00206000
63 #define PHY_BCM_OUI_2 0x0143 56 #define PHY_BCM_OUI_2 0x0143bc00
64 #define PHY_BCM_OUI_3 0x0362 57 #define PHY_BCM_OUI_3 0x03625c00
65 #define PHY_BCM_OUI_4 0x600d 58 #define PHY_BCM_OUI_4 0x600d8400
66 #define PHY_BCM_OUI_5 0x0362 59 #define PHY_BCM_OUI_5 0x03625e00
67 #define PHY_BCM_OUI_6 0xae02 60 #define PHY_BCM_OUI_6 0xae025000
68 61
69 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x0000 !! 62 #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
70 #define PHY_BRCM_RX_REFCLK_UNUSED 0x0000 !! 63 #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
71 #define PHY_BRCM_CLEAR_RGMII_MODE 0x0000 !! 64 #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
72 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x0000 !! 65 #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
73 #define PHY_BRCM_EN_MASTER_MODE 0x0000 !! 66 #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
74 #define PHY_BRCM_IDDQ_SUSPEND 0x0000 !! 67 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
>> 68 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
>> 69 #define PHY_BRCM_STD_IBND_DISABLE 0x00000800
>> 70 #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
>> 71 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
>> 72 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
>> 73 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
>> 74 #define PHY_BRCM_EN_MASTER_MODE 0x00010000
75 75
76 /* Broadcom BCM7xxx specific workarounds */ 76 /* Broadcom BCM7xxx specific workarounds */
77 #define PHY_BRCM_7XXX_REV(x) (((x) 77 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
78 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 78 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
79 #define PHY_BCM_FLAGS_VALID 0x8000 79 #define PHY_BCM_FLAGS_VALID 0x80000000
80 80
81 /* Broadcom BCM54XX register definitions, comm 81 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
82 #define MII_BCM54XX_ECR 0x10 /* BCM 82 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
83 #define MII_BCM54XX_ECR_IM 0x1000 /* Int 83 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
84 #define MII_BCM54XX_ECR_IF 0x0800 /* Int 84 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
85 #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIF 85 #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */
86 86
87 #define MII_BCM54XX_ESR 0x11 /* BCM 87 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
88 #define MII_BCM54XX_ESR_IS 0x1000 /* Int 88 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
89 89
90 #define MII_BCM54XX_EXP_DATA 0x15 /* Exp 90 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
91 #define MII_BCM54XX_EXP_SEL 0x17 /* Exp 91 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
92 #define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP <<
93 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Sec 92 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
94 #define MII_BCM54XX_EXP_SEL_WOL 0x0e00 /* Wak <<
95 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Exp 93 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
96 #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Exp 94 #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */
97 95
98 #define MII_BCM54XX_AUX_CTL 0x18 /* Aux 96 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
99 #define MII_BCM54XX_ISR 0x1a /* BCM 97 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
100 #define MII_BCM54XX_IMR 0x1b /* BCM 98 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
101 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC 99 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
102 #define MII_BCM54XX_INT_LINK 0x0002 /* Lin 100 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
103 #define MII_BCM54XX_INT_SPEED 0x0004 /* Lin 101 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
104 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Dup 102 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
105 #define MII_BCM54XX_INT_LRS 0x0010 /* Loc 103 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
106 #define MII_BCM54XX_INT_RRS 0x0020 /* Rem 104 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
107 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scr 105 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
108 #define MII_BCM54XX_INT_UHCD 0x0080 /* Uns 106 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
109 #define MII_BCM54XX_INT_NHCD 0x0100 /* No 107 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
110 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No 108 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
111 #define MII_BCM54XX_INT_ANPR 0x0400 /* Aut 109 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
112 #define MII_BCM54XX_INT_LC 0x0800 /* All 110 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
113 #define MII_BCM54XX_INT_HC 0x1000 /* Cou 111 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
114 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDI 112 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
115 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pai 113 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
116 114
117 #define MII_BCM54XX_SHD 0x1c /* 0x1 115 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
118 #define MII_BCM54XX_SHD_WRITE 0x8000 116 #define MII_BCM54XX_SHD_WRITE 0x8000
119 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 117 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
120 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) < 118 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
121 119
122 #define MII_BCM54XX_RDB_ADDR 0x1e 120 #define MII_BCM54XX_RDB_ADDR 0x1e
123 #define MII_BCM54XX_RDB_DATA 0x1f 121 #define MII_BCM54XX_RDB_DATA 0x1f
124 122
125 /* legacy access control via rdb/expansion reg 123 /* legacy access control via rdb/expansion register */
126 #define BCM54XX_RDB_REG0087 0x0087 124 #define BCM54XX_RDB_REG0087 0x0087
127 #define BCM54XX_EXP_REG7E (MII_B 125 #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E)
128 #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15 126 #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15)
129 127
130 /* 128 /*
131 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. 129 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
132 */ 130 */
133 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 131 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
134 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 132 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
135 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 133 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
136 #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 134 #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000
137 135
138 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 136 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
139 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESP 137 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
140 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_ <<
141 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_ 138 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
142 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 139 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
143 #define MII_BCM54XX_AUXCTL_MISC_WREN 140 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
144 141
145 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 142 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
146 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 143 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
147 144
148 /* 145 /*
149 * Broadcom LED source encodings. These are u 146 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
150 * BCM5482, and possibly some others. 147 * BCM5482, and possibly some others.
151 */ 148 */
152 #define BCM_LED_SRC_LINKSPD1 0x0 149 #define BCM_LED_SRC_LINKSPD1 0x0
153 #define BCM_LED_SRC_LINKSPD2 0x1 150 #define BCM_LED_SRC_LINKSPD2 0x1
154 #define BCM_LED_SRC_XMITLED 0x2 151 #define BCM_LED_SRC_XMITLED 0x2
155 #define BCM_LED_SRC_ACTIVITYLED 0x3 152 #define BCM_LED_SRC_ACTIVITYLED 0x3
156 #define BCM_LED_SRC_FDXLED 0x4 153 #define BCM_LED_SRC_FDXLED 0x4
157 #define BCM_LED_SRC_SLAVE 0x5 154 #define BCM_LED_SRC_SLAVE 0x5
158 #define BCM_LED_SRC_INTR 0x6 155 #define BCM_LED_SRC_INTR 0x6
159 #define BCM_LED_SRC_QUALITY 0x7 156 #define BCM_LED_SRC_QUALITY 0x7
160 #define BCM_LED_SRC_RCVLED 0x8 157 #define BCM_LED_SRC_RCVLED 0x8
161 #define BCM_LED_SRC_WIRESPEED 0x9 158 #define BCM_LED_SRC_WIRESPEED 0x9
162 #define BCM_LED_SRC_MULTICOLOR1 0xa 159 #define BCM_LED_SRC_MULTICOLOR1 0xa
163 #define BCM_LED_SRC_OPENSHORT 0xb 160 #define BCM_LED_SRC_OPENSHORT 0xb
164 #define BCM_LED_SRC_OFF 0xe /* Tie 161 #define BCM_LED_SRC_OFF 0xe /* Tied high */
165 #define BCM_LED_SRC_ON 0xf /* Tie 162 #define BCM_LED_SRC_ON 0xf /* Tied low */
166 #define BCM_LED_SRC_MASK GENMASK(3, 0) <<
167 163
168 /* 164 /*
169 * Broadcom Multicolor LED configurations (exp 165 * Broadcom Multicolor LED configurations (expansion register 4)
170 */ 166 */
171 #define BCM_EXP_MULTICOLOR (MII_B 167 #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)
172 #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 168 #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)
173 #define BCM_LED_MULTICOLOR_LINK_ACT 0x0 169 #define BCM_LED_MULTICOLOR_LINK_ACT 0x0
174 #define BCM_LED_MULTICOLOR_SPEED 0x1 170 #define BCM_LED_MULTICOLOR_SPEED 0x1
175 #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 171 #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2
176 #define BCM_LED_MULTICOLOR_FDX 0x3 172 #define BCM_LED_MULTICOLOR_FDX 0x3
177 #define BCM_LED_MULTICOLOR_OFF 0x4 173 #define BCM_LED_MULTICOLOR_OFF 0x4
178 #define BCM_LED_MULTICOLOR_ON 0x5 174 #define BCM_LED_MULTICOLOR_ON 0x5
179 #define BCM_LED_MULTICOLOR_ALT 0x6 175 #define BCM_LED_MULTICOLOR_ALT 0x6
180 #define BCM_LED_MULTICOLOR_FLASH 0x7 176 #define BCM_LED_MULTICOLOR_FLASH 0x7
181 #define BCM_LED_MULTICOLOR_LINK 0x8 177 #define BCM_LED_MULTICOLOR_LINK 0x8
182 #define BCM_LED_MULTICOLOR_ACT 0x9 178 #define BCM_LED_MULTICOLOR_ACT 0x9
183 #define BCM_LED_MULTICOLOR_PROGRAM 0xa 179 #define BCM_LED_MULTICOLOR_PROGRAM 0xa
184 180
185 /* 181 /*
186 * BCM5482: Shadow registers 182 * BCM5482: Shadow registers
187 * Shadow values go into bits [14:10] of regis 183 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
188 * register to access. 184 * register to access.
189 */ 185 */
190 186
191 /* 00100: Reserved control register 2 */ 187 /* 00100: Reserved control register 2 */
192 #define BCM54XX_SHD_SCR2 0x04 188 #define BCM54XX_SHD_SCR2 0x04
193 #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 189 #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
194 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 190 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
195 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 191 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
196 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 192 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
197 193
198 /* 00101: Spare Control Register 3 */ 194 /* 00101: Spare Control Register 3 */
199 #define BCM54XX_SHD_SCR3 0x05 195 #define BCM54XX_SHD_SCR3 0x05
200 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 196 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
201 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 197 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
202 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 198 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
203 #define BCM54XX_SHD_SCR3_RXCTXC_DIS 0x0100 <<
204 199
205 /* 01010: Auto Power-Down */ 200 /* 01010: Auto Power-Down */
206 #define BCM54XX_SHD_APD 0x0a 201 #define BCM54XX_SHD_APD 0x0a
207 #define BCM_APD_CLR_MASK 0xFE9F 202 #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
208 #define BCM54XX_SHD_APD_EN 0x0020 203 #define BCM54XX_SHD_APD_EN 0x0020
209 #define BCM_NO_ANEG_APD_EN 0x0060 204 #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
210 #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 205 #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
211 206
212 #define BCM54XX_SHD_LEDS1 0x0d /* 011 !! 207 #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
213 /* LED 208 /* LED3 / ~LINKSPD[2] selector */
214 #define BCM54XX_SHD_LEDS_SHIFT(led) (4 * ( !! 209 #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
215 #define BCM54XX_SHD_LEDS1_LED3(src) ((src <<
216 /* LED 210 /* LED1 / ~LINKSPD[1] selector */
217 #define BCM54XX_SHD_LEDS1_LED1(src) ((src !! 211 #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
218 #define BCM54XX_SHD_LEDS2 0x0e /* 011 <<
219 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 010 212 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
220 #define BCM5482_SHD_SSD 0x14 /* 101 213 #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
221 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD 214 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
222 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD 215 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
223 216
224 /* 10011: SerDes 100-FX Control Register */ 217 /* 10011: SerDes 100-FX Control Register */
225 #define BCM54616S_SHD_100FX_CTRL 0x13 218 #define BCM54616S_SHD_100FX_CTRL 0x13
226 #define BCM54616S_100FX_MODE BIT(0) 219 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
227 220
228 /* 11111: Mode Control Register */ 221 /* 11111: Mode Control Register */
229 #define BCM54XX_SHD_MODE 0x1f 222 #define BCM54XX_SHD_MODE 0x1f
230 #define BCM54XX_SHD_INTF_SEL_MASK GENMAS 223 #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
231 #define BCM54XX_SHD_INTF_SEL_RGMII 0x02 <<
232 #define BCM54XX_SHD_INTF_SEL_SGMII 0x04 <<
233 #define BCM54XX_SHD_INTF_SEL_GBIC 0x06 <<
234 #define BCM54XX_SHD_MODE_1000BX BIT(0) 224 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
235 225
236 /* 226 /*
237 * EXPANSION SHADOW ACCESS REGISTERS. (PHY RE 227 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
238 */ 228 */
239 #define MII_BCM54XX_EXP_AADJ1CH0 229 #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
240 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 230 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
241 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 231 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
242 #define MII_BCM54XX_EXP_AADJ1CH3 232 #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
243 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 233 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
244 #define MII_BCM54XX_EXP_EXP08 234 #define MII_BCM54XX_EXP_EXP08 0x0F08
245 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 235 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
246 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 236 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
247 #define MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE <<
248 #define MII_BCM54XX_EXP_EXP75 237 #define MII_BCM54XX_EXP_EXP75 0x0f75
249 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 238 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
250 #define MII_BCM54XX_EXP_EXP75_CM_OSC 239 #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
251 #define MII_BCM54XX_EXP_EXP96 240 #define MII_BCM54XX_EXP_EXP96 0x0f96
252 #define MII_BCM54XX_EXP_EXP96_MYST 241 #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
253 #define MII_BCM54XX_EXP_EXP97 242 #define MII_BCM54XX_EXP_EXP97 0x0f97
254 #define MII_BCM54XX_EXP_EXP97_MYST 243 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
255 244
256 /* Top-MISC expansion registers */ <<
257 #define BCM54XX_TOP_MISC_IDDQ_CTRL <<
258 #define BCM54XX_TOP_MISC_IDDQ_LP <<
259 #define BCM54XX_TOP_MISC_IDDQ_SD <<
260 #define BCM54XX_TOP_MISC_IDDQ_SR <<
261 <<
262 #define BCM54XX_TOP_MISC_LED_CTL <<
263 #define BCM54XX_LED4_SEL_INTR <<
264 <<
265 /* 245 /*
266 * BCM5482: Secondary SerDes registers 246 * BCM5482: Secondary SerDes registers
267 */ 247 */
268 #define BCM5482_SSD_1000BX_CTL 0x00 248 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
269 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 249 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
270 #define BCM5482_SSD_SGMII_SLAVE 0x15 250 #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
271 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 251 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
272 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 252 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
273 253
274 /* BroadR-Reach LRE Registers. */ <<
275 #define MII_BCM54XX_LRECR 0x00 <<
276 #define MII_BCM54XX_LRESR 0x01 <<
277 #define MII_BCM54XX_LREPHYSID1 0x02 <<
278 #define MII_BCM54XX_LREPHYSID2 0x03 <<
279 #define MII_BCM54XX_LREANAA 0x04 <<
280 #define MII_BCM54XX_LREANAC 0x05 <<
281 #define MII_BCM54XX_LREANPT 0x06 <<
282 #define MII_BCM54XX_LRELPA 0x07 <<
283 #define MII_BCM54XX_LRELPNPM 0x08 <<
284 #define MII_BCM54XX_LRELPNPC 0x09 <<
285 #define MII_BCM54XX_LRELDSE 0x0a <<
286 #define MII_BCM54XX_LREES 0x0f <<
287 <<
288 /* LRE control register. */ <<
289 #define LRECR_RESET 0x8000 <<
290 #define LRECR_LOOPBACK 0x4000 <<
291 #define LRECR_LDSRES 0x2000 <<
292 #define LRECR_LDSEN 0x1000 <<
293 #define LRECR_PDOWN 0x0800 <<
294 #define LRECR_ISOLATE 0x0400 <<
295 #define LRECR_SPEED100 0x0200 <<
296 #define LRECR_SPEED10 0x0000 <<
297 #define LRECR_4PAIRS 0x0020 <<
298 #define LRECR_2PAIRS 0x0010 <<
299 #define LRECR_1PAIR 0x0000 <<
300 #define LRECR_MASTER 0x0008 <<
301 #define LRECR_SLAVE 0x0000 <<
302 <<
303 /* LRE status register. */ <<
304 #define LRESR_100_1PAIR 0x2000 <<
305 #define LRESR_100_4PAIR 0x1000 <<
306 #define LRESR_100_2PAIR 0x0800 <<
307 #define LRESR_10_2PAIR 0x0400 <<
308 #define LRESR_10_1PAIR 0x0200 <<
309 #define LRESR_ESTATEN 0x0100 <<
310 #define LRESR_RESV 0x0080 <<
311 #define LRESR_MFPS 0x0040 <<
312 #define LRESR_LDSCOMPLETE 0x0020 <<
313 #define LRESR_8023 0x0010 <<
314 #define LRESR_LDSABILITY 0x0008 <<
315 #define LRESR_LSTATUS 0x0004 <<
316 #define LRESR_JCD 0x0002 <<
317 #define LRESR_ERCAP 0x0001 <<
318 <<
319 /* LDS Auto-Negotiation Advertised Ability. */ <<
320 #define LREANAA_PAUSE_ASYM 0x8000 <<
321 #define LREANAA_PAUSE 0x4000 <<
322 #define LREANAA_100_1PAIR 0x0020 <<
323 #define LREANAA_100_4PAIR 0x0010 <<
324 #define LREANAA_100_2PAIR 0x0008 <<
325 #define LREANAA_10_2PAIR 0x0004 <<
326 #define LREANAA_10_1PAIR 0x0002 <<
327 <<
328 #define LRE_ADVERTISE_FULL (LREAN <<
329 LREAN <<
330 LREAN <<
331 <<
332 #define LRE_ADVERTISE_ALL LRE_AD <<
333 <<
334 /* LDS Link Partner Ability. */ <<
335 #define LRELPA_PAUSE_ASYM 0x8000 <<
336 #define LRELPA_PAUSE 0x4000 <<
337 #define LRELPA_100_1PAIR 0x0020 <<
338 #define LRELPA_100_4PAIR 0x0010 <<
339 #define LRELPA_100_2PAIR 0x0008 <<
340 #define LRELPA_10_2PAIR 0x0004 <<
341 #define LRELPA_10_1PAIR 0x0002 <<
342 <<
343 /* LDS Expansion register. */ <<
344 #define LDSE_DOWNGRADE 0x8000 <<
345 #define LDSE_MASTER 0x4000 <<
346 #define LDSE_PAIRS_MASK 0x3000 <<
347 #define LDSE_PAIRS_SHIFT 12 <<
348 #define LDSE_4PAIRS (2 << <<
349 #define LDSE_2PAIRS (1 << <<
350 #define LDSE_1PAIR (0 << <<
351 #define LDSE_CABLEN_MASK 0x0FFF <<
352 <<
353 /* BCM54810 Registers */ 254 /* BCM54810 Registers */
354 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL 255 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
355 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_E 256 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
356 #define BCM54810_SHD_CLK_CTL 257 #define BCM54810_SHD_CLK_CTL 0x3
357 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN 258 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
358 !! 259 #define BCM54810_SHD_SCR3_TRDDAPD 0x0100
359 /* BCM54811 Registers */ <<
360 #define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CT <<
361 /* Access Control Override Enable */ <<
362 #define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CT <<
363 /* Access Control Override Value */ <<
364 #define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CT <<
365 /* Access Control Value */ <<
366 #define BCM54811_EXP_BROADREACH_LRE_OVERLAY_CT <<
367 260
368 /* BCM54612E Registers */ 261 /* BCM54612E Registers */
369 #define BCM54612E_EXP_SPARE0 (MII_B 262 #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)
370 #define BCM54612E_LED4_CLK125OUT_EN (1 << 263 #define BCM54612E_LED4_CLK125OUT_EN (1 << 1)
371 264
372 <<
373 /* Wake-on-LAN registers */ <<
374 #define BCM54XX_WOL_MAIN_CTL (MII_B <<
375 #define BCM54XX_WOL_EN BIT(0) <<
376 #define BCM54XX_WOL_MODE_SINGLE_MPD 0 <<
377 #define BCM54XX_WOL_MODE_SINGLE_MPDSEC 1 <<
378 #define BCM54XX_WOL_MODE_DUAL 2 <<
379 #define BCM54XX_WOL_MODE_SHIFT 1 <<
380 #define BCM54XX_WOL_MODE_MASK 0x3 <<
381 #define BCM54XX_WOL_MP_MSB_FF_EN BIT(3) <<
382 #define BCM54XX_WOL_SECKEY_OPT_4B 0 <<
383 #define BCM54XX_WOL_SECKEY_OPT_6B 1 <<
384 #define BCM54XX_WOL_SECKEY_OPT_8B 2 <<
385 #define BCM54XX_WOL_SECKEY_OPT_SHIFT 4 <<
386 #define BCM54XX_WOL_SECKEY_OPT_MASK 0x3 <<
387 #define BCM54XX_WOL_L2_TYPE_CHK BIT(6) <<
388 #define BCM54XX_WOL_L4IPV4UDP_CHK BIT(7) <<
389 #define BCM54XX_WOL_L4IPV6UDP_CHK BIT(8) <<
390 #define BCM54XX_WOL_UDPPORT_CHK BIT(9) <<
391 #define BCM54XX_WOL_CRC_CHK BIT(10 <<
392 #define BCM54XX_WOL_SECKEY_MODE BIT(11 <<
393 #define BCM54XX_WOL_RST BIT(12 <<
394 #define BCM54XX_WOL_DIR_PKT_EN BIT(13 <<
395 #define BCM54XX_WOL_MASK_MODE_DA_FF 0 <<
396 #define BCM54XX_WOL_MASK_MODE_DA_MPD 1 <<
397 #define BCM54XX_WOL_MASK_MODE_DA_ONLY 2 <<
398 #define BCM54XX_WOL_MASK_MODE_MPD 3 <<
399 #define BCM54XX_WOL_MASK_MODE_SHIFT 14 <<
400 #define BCM54XX_WOL_MASK_MODE_MASK 0x3 <<
401 <<
402 #define BCM54XX_WOL_INNER_PROTO (MII_B <<
403 #define BCM54XX_WOL_OUTER_PROTO (MII_B <<
404 #define BCM54XX_WOL_OUTER_PROTO2 (MII_B <<
405 <<
406 #define BCM54XX_WOL_MPD_DATA1(x) (MII_B <<
407 #define BCM54XX_WOL_MPD_DATA2(x) (MII_B <<
408 #define BCM54XX_WOL_SEC_KEY_8B (MII_B <<
409 #define BCM54XX_WOL_MASK(x) (MII_B <<
410 #define BCM54XX_SEC_KEY_STORE(x) (MII_B <<
411 #define BCM54XX_WOL_SHARED_CNT (MII_B <<
412 <<
413 #define BCM54XX_WOL_INT_MASK (MII_B <<
414 #define BCM54XX_WOL_PKT1 BIT(0) <<
415 #define BCM54XX_WOL_PKT2 BIT(1) <<
416 #define BCM54XX_WOL_DIR BIT(2) <<
417 #define BCM54XX_WOL_ALL_INTRS (BCM54 <<
418 BCM54 <<
419 BCM54 <<
420 <<
421 #define BCM54XX_WOL_INT_STATUS (MII_B <<
422 <<
423 /* BCM5221 Registers */ <<
424 #define BCM5221_AEGSR 0x1C <<
425 #define BCM5221_AEGSR_MDIX_STATUS BIT(13 <<
426 #define BCM5221_AEGSR_MDIX_MAN_SWAP BIT(12 <<
427 #define BCM5221_AEGSR_MDIX_DIS BIT(11 <<
428 <<
429 #define BCM5221_SHDW_AM4_EN_CLK_LPM BIT(2) <<
430 #define BCM5221_SHDW_AM4_FORCE_LPM BIT(1) <<
431 <<
432 /********************************************* 265 /*****************************************************************************/
433 /* Fast Ethernet Transceiver definitions. */ 266 /* Fast Ethernet Transceiver definitions. */
434 /********************************************* 267 /*****************************************************************************/
435 268
436 #define MII_BRCM_FET_INTREG 0x1a 269 #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
437 #define MII_BRCM_FET_IR_MASK 0x0100 270 #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
438 #define MII_BRCM_FET_IR_LINK_EN 0x0200 271 #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
439 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 272 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
440 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 273 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
441 #define MII_BRCM_FET_IR_ENABLE 0x4000 274 #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
442 275
443 #define MII_BRCM_FET_BRCMTEST 0x1f 276 #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
444 #define MII_BRCM_FET_BT_SRE 0x0080 277 #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
445 278
446 279
447 /*** Shadow register definitions ***/ 280 /*** Shadow register definitions ***/
448 281
449 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 282 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
450 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 283 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
451 284
452 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a 285 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
453 #define MII_BRCM_FET_SHDW_AM4_STANDBY 0x0008 <<
454 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 286 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
455 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 287 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
456 288
457 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b 289 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
458 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 290 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
459 291
460 #define BRCM_CL45VEN_EEE_CONTROL 0x803d 292 #define BRCM_CL45VEN_EEE_CONTROL 0x803d
461 #define LPI_FEATURE_EN 0x8000 293 #define LPI_FEATURE_EN 0x8000
462 #define LPI_FEATURE_EN_DIG1000X 0x4000 294 #define LPI_FEATURE_EN_DIG1000X 0x4000
463 <<
464 #define BRCM_CL45VEN_EEE_LPI_CNT 0x803f <<
465 295
466 /* Core register definitions*/ 296 /* Core register definitions*/
467 #define MII_BRCM_CORE_BASE12 0x12 297 #define MII_BRCM_CORE_BASE12 0x12
468 #define MII_BRCM_CORE_BASE13 0x13 298 #define MII_BRCM_CORE_BASE13 0x13
469 #define MII_BRCM_CORE_BASE14 0x14 299 #define MII_BRCM_CORE_BASE14 0x14
470 #define MII_BRCM_CORE_BASE1E 0x1E 300 #define MII_BRCM_CORE_BASE1E 0x1E
471 #define MII_BRCM_CORE_EXPB0 0xB0 301 #define MII_BRCM_CORE_EXPB0 0xB0
472 #define MII_BRCM_CORE_EXPB1 0xB1 302 #define MII_BRCM_CORE_EXPB1 0xB1
473 303
474 /* Enhanced Cable Diagnostics */ 304 /* Enhanced Cable Diagnostics */
475 #define BCM54XX_RDB_ECD_CTRL 305 #define BCM54XX_RDB_ECD_CTRL 0x2a0
476 #define BCM54XX_EXP_ECD_CTRL 306 #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0)
477 307
478 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 308 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */
479 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 309 #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */
480 #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK 310 #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */
481 #define BCM54XX_ECD_CTRL_INVALID 311 #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */
482 #define BCM54XX_ECD_CTRL_UNIT_CM 312 #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */
483 #define BCM54XX_ECD_CTRL_UNIT_M 313 #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */
484 #define BCM54XX_ECD_CTRL_UNIT_MASK 314 #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */
485 #define BCM54XX_ECD_CTRL_IN_PROGRESS 315 #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */
486 #define BCM54XX_ECD_CTRL_BREAK_LINK 316 #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link
487 317 * during test
488 318 */
489 #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS 319 #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair
490 320 * short check
491 321 */
492 #define BCM54XX_ECD_CTRL_RUN 322 #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */
493 323
494 #define BCM54XX_RDB_ECD_FAULT_TYPE 324 #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1
495 #define BCM54XX_EXP_ECD_FAULT_TYPE 325 #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1)
496 #define BCM54XX_ECD_FAULT_TYPE_INVALID 326 #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0
497 #define BCM54XX_ECD_FAULT_TYPE_OK 327 #define BCM54XX_ECD_FAULT_TYPE_OK 0x1
498 #define BCM54XX_ECD_FAULT_TYPE_OPEN 328 #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2
499 #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 329 #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */
500 #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 330 #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */
501 #define BCM54XX_ECD_FAULT_TYPE_BUSY 331 #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9
502 #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK 332 #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0)
503 #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK 333 #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4)
504 #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK 334 #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8)
505 #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK 335 #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12)
506 #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 336 #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
507 #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 337 #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
508 #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 338 #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
509 #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 339 #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
510 340
511 #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 341 #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2
512 #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS 342 #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2)
513 #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 343 #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3
514 #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS 344 #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3)
515 #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 345 #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4
516 #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS 346 #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4)
517 #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 347 #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5
518 #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS 348 #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5)
519 #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 349 #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff
520 350
521 #endif /* _LINUX_BRCMPHY_H */ 351 #endif /* _LINUX_BRCMPHY_H */
522 352
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