1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_DMA_MAPPING_H 2 #ifndef _LINUX_DMA_MAPPING_H
3 #define _LINUX_DMA_MAPPING_H 3 #define _LINUX_DMA_MAPPING_H
4 4
5 #include <linux/cache.h> <<
6 #include <linux/sizes.h> 5 #include <linux/sizes.h>
7 #include <linux/string.h> 6 #include <linux/string.h>
8 #include <linux/device.h> 7 #include <linux/device.h>
9 #include <linux/err.h> 8 #include <linux/err.h>
10 #include <linux/dma-direction.h> 9 #include <linux/dma-direction.h>
11 #include <linux/scatterlist.h> 10 #include <linux/scatterlist.h>
12 #include <linux/bug.h> 11 #include <linux/bug.h>
13 #include <linux/mem_encrypt.h> 12 #include <linux/mem_encrypt.h>
14 13
15 /** 14 /**
16 * List of possible attributes associated with 15 * List of possible attributes associated with a DMA mapping. The semantics
17 * of each attribute should be defined in Docu 16 * of each attribute should be defined in Documentation/core-api/dma-attributes.rst.
18 */ 17 */
19 18
20 /* 19 /*
21 * DMA_ATTR_WEAK_ORDERING: Specifies that read 20 * DMA_ATTR_WEAK_ORDERING: Specifies that reads and writes to the mapping
22 * may be weakly ordered, that is that reads a 21 * may be weakly ordered, that is that reads and writes may pass each other.
23 */ 22 */
24 #define DMA_ATTR_WEAK_ORDERING (1UL < 23 #define DMA_ATTR_WEAK_ORDERING (1UL << 1)
25 /* 24 /*
26 * DMA_ATTR_WRITE_COMBINE: Specifies that writ 25 * DMA_ATTR_WRITE_COMBINE: Specifies that writes to the mapping may be
27 * buffered to improve performance. 26 * buffered to improve performance.
28 */ 27 */
29 #define DMA_ATTR_WRITE_COMBINE (1UL < 28 #define DMA_ATTR_WRITE_COMBINE (1UL << 2)
30 /* 29 /*
31 * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platfo 30 * DMA_ATTR_NO_KERNEL_MAPPING: Lets the platform to avoid creating a kernel
32 * virtual mapping for the allocated buffer. 31 * virtual mapping for the allocated buffer.
33 */ 32 */
34 #define DMA_ATTR_NO_KERNEL_MAPPING (1UL < 33 #define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 4)
35 /* 34 /*
36 * DMA_ATTR_SKIP_CPU_SYNC: Allows platform cod 35 * DMA_ATTR_SKIP_CPU_SYNC: Allows platform code to skip synchronization of
37 * the CPU cache for the given buffer assuming 36 * the CPU cache for the given buffer assuming that it has been already
38 * transferred to 'device' domain. 37 * transferred to 'device' domain.
39 */ 38 */
40 #define DMA_ATTR_SKIP_CPU_SYNC (1UL < 39 #define DMA_ATTR_SKIP_CPU_SYNC (1UL << 5)
41 /* 40 /*
42 * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguou 41 * DMA_ATTR_FORCE_CONTIGUOUS: Forces contiguous allocation of the buffer
43 * in physical memory. 42 * in physical memory.
44 */ 43 */
45 #define DMA_ATTR_FORCE_CONTIGUOUS (1UL < 44 #define DMA_ATTR_FORCE_CONTIGUOUS (1UL << 6)
46 /* 45 /*
47 * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint 46 * DMA_ATTR_ALLOC_SINGLE_PAGES: This is a hint to the DMA-mapping subsystem
48 * that it's probably not worth the time to tr 47 * that it's probably not worth the time to try to allocate memory to in a way
49 * that gives better TLB efficiency. 48 * that gives better TLB efficiency.
50 */ 49 */
51 #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL < 50 #define DMA_ATTR_ALLOC_SINGLE_PAGES (1UL << 7)
52 /* 51 /*
53 * DMA_ATTR_NO_WARN: This tells the DMA-mappin 52 * DMA_ATTR_NO_WARN: This tells the DMA-mapping subsystem to suppress
54 * allocation failure reports (similarly to __ 53 * allocation failure reports (similarly to __GFP_NOWARN).
55 */ 54 */
56 #define DMA_ATTR_NO_WARN (1UL << 8) 55 #define DMA_ATTR_NO_WARN (1UL << 8)
57 56
58 /* 57 /*
59 * DMA_ATTR_PRIVILEGED: used to indicate that 58 * DMA_ATTR_PRIVILEGED: used to indicate that the buffer is fully
60 * accessible at an elevated privilege level ( 59 * accessible at an elevated privilege level (and ideally inaccessible or
61 * at least read-only at lesser-privileged lev 60 * at least read-only at lesser-privileged levels).
62 */ 61 */
63 #define DMA_ATTR_PRIVILEGED (1UL < 62 #define DMA_ATTR_PRIVILEGED (1UL << 9)
64 63
65 /* 64 /*
66 * A dma_addr_t can hold any valid DMA or bus 65 * A dma_addr_t can hold any valid DMA or bus address for the platform. It can
67 * be given to a device to use as a DMA source 66 * be given to a device to use as a DMA source or target. It is specific to a
68 * given device and there may be a translation 67 * given device and there may be a translation between the CPU physical address
69 * space and the bus address space. 68 * space and the bus address space.
70 * 69 *
71 * DMA_MAPPING_ERROR is the magic error code i 70 * DMA_MAPPING_ERROR is the magic error code if a mapping failed. It should not
72 * be used directly in drivers, but checked fo 71 * be used directly in drivers, but checked for using dma_mapping_error()
73 * instead. 72 * instead.
74 */ 73 */
75 #define DMA_MAPPING_ERROR (~(dma 74 #define DMA_MAPPING_ERROR (~(dma_addr_t)0)
76 75
77 #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : 76 #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
78 77
79 #ifdef CONFIG_DMA_API_DEBUG 78 #ifdef CONFIG_DMA_API_DEBUG
80 void debug_dma_mapping_error(struct device *de 79 void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
81 void debug_dma_map_single(struct device *dev, 80 void debug_dma_map_single(struct device *dev, const void *addr,
82 unsigned long len); 81 unsigned long len);
83 #else 82 #else
84 static inline void debug_dma_mapping_error(str 83 static inline void debug_dma_mapping_error(struct device *dev,
85 dma_addr_t dma_addr) 84 dma_addr_t dma_addr)
86 { 85 {
87 } 86 }
88 static inline void debug_dma_map_single(struct 87 static inline void debug_dma_map_single(struct device *dev, const void *addr,
89 unsigned long len) 88 unsigned long len)
90 { 89 {
91 } 90 }
92 #endif /* CONFIG_DMA_API_DEBUG */ 91 #endif /* CONFIG_DMA_API_DEBUG */
93 92
94 #ifdef CONFIG_HAS_DMA 93 #ifdef CONFIG_HAS_DMA
95 static inline int dma_mapping_error(struct dev 94 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
96 { 95 {
97 debug_dma_mapping_error(dev, dma_addr) 96 debug_dma_mapping_error(dev, dma_addr);
98 97
99 if (unlikely(dma_addr == DMA_MAPPING_E !! 98 if (dma_addr == DMA_MAPPING_ERROR)
100 return -ENOMEM; 99 return -ENOMEM;
101 return 0; 100 return 0;
102 } 101 }
103 102
104 dma_addr_t dma_map_page_attrs(struct device *d 103 dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
105 size_t offset, size_t size, en 104 size_t offset, size_t size, enum dma_data_direction dir,
106 unsigned long attrs); 105 unsigned long attrs);
107 void dma_unmap_page_attrs(struct device *dev, 106 void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
108 enum dma_data_direction dir, u 107 enum dma_data_direction dir, unsigned long attrs);
109 unsigned int dma_map_sg_attrs(struct device *d !! 108 int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents,
110 int nents, enum dma_data_direc !! 109 enum dma_data_direction dir, unsigned long attrs);
111 void dma_unmap_sg_attrs(struct device *dev, st 110 void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
112 int nent 111 int nents, enum dma_data_direction dir,
113 unsigned 112 unsigned long attrs);
114 int dma_map_sgtable(struct device *dev, struct <<
115 enum dma_data_direction dir, u <<
116 dma_addr_t dma_map_resource(struct device *dev 113 dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
117 size_t size, enum dma_data_dir 114 size_t size, enum dma_data_direction dir, unsigned long attrs);
118 void dma_unmap_resource(struct device *dev, dm 115 void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size,
119 enum dma_data_direction dir, u 116 enum dma_data_direction dir, unsigned long attrs);
>> 117 void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr, size_t size,
>> 118 enum dma_data_direction dir);
>> 119 void dma_sync_single_for_device(struct device *dev, dma_addr_t addr,
>> 120 size_t size, enum dma_data_direction dir);
>> 121 void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
>> 122 int nelems, enum dma_data_direction dir);
>> 123 void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
>> 124 int nelems, enum dma_data_direction dir);
120 void *dma_alloc_attrs(struct device *dev, size 125 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
121 gfp_t flag, unsigned long attr 126 gfp_t flag, unsigned long attrs);
122 void dma_free_attrs(struct device *dev, size_t 127 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
123 dma_addr_t dma_handle, unsigne 128 dma_addr_t dma_handle, unsigned long attrs);
124 void *dmam_alloc_attrs(struct device *dev, siz 129 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
125 gfp_t gfp, unsigned long attrs 130 gfp_t gfp, unsigned long attrs);
126 void dmam_free_coherent(struct device *dev, si 131 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr,
127 dma_addr_t dma_handle); 132 dma_addr_t dma_handle);
128 int dma_get_sgtable_attrs(struct device *dev, 133 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
129 void *cpu_addr, dma_addr_t dma 134 void *cpu_addr, dma_addr_t dma_addr, size_t size,
130 unsigned long attrs); 135 unsigned long attrs);
131 int dma_mmap_attrs(struct device *dev, struct 136 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
132 void *cpu_addr, dma_addr_t dma 137 void *cpu_addr, dma_addr_t dma_addr, size_t size,
133 unsigned long attrs); 138 unsigned long attrs);
134 bool dma_can_mmap(struct device *dev); 139 bool dma_can_mmap(struct device *dev);
135 bool dma_pci_p2pdma_supported(struct device *d !! 140 int dma_supported(struct device *dev, u64 mask);
136 int dma_set_mask(struct device *dev, u64 mask) 141 int dma_set_mask(struct device *dev, u64 mask);
137 int dma_set_coherent_mask(struct device *dev, 142 int dma_set_coherent_mask(struct device *dev, u64 mask);
138 u64 dma_get_required_mask(struct device *dev); 143 u64 dma_get_required_mask(struct device *dev);
139 bool dma_addressing_limited(struct device *dev <<
140 size_t dma_max_mapping_size(struct device *dev 144 size_t dma_max_mapping_size(struct device *dev);
141 size_t dma_opt_mapping_size(struct device *dev !! 145 bool dma_need_sync(struct device *dev, dma_addr_t dma_addr);
142 unsigned long dma_get_merge_boundary(struct de 146 unsigned long dma_get_merge_boundary(struct device *dev);
143 struct sg_table *dma_alloc_noncontiguous(struc <<
144 enum dma_data_direction dir, g <<
145 void dma_free_noncontiguous(struct device *dev <<
146 struct sg_table *sgt, enum dma <<
147 void *dma_vmap_noncontiguous(struct device *de <<
148 struct sg_table *sgt); <<
149 void dma_vunmap_noncontiguous(struct device *d <<
150 int dma_mmap_noncontiguous(struct device *dev, <<
151 size_t size, struct sg_table * <<
152 #else /* CONFIG_HAS_DMA */ 147 #else /* CONFIG_HAS_DMA */
153 static inline dma_addr_t dma_map_page_attrs(st 148 static inline dma_addr_t dma_map_page_attrs(struct device *dev,
154 struct page *page, size_t offs 149 struct page *page, size_t offset, size_t size,
155 enum dma_data_direction dir, u 150 enum dma_data_direction dir, unsigned long attrs)
156 { 151 {
157 return DMA_MAPPING_ERROR; 152 return DMA_MAPPING_ERROR;
158 } 153 }
159 static inline void dma_unmap_page_attrs(struct 154 static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
160 size_t size, enum dma_data_dir 155 size_t size, enum dma_data_direction dir, unsigned long attrs)
161 { 156 {
162 } 157 }
163 static inline unsigned int dma_map_sg_attrs(st !! 158 static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
164 struct scatterlist *sg, int ne !! 159 int nents, enum dma_data_direction dir, unsigned long attrs)
165 unsigned long attrs) <<
166 { 160 {
167 return 0; 161 return 0;
168 } 162 }
169 static inline void dma_unmap_sg_attrs(struct d 163 static inline void dma_unmap_sg_attrs(struct device *dev,
170 struct scatterlist *sg, int ne 164 struct scatterlist *sg, int nents, enum dma_data_direction dir,
171 unsigned long attrs) 165 unsigned long attrs)
172 { 166 {
173 } 167 }
174 static inline int dma_map_sgtable(struct devic <<
175 enum dma_data_direction dir, u <<
176 { <<
177 return -EOPNOTSUPP; <<
178 } <<
179 static inline dma_addr_t dma_map_resource(stru 168 static inline dma_addr_t dma_map_resource(struct device *dev,
180 phys_addr_t phys_addr, size_t 169 phys_addr_t phys_addr, size_t size, enum dma_data_direction dir,
181 unsigned long attrs) 170 unsigned long attrs)
182 { 171 {
183 return DMA_MAPPING_ERROR; 172 return DMA_MAPPING_ERROR;
184 } 173 }
185 static inline void dma_unmap_resource(struct d 174 static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr,
186 size_t size, enum dma_data_dir 175 size_t size, enum dma_data_direction dir, unsigned long attrs)
187 { 176 {
188 } 177 }
>> 178 static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
>> 179 size_t size, enum dma_data_direction dir)
>> 180 {
>> 181 }
>> 182 static inline void dma_sync_single_for_device(struct device *dev,
>> 183 dma_addr_t addr, size_t size, enum dma_data_direction dir)
>> 184 {
>> 185 }
>> 186 static inline void dma_sync_sg_for_cpu(struct device *dev,
>> 187 struct scatterlist *sg, int nelems, enum dma_data_direction dir)
>> 188 {
>> 189 }
>> 190 static inline void dma_sync_sg_for_device(struct device *dev,
>> 191 struct scatterlist *sg, int nelems, enum dma_data_direction dir)
>> 192 {
>> 193 }
189 static inline int dma_mapping_error(struct dev 194 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
190 { 195 {
191 return -ENOMEM; 196 return -ENOMEM;
192 } 197 }
193 static inline void *dma_alloc_attrs(struct dev 198 static inline void *dma_alloc_attrs(struct device *dev, size_t size,
194 dma_addr_t *dma_handle, gfp_t 199 dma_addr_t *dma_handle, gfp_t flag, unsigned long attrs)
195 { 200 {
196 return NULL; 201 return NULL;
197 } 202 }
198 static void dma_free_attrs(struct device *dev, 203 static void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
199 dma_addr_t dma_handle, unsigne 204 dma_addr_t dma_handle, unsigned long attrs)
200 { 205 {
201 } 206 }
202 static inline void *dmam_alloc_attrs(struct de 207 static inline void *dmam_alloc_attrs(struct device *dev, size_t size,
203 dma_addr_t *dma_handle, gfp_t 208 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
204 { 209 {
205 return NULL; 210 return NULL;
206 } 211 }
207 static inline void dmam_free_coherent(struct d 212 static inline void dmam_free_coherent(struct device *dev, size_t size,
208 void *vaddr, dma_addr_t dma_ha 213 void *vaddr, dma_addr_t dma_handle)
209 { 214 {
210 } 215 }
211 static inline int dma_get_sgtable_attrs(struct 216 static inline int dma_get_sgtable_attrs(struct device *dev,
212 struct sg_table *sgt, void *cp 217 struct sg_table *sgt, void *cpu_addr, dma_addr_t dma_addr,
213 size_t size, unsigned long att 218 size_t size, unsigned long attrs)
214 { 219 {
215 return -ENXIO; 220 return -ENXIO;
216 } 221 }
217 static inline int dma_mmap_attrs(struct device 222 static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
218 void *cpu_addr, dma_addr_t dma 223 void *cpu_addr, dma_addr_t dma_addr, size_t size,
219 unsigned long attrs) 224 unsigned long attrs)
220 { 225 {
221 return -ENXIO; 226 return -ENXIO;
222 } 227 }
223 static inline bool dma_can_mmap(struct device 228 static inline bool dma_can_mmap(struct device *dev)
224 { 229 {
225 return false; 230 return false;
226 } 231 }
227 static inline bool dma_pci_p2pdma_supported(st !! 232 static inline int dma_supported(struct device *dev, u64 mask)
228 { 233 {
229 return false; !! 234 return 0;
230 } 235 }
231 static inline int dma_set_mask(struct device * 236 static inline int dma_set_mask(struct device *dev, u64 mask)
232 { 237 {
233 return -EIO; 238 return -EIO;
234 } 239 }
235 static inline int dma_set_coherent_mask(struct 240 static inline int dma_set_coherent_mask(struct device *dev, u64 mask)
236 { 241 {
237 return -EIO; 242 return -EIO;
238 } 243 }
239 static inline u64 dma_get_required_mask(struct 244 static inline u64 dma_get_required_mask(struct device *dev)
240 { 245 {
241 return 0; 246 return 0;
242 } 247 }
243 static inline bool dma_addressing_limited(stru <<
244 { <<
245 return false; <<
246 } <<
247 static inline size_t dma_max_mapping_size(stru 248 static inline size_t dma_max_mapping_size(struct device *dev)
248 { 249 {
249 return 0; 250 return 0;
250 } 251 }
251 static inline size_t dma_opt_mapping_size(stru !! 252 static inline bool dma_need_sync(struct device *dev, dma_addr_t dma_addr)
252 { 253 {
253 return 0; !! 254 return false;
254 } 255 }
255 static inline unsigned long dma_get_merge_boun 256 static inline unsigned long dma_get_merge_boundary(struct device *dev)
256 { 257 {
257 return 0; 258 return 0;
258 } 259 }
259 static inline struct sg_table *dma_alloc_nonco <<
260 size_t size, enum dma_data_dir <<
261 unsigned long attrs) <<
262 { <<
263 return NULL; <<
264 } <<
265 static inline void dma_free_noncontiguous(stru <<
266 struct sg_table *sgt, enum dma <<
267 { <<
268 } <<
269 static inline void *dma_vmap_noncontiguous(str <<
270 struct sg_table *sgt) <<
271 { <<
272 return NULL; <<
273 } <<
274 static inline void dma_vunmap_noncontiguous(st <<
275 { <<
276 } <<
277 static inline int dma_mmap_noncontiguous(struc <<
278 struct vm_area_struct *vma, si <<
279 { <<
280 return -EINVAL; <<
281 } <<
282 #endif /* CONFIG_HAS_DMA */ 260 #endif /* CONFIG_HAS_DMA */
283 261
284 #if defined(CONFIG_HAS_DMA) && defined(CONFIG_ <<
285 void __dma_sync_single_for_cpu(struct device * <<
286 enum dma_data_direction dir); <<
287 void __dma_sync_single_for_device(struct devic <<
288 size_t size, enum dma_data_dir <<
289 void __dma_sync_sg_for_cpu(struct device *dev, <<
290 int nelems, enum dma_data_dire <<
291 void __dma_sync_sg_for_device(struct device *d <<
292 int nelems, enum dma_data_dire <<
293 bool __dma_need_sync(struct device *dev, dma_a <<
294 <<
295 static inline bool dma_dev_need_sync(const str <<
296 { <<
297 /* Always call DMA sync operations whe <<
298 return !dev->dma_skip_sync || IS_ENABL <<
299 } <<
300 <<
301 static inline void dma_sync_single_for_cpu(str <<
302 size_t size, enum dma_data_dir <<
303 { <<
304 if (dma_dev_need_sync(dev)) <<
305 __dma_sync_single_for_cpu(dev, <<
306 } <<
307 <<
308 static inline void dma_sync_single_for_device( <<
309 dma_addr_t addr, size_t size, <<
310 { <<
311 if (dma_dev_need_sync(dev)) <<
312 __dma_sync_single_for_device(d <<
313 } <<
314 <<
315 static inline void dma_sync_sg_for_cpu(struct <<
316 struct scatterlist *sg, int ne <<
317 { <<
318 if (dma_dev_need_sync(dev)) <<
319 __dma_sync_sg_for_cpu(dev, sg, <<
320 } <<
321 <<
322 static inline void dma_sync_sg_for_device(stru <<
323 struct scatterlist *sg, int ne <<
324 { <<
325 if (dma_dev_need_sync(dev)) <<
326 __dma_sync_sg_for_device(dev, <<
327 } <<
328 <<
329 static inline bool dma_need_sync(struct device <<
330 { <<
331 return dma_dev_need_sync(dev) ? __dma_ <<
332 } <<
333 #else /* !CONFIG_HAS_DMA || !CONFIG_DMA_NEED_S <<
334 static inline bool dma_dev_need_sync(const str <<
335 { <<
336 return false; <<
337 } <<
338 static inline void dma_sync_single_for_cpu(str <<
339 size_t size, enum dma_data_dir <<
340 { <<
341 } <<
342 static inline void dma_sync_single_for_device( <<
343 dma_addr_t addr, size_t size, <<
344 { <<
345 } <<
346 static inline void dma_sync_sg_for_cpu(struct <<
347 struct scatterlist *sg, int ne <<
348 { <<
349 } <<
350 static inline void dma_sync_sg_for_device(stru <<
351 struct scatterlist *sg, int ne <<
352 { <<
353 } <<
354 static inline bool dma_need_sync(struct device <<
355 { <<
356 return false; <<
357 } <<
358 #endif /* !CONFIG_HAS_DMA || !CONFIG_DMA_NEED_ <<
359 <<
360 struct page *dma_alloc_pages(struct device *de 262 struct page *dma_alloc_pages(struct device *dev, size_t size,
361 dma_addr_t *dma_handle, enum d 263 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp);
362 void dma_free_pages(struct device *dev, size_t 264 void dma_free_pages(struct device *dev, size_t size, struct page *page,
363 dma_addr_t dma_handle, enum dm 265 dma_addr_t dma_handle, enum dma_data_direction dir);
364 int dma_mmap_pages(struct device *dev, struct !! 266 void *dma_alloc_noncoherent(struct device *dev, size_t size,
365 size_t size, struct page *page !! 267 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp);
366 !! 268 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
367 static inline void *dma_alloc_noncoherent(stru !! 269 dma_addr_t dma_handle, enum dma_data_direction dir);
368 dma_addr_t *dma_handle, enum d <<
369 { <<
370 struct page *page = dma_alloc_pages(de <<
371 return page ? page_address(page) : NUL <<
372 } <<
373 <<
374 static inline void dma_free_noncoherent(struct <<
375 void *vaddr, dma_addr_t dma_ha <<
376 { <<
377 dma_free_pages(dev, size, virt_to_page <<
378 } <<
379 270
380 static inline dma_addr_t dma_map_single_attrs( 271 static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr,
381 size_t size, enum dma_data_dir 272 size_t size, enum dma_data_direction dir, unsigned long attrs)
382 { 273 {
383 /* DMA must never operate on areas tha 274 /* DMA must never operate on areas that might be remapped. */
384 if (dev_WARN_ONCE(dev, is_vmalloc_addr 275 if (dev_WARN_ONCE(dev, is_vmalloc_addr(ptr),
385 "rejecting DMA map o 276 "rejecting DMA map of vmalloc memory\n"))
386 return DMA_MAPPING_ERROR; 277 return DMA_MAPPING_ERROR;
387 debug_dma_map_single(dev, ptr, size); 278 debug_dma_map_single(dev, ptr, size);
388 return dma_map_page_attrs(dev, virt_to 279 return dma_map_page_attrs(dev, virt_to_page(ptr), offset_in_page(ptr),
389 size, dir, attrs); 280 size, dir, attrs);
390 } 281 }
391 282
392 static inline void dma_unmap_single_attrs(stru 283 static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t addr,
393 size_t size, enum dma_data_dir 284 size_t size, enum dma_data_direction dir, unsigned long attrs)
394 { 285 {
395 return dma_unmap_page_attrs(dev, addr, 286 return dma_unmap_page_attrs(dev, addr, size, dir, attrs);
396 } 287 }
397 288
398 static inline void dma_sync_single_range_for_c 289 static inline void dma_sync_single_range_for_cpu(struct device *dev,
399 dma_addr_t addr, unsigned long 290 dma_addr_t addr, unsigned long offset, size_t size,
400 enum dma_data_direction dir) 291 enum dma_data_direction dir)
401 { 292 {
402 return dma_sync_single_for_cpu(dev, ad 293 return dma_sync_single_for_cpu(dev, addr + offset, size, dir);
403 } 294 }
404 295
405 static inline void dma_sync_single_range_for_d 296 static inline void dma_sync_single_range_for_device(struct device *dev,
406 dma_addr_t addr, unsigned long 297 dma_addr_t addr, unsigned long offset, size_t size,
407 enum dma_data_direction dir) 298 enum dma_data_direction dir)
408 { 299 {
409 return dma_sync_single_for_device(dev, 300 return dma_sync_single_for_device(dev, addr + offset, size, dir);
410 } 301 }
411 302
412 /** 303 /**
>> 304 * dma_map_sgtable - Map the given buffer for DMA
>> 305 * @dev: The device for which to perform the DMA operation
>> 306 * @sgt: The sg_table object describing the buffer
>> 307 * @dir: DMA direction
>> 308 * @attrs: Optional DMA attributes for the map operation
>> 309 *
>> 310 * Maps a buffer described by a scatterlist stored in the given sg_table
>> 311 * object for the @dir DMA operation by the @dev device. After success the
>> 312 * ownership for the buffer is transferred to the DMA domain. One has to
>> 313 * call dma_sync_sgtable_for_cpu() or dma_unmap_sgtable() to move the
>> 314 * ownership of the buffer back to the CPU domain before touching the
>> 315 * buffer by the CPU.
>> 316 *
>> 317 * Returns 0 on success or -EINVAL on error during mapping the buffer.
>> 318 */
>> 319 static inline int dma_map_sgtable(struct device *dev, struct sg_table *sgt,
>> 320 enum dma_data_direction dir, unsigned long attrs)
>> 321 {
>> 322 int nents;
>> 323
>> 324 nents = dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs);
>> 325 if (nents <= 0)
>> 326 return -EINVAL;
>> 327 sgt->nents = nents;
>> 328 return 0;
>> 329 }
>> 330
>> 331 /**
413 * dma_unmap_sgtable - Unmap the given buffer 332 * dma_unmap_sgtable - Unmap the given buffer for DMA
414 * @dev: The device for which to perfor 333 * @dev: The device for which to perform the DMA operation
415 * @sgt: The sg_table object describing 334 * @sgt: The sg_table object describing the buffer
416 * @dir: DMA direction 335 * @dir: DMA direction
417 * @attrs: Optional DMA attributes for th 336 * @attrs: Optional DMA attributes for the unmap operation
418 * 337 *
419 * Unmaps a buffer described by a scatterlist 338 * Unmaps a buffer described by a scatterlist stored in the given sg_table
420 * object for the @dir DMA operation by the @d 339 * object for the @dir DMA operation by the @dev device. After this function
421 * the ownership of the buffer is transferred 340 * the ownership of the buffer is transferred back to the CPU domain.
422 */ 341 */
423 static inline void dma_unmap_sgtable(struct de 342 static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt,
424 enum dma_data_direction dir, u 343 enum dma_data_direction dir, unsigned long attrs)
425 { 344 {
426 dma_unmap_sg_attrs(dev, sgt->sgl, sgt- 345 dma_unmap_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs);
427 } 346 }
428 347
429 /** 348 /**
430 * dma_sync_sgtable_for_cpu - Synchronize the 349 * dma_sync_sgtable_for_cpu - Synchronize the given buffer for CPU access
431 * @dev: The device for which to perfor 350 * @dev: The device for which to perform the DMA operation
432 * @sgt: The sg_table object describing 351 * @sgt: The sg_table object describing the buffer
433 * @dir: DMA direction 352 * @dir: DMA direction
434 * 353 *
435 * Performs the needed cache synchronization a 354 * Performs the needed cache synchronization and moves the ownership of the
436 * buffer back to the CPU domain, so it is saf 355 * buffer back to the CPU domain, so it is safe to perform any access to it
437 * by the CPU. Before doing any further DMA op 356 * by the CPU. Before doing any further DMA operations, one has to transfer
438 * the ownership of the buffer back to the DMA 357 * the ownership of the buffer back to the DMA domain by calling the
439 * dma_sync_sgtable_for_device(). 358 * dma_sync_sgtable_for_device().
440 */ 359 */
441 static inline void dma_sync_sgtable_for_cpu(st 360 static inline void dma_sync_sgtable_for_cpu(struct device *dev,
442 struct sg_table *sgt, enum dma 361 struct sg_table *sgt, enum dma_data_direction dir)
443 { 362 {
444 dma_sync_sg_for_cpu(dev, sgt->sgl, sgt 363 dma_sync_sg_for_cpu(dev, sgt->sgl, sgt->orig_nents, dir);
445 } 364 }
446 365
447 /** 366 /**
448 * dma_sync_sgtable_for_device - Synchronize t 367 * dma_sync_sgtable_for_device - Synchronize the given buffer for DMA
449 * @dev: The device for which to perfor 368 * @dev: The device for which to perform the DMA operation
450 * @sgt: The sg_table object describing 369 * @sgt: The sg_table object describing the buffer
451 * @dir: DMA direction 370 * @dir: DMA direction
452 * 371 *
453 * Performs the needed cache synchronization a 372 * Performs the needed cache synchronization and moves the ownership of the
454 * buffer back to the DMA domain, so it is saf 373 * buffer back to the DMA domain, so it is safe to perform the DMA operation.
455 * Once finished, one has to call dma_sync_sgt 374 * Once finished, one has to call dma_sync_sgtable_for_cpu() or
456 * dma_unmap_sgtable(). 375 * dma_unmap_sgtable().
457 */ 376 */
458 static inline void dma_sync_sgtable_for_device 377 static inline void dma_sync_sgtable_for_device(struct device *dev,
459 struct sg_table *sgt, enum dma 378 struct sg_table *sgt, enum dma_data_direction dir)
460 { 379 {
461 dma_sync_sg_for_device(dev, sgt->sgl, 380 dma_sync_sg_for_device(dev, sgt->sgl, sgt->orig_nents, dir);
462 } 381 }
463 382
464 #define dma_map_single(d, a, s, r) dma_map_sin 383 #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0)
465 #define dma_unmap_single(d, a, s, r) dma_unmap 384 #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0)
466 #define dma_map_sg(d, s, n, r) dma_map_sg_attr 385 #define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, 0)
467 #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_ 386 #define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, 0)
468 #define dma_map_page(d, p, o, s, r) dma_map_pa 387 #define dma_map_page(d, p, o, s, r) dma_map_page_attrs(d, p, o, s, r, 0)
469 #define dma_unmap_page(d, a, s, r) dma_unmap_p 388 #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0)
470 #define dma_get_sgtable(d, t, v, h, s) dma_get 389 #define dma_get_sgtable(d, t, v, h, s) dma_get_sgtable_attrs(d, t, v, h, s, 0)
471 #define dma_mmap_coherent(d, v, c, h, s) dma_m 390 #define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, 0)
472 391
473 bool dma_coherent_ok(struct device *dev, phys_ <<
474 <<
475 static inline void *dma_alloc_coherent(struct 392 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
476 dma_addr_t *dma_handle, gfp_t 393 dma_addr_t *dma_handle, gfp_t gfp)
477 { 394 {
>> 395
478 return dma_alloc_attrs(dev, size, dma_ 396 return dma_alloc_attrs(dev, size, dma_handle, gfp,
479 (gfp & __GFP_NOWARN) ? 397 (gfp & __GFP_NOWARN) ? DMA_ATTR_NO_WARN : 0);
480 } 398 }
481 399
482 static inline void dma_free_coherent(struct de 400 static inline void dma_free_coherent(struct device *dev, size_t size,
483 void *cpu_addr, dma_addr_t dma 401 void *cpu_addr, dma_addr_t dma_handle)
484 { 402 {
485 return dma_free_attrs(dev, size, cpu_a 403 return dma_free_attrs(dev, size, cpu_addr, dma_handle, 0);
486 } 404 }
487 405
488 406
489 static inline u64 dma_get_mask(struct device * 407 static inline u64 dma_get_mask(struct device *dev)
490 { 408 {
491 if (dev->dma_mask && *dev->dma_mask) 409 if (dev->dma_mask && *dev->dma_mask)
492 return *dev->dma_mask; 410 return *dev->dma_mask;
493 return DMA_BIT_MASK(32); 411 return DMA_BIT_MASK(32);
494 } 412 }
495 413
496 /* 414 /*
497 * Set both the DMA mask and the coherent DMA 415 * Set both the DMA mask and the coherent DMA mask to the same thing.
498 * Note that we don't check the return value f 416 * Note that we don't check the return value from dma_set_coherent_mask()
499 * as the DMA API guarantees that the coherent 417 * as the DMA API guarantees that the coherent DMA mask can be set to
500 * the same or smaller than the streaming DMA 418 * the same or smaller than the streaming DMA mask.
501 */ 419 */
502 static inline int dma_set_mask_and_coherent(st 420 static inline int dma_set_mask_and_coherent(struct device *dev, u64 mask)
503 { 421 {
504 int rc = dma_set_mask(dev, mask); 422 int rc = dma_set_mask(dev, mask);
505 if (rc == 0) 423 if (rc == 0)
506 dma_set_coherent_mask(dev, mas 424 dma_set_coherent_mask(dev, mask);
507 return rc; 425 return rc;
508 } 426 }
509 427
510 /* 428 /*
511 * Similar to the above, except it deals with 429 * Similar to the above, except it deals with the case where the device
512 * does not have dev->dma_mask appropriately s 430 * does not have dev->dma_mask appropriately setup.
513 */ 431 */
514 static inline int dma_coerce_mask_and_coherent 432 static inline int dma_coerce_mask_and_coherent(struct device *dev, u64 mask)
515 { 433 {
516 dev->dma_mask = &dev->coherent_dma_mas 434 dev->dma_mask = &dev->coherent_dma_mask;
517 return dma_set_mask_and_coherent(dev, 435 return dma_set_mask_and_coherent(dev, mask);
518 } 436 }
519 437
>> 438 /**
>> 439 * dma_addressing_limited - return if the device is addressing limited
>> 440 * @dev: device to check
>> 441 *
>> 442 * Return %true if the devices DMA mask is too small to address all memory in
>> 443 * the system, else %false. Lack of addressing bits is the prime reason for
>> 444 * bounce buffering, but might not be the only one.
>> 445 */
>> 446 static inline bool dma_addressing_limited(struct device *dev)
>> 447 {
>> 448 return min_not_zero(dma_get_mask(dev), dev->bus_dma_limit) <
>> 449 dma_get_required_mask(dev);
>> 450 }
>> 451
520 static inline unsigned int dma_get_max_seg_siz 452 static inline unsigned int dma_get_max_seg_size(struct device *dev)
521 { 453 {
522 if (dev->dma_parms && dev->dma_parms-> 454 if (dev->dma_parms && dev->dma_parms->max_segment_size)
523 return dev->dma_parms->max_seg 455 return dev->dma_parms->max_segment_size;
524 return SZ_64K; 456 return SZ_64K;
525 } 457 }
526 458
527 static inline void dma_set_max_seg_size(struct !! 459 static inline int dma_set_max_seg_size(struct device *dev, unsigned int size)
528 { 460 {
529 if (WARN_ON_ONCE(!dev->dma_parms)) !! 461 if (dev->dma_parms) {
530 return; !! 462 dev->dma_parms->max_segment_size = size;
531 dev->dma_parms->max_segment_size = siz !! 463 return 0;
>> 464 }
>> 465 return -EIO;
532 } 466 }
533 467
534 static inline unsigned long dma_get_seg_bounda 468 static inline unsigned long dma_get_seg_boundary(struct device *dev)
535 { 469 {
536 if (dev->dma_parms && dev->dma_parms-> 470 if (dev->dma_parms && dev->dma_parms->segment_boundary_mask)
537 return dev->dma_parms->segment 471 return dev->dma_parms->segment_boundary_mask;
538 return ULONG_MAX; 472 return ULONG_MAX;
539 } 473 }
540 474
541 /** 475 /**
542 * dma_get_seg_boundary_nr_pages - return the 476 * dma_get_seg_boundary_nr_pages - return the segment boundary in "page" units
543 * @dev: device to guery the boundary for 477 * @dev: device to guery the boundary for
544 * @page_shift: ilog() of the IOMMU page size 478 * @page_shift: ilog() of the IOMMU page size
545 * 479 *
546 * Return the segment boundary in IOMMU page u 480 * Return the segment boundary in IOMMU page units (which may be different from
547 * the CPU page size) for the passed in device 481 * the CPU page size) for the passed in device.
548 * 482 *
549 * If @dev is NULL a boundary of U32_MAX is as 483 * If @dev is NULL a boundary of U32_MAX is assumed, this case is just for
550 * non-DMA API callers. 484 * non-DMA API callers.
551 */ 485 */
552 static inline unsigned long dma_get_seg_bounda 486 static inline unsigned long dma_get_seg_boundary_nr_pages(struct device *dev,
553 unsigned int page_shift) 487 unsigned int page_shift)
554 { 488 {
555 if (!dev) 489 if (!dev)
556 return (U32_MAX >> page_shift) 490 return (U32_MAX >> page_shift) + 1;
557 return (dma_get_seg_boundary(dev) >> p 491 return (dma_get_seg_boundary(dev) >> page_shift) + 1;
558 } 492 }
559 493
560 static inline void dma_set_seg_boundary(struct !! 494 static inline int dma_set_seg_boundary(struct device *dev, unsigned long mask)
561 { 495 {
562 if (WARN_ON_ONCE(!dev->dma_parms)) !! 496 if (dev->dma_parms) {
563 return; !! 497 dev->dma_parms->segment_boundary_mask = mask;
564 dev->dma_parms->segment_boundary_mask !! 498 return 0;
>> 499 }
>> 500 return -EIO;
565 } 501 }
566 502
567 static inline unsigned int dma_get_min_align_m 503 static inline unsigned int dma_get_min_align_mask(struct device *dev)
568 { 504 {
569 if (dev->dma_parms) 505 if (dev->dma_parms)
570 return dev->dma_parms->min_ali 506 return dev->dma_parms->min_align_mask;
571 return 0; 507 return 0;
572 } 508 }
573 509
574 static inline void dma_set_min_align_mask(stru !! 510 static inline int dma_set_min_align_mask(struct device *dev,
575 unsigned int min_align_mask) 511 unsigned int min_align_mask)
576 { 512 {
577 if (WARN_ON_ONCE(!dev->dma_parms)) 513 if (WARN_ON_ONCE(!dev->dma_parms))
578 return; !! 514 return -EIO;
579 dev->dma_parms->min_align_mask = min_a 515 dev->dma_parms->min_align_mask = min_align_mask;
>> 516 return 0;
580 } 517 }
581 518
582 #ifndef dma_get_cache_alignment <<
583 static inline int dma_get_cache_alignment(void 519 static inline int dma_get_cache_alignment(void)
584 { 520 {
585 #ifdef ARCH_HAS_DMA_MINALIGN !! 521 #ifdef ARCH_DMA_MINALIGN
586 return ARCH_DMA_MINALIGN; 522 return ARCH_DMA_MINALIGN;
587 #endif 523 #endif
588 return 1; 524 return 1;
589 } 525 }
590 #endif <<
591 526
592 static inline void *dmam_alloc_coherent(struct 527 static inline void *dmam_alloc_coherent(struct device *dev, size_t size,
593 dma_addr_t *dma_handle, gfp_t 528 dma_addr_t *dma_handle, gfp_t gfp)
594 { 529 {
595 return dmam_alloc_attrs(dev, size, dma 530 return dmam_alloc_attrs(dev, size, dma_handle, gfp,
596 (gfp & __GFP_NOWARN) ? 531 (gfp & __GFP_NOWARN) ? DMA_ATTR_NO_WARN : 0);
597 } 532 }
598 533
599 static inline void *dma_alloc_wc(struct device 534 static inline void *dma_alloc_wc(struct device *dev, size_t size,
600 dma_addr_t *d 535 dma_addr_t *dma_addr, gfp_t gfp)
601 { 536 {
602 unsigned long attrs = DMA_ATTR_WRITE_C 537 unsigned long attrs = DMA_ATTR_WRITE_COMBINE;
603 538
604 if (gfp & __GFP_NOWARN) 539 if (gfp & __GFP_NOWARN)
605 attrs |= DMA_ATTR_NO_WARN; 540 attrs |= DMA_ATTR_NO_WARN;
606 541
607 return dma_alloc_attrs(dev, size, dma_ 542 return dma_alloc_attrs(dev, size, dma_addr, gfp, attrs);
608 } 543 }
609 544
610 static inline void dma_free_wc(struct device * 545 static inline void dma_free_wc(struct device *dev, size_t size,
611 void *cpu_addr, 546 void *cpu_addr, dma_addr_t dma_addr)
612 { 547 {
613 return dma_free_attrs(dev, size, cpu_a 548 return dma_free_attrs(dev, size, cpu_addr, dma_addr,
614 DMA_ATTR_WRITE_C 549 DMA_ATTR_WRITE_COMBINE);
615 } 550 }
616 551
617 static inline int dma_mmap_wc(struct device *d 552 static inline int dma_mmap_wc(struct device *dev,
618 struct vm_area_s 553 struct vm_area_struct *vma,
619 void *cpu_addr, 554 void *cpu_addr, dma_addr_t dma_addr,
620 size_t size) 555 size_t size)
621 { 556 {
622 return dma_mmap_attrs(dev, vma, cpu_ad 557 return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size,
623 DMA_ATTR_WRITE_C 558 DMA_ATTR_WRITE_COMBINE);
624 } 559 }
625 560
626 #ifdef CONFIG_NEED_DMA_MAP_STATE 561 #ifdef CONFIG_NEED_DMA_MAP_STATE
627 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) 562 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME
628 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) 563 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME
629 #define dma_unmap_addr(PTR, ADDR_NAME) 564 #define dma_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
630 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL 565 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
631 #define dma_unmap_len(PTR, LEN_NAME) 566 #define dma_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
632 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) 567 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
633 #else 568 #else
634 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME) 569 #define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)
635 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME) 570 #define DEFINE_DMA_UNMAP_LEN(LEN_NAME)
636 #define dma_unmap_addr(PTR, ADDR_NAME) 571 #define dma_unmap_addr(PTR, ADDR_NAME) (0)
637 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL 572 #define dma_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
638 #define dma_unmap_len(PTR, LEN_NAME) 573 #define dma_unmap_len(PTR, LEN_NAME) (0)
639 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) 574 #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
640 #endif 575 #endif
641 576
642 #endif /* _LINUX_DMA_MAPPING_H */ 577 #endif /* _LINUX_DMA_MAPPING_H */
643 578
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