1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Copyright (C) 2019 Texas Instruments Incor !! 3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
4 */ 4 */
5 5
6 #ifndef K3_PSIL_H_ 6 #ifndef K3_PSIL_H_
7 #define K3_PSIL_H_ 7 #define K3_PSIL_H_
8 8
9 #include <linux/types.h> 9 #include <linux/types.h>
10 10
11 #define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000 11 #define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000
12 12
13 struct device; 13 struct device;
14 14
15 /** 15 /**
16 * enum udma_tp_level - Channel Throughput Lev 16 * enum udma_tp_level - Channel Throughput Levels
17 * @UDMA_TP_NORMAL: Normal channel 17 * @UDMA_TP_NORMAL: Normal channel
18 * @UDMA_TP_HIGH: High Throughput channe 18 * @UDMA_TP_HIGH: High Throughput channel
19 * @UDMA_TP_ULTRAHIGH: Ultra High Throughput 19 * @UDMA_TP_ULTRAHIGH: Ultra High Throughput channel
20 */ 20 */
21 enum udma_tp_level { 21 enum udma_tp_level {
22 UDMA_TP_NORMAL = 0, 22 UDMA_TP_NORMAL = 0,
23 UDMA_TP_HIGH, 23 UDMA_TP_HIGH,
24 UDMA_TP_ULTRAHIGH, 24 UDMA_TP_ULTRAHIGH,
25 UDMA_TP_LAST, 25 UDMA_TP_LAST,
26 }; 26 };
27 27
28 /** 28 /**
29 * enum psil_endpoint_type - PSI-L Endpoint ty 29 * enum psil_endpoint_type - PSI-L Endpoint type
30 * @PSIL_EP_NATIVE: Normal channel 30 * @PSIL_EP_NATIVE: Normal channel
31 * @PSIL_EP_PDMA_XY: XY mode PDMA 31 * @PSIL_EP_PDMA_XY: XY mode PDMA
32 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA 32 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
33 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA 33 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
34 */ 34 */
35 enum psil_endpoint_type { 35 enum psil_endpoint_type {
36 PSIL_EP_NATIVE = 0, 36 PSIL_EP_NATIVE = 0,
37 PSIL_EP_PDMA_XY, 37 PSIL_EP_PDMA_XY,
38 PSIL_EP_PDMA_MCAN, 38 PSIL_EP_PDMA_MCAN,
39 PSIL_EP_PDMA_AASRC, 39 PSIL_EP_PDMA_AASRC,
40 }; 40 };
41 41
42 /** 42 /**
43 * struct psil_endpoint_config - PSI-L Endpoin 43 * struct psil_endpoint_config - PSI-L Endpoint configuration
44 * @ep_type: PSI-L endpoint type 44 * @ep_type: PSI-L endpoint type
45 * @channel_tpl: Desired throughput lev <<
46 * @pkt_mode: If set, the channel mu 45 * @pkt_mode: If set, the channel must be in Packet mode, otherwise in
47 * TR mode 46 * TR mode
48 * @notdpkt: TDCM must be suppresse 47 * @notdpkt: TDCM must be suppressed on the TX channel
49 * @needs_epib: Endpoint needs EPIB 48 * @needs_epib: Endpoint needs EPIB
>> 49 * @psd_size: If set, PSdata is used by the endpoint
>> 50 * @channel_tpl: Desired throughput level for the channel
50 * @pdma_acc32: ACC32 must be enabled 51 * @pdma_acc32: ACC32 must be enabled on the PDMA side
51 * @pdma_burst: BURST must be enabled 52 * @pdma_burst: BURST must be enabled on the PDMA side
52 * @psd_size: If set, PSdata is used <<
53 * @mapped_channel_id: PKTDMA thread to chann <<
54 * The thread must be ser <<
55 * mapped_channel_id is > <<
56 * @flow_start: PKDMA flow range start <<
57 * channels use flow_id = <<
58 * @flow_num: PKDMA flow count of ma <<
59 * use flow_id == chan_id <<
60 * @default_flow_id: PKDMA default (r)flow <<
61 * Must be within the flo <<
62 */ 53 */
63 struct psil_endpoint_config { 54 struct psil_endpoint_config {
64 enum psil_endpoint_type ep_type; 55 enum psil_endpoint_type ep_type;
65 enum udma_tp_level channel_tpl; <<
66 56
67 unsigned pkt_mode:1; 57 unsigned pkt_mode:1;
68 unsigned notdpkt:1; 58 unsigned notdpkt:1;
69 unsigned needs_epib:1; 59 unsigned needs_epib:1;
>> 60 u32 psd_size;
>> 61 enum udma_tp_level channel_tpl;
>> 62
70 /* PDMA properties, valid for PSIL_EP_ 63 /* PDMA properties, valid for PSIL_EP_PDMA_* */
71 unsigned pdma_acc32:1; 64 unsigned pdma_acc32:1;
72 unsigned pdma_burst:1; 65 unsigned pdma_burst:1;
73 <<
74 u32 psd_size; <<
75 /* PKDMA mapped channel */ <<
76 s16 mapped_channel_id; <<
77 /* PKTDMA tflow and rflow ranges for m <<
78 u16 flow_start; <<
79 u16 flow_num; <<
80 s16 default_flow_id; <<
81 }; 66 };
82 67
83 int psil_set_new_ep_config(struct device *dev, 68 int psil_set_new_ep_config(struct device *dev, const char *name,
84 struct psil_endpoin 69 struct psil_endpoint_config *ep_config);
85 70
86 #endif /* K3_PSIL_H_ */ 71 #endif /* K3_PSIL_H_ */
87 72
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