1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2
3 #ifndef _SPRD_DMA_H_
4 #define _SPRD_DMA_H_
5
6 #define SPRD_DMA_REQ_SHIFT 8
7 #define SPRD_DMA_TRG_MODE_SHIFT 16
8 #define SPRD_DMA_CHN_MODE_SHIFT 24
9 #define SPRD_DMA_FLAGS(chn_mode, trg_mode, req
10 ((chn_mode) << SPRD_DMA_CHN_MODE_SHIFT
11 (trg_mode) << SPRD_DMA_TRG_MODE_SHIFT
12 (req_mode) << SPRD_DMA_REQ_SHIFT | (in
13
14 /*
15 * The Spreadtrum DMA controller supports chan
16 * we can request 2 dma channels, one for sour
17 * destination channel. Each channel is indepe
18 * configurations. Once the source channel's t
19 * trigger the destination channel's transacti
20 * signal.
21 *
22 * To support 2-stage tansfer, we must configu
23 * mode as below definition.
24 */
25
26 /*
27 * enum sprd_dma_chn_mode: define the DMA chan
28 * @SPRD_DMA_CHN_MODE_NONE: No channel mode se
29 * support the 2-stage transfer.
30 * @SPRD_DMA_SRC_CHN0: Channel used as source
31 * @SPRD_DMA_SRC_CHN1: Channel used as source
32 * @SPRD_DMA_DST_CHN0: Channel used as destina
33 * @SPRD_DMA_DST_CHN1: Channel used as destina
34 *
35 * Now the DMA controller can supports 2 group
36 */
37 enum sprd_dma_chn_mode {
38 SPRD_DMA_CHN_MODE_NONE,
39 SPRD_DMA_SRC_CHN0,
40 SPRD_DMA_SRC_CHN1,
41 SPRD_DMA_DST_CHN0,
42 SPRD_DMA_DST_CHN1,
43 };
44
45 /*
46 * enum sprd_dma_trg_mode: define the DMA chan
47 * transfer
48 * @SPRD_DMA_NO_TRG: No trigger setting.
49 * @SPRD_DMA_FRAG_DONE_TRG: Trigger the transa
50 * automatically once the source channel's fra
51 * @SPRD_DMA_BLOCK_DONE_TRG: Trigger the trans
52 * automatically once the source channel's blo
53 * @SPRD_DMA_TRANS_DONE_TRG: Trigger the trans
54 * automatically once the source channel's tra
55 * @SPRD_DMA_LIST_DONE_TRG: Trigger the transa
56 * automatically once the source channel's lin
57 */
58 enum sprd_dma_trg_mode {
59 SPRD_DMA_NO_TRG,
60 SPRD_DMA_FRAG_DONE_TRG,
61 SPRD_DMA_BLOCK_DONE_TRG,
62 SPRD_DMA_TRANS_DONE_TRG,
63 SPRD_DMA_LIST_DONE_TRG,
64 };
65
66 /*
67 * enum sprd_dma_req_mode: define the DMA requ
68 * @SPRD_DMA_FRAG_REQ: fragment request mode
69 * @SPRD_DMA_BLK_REQ: block request mode
70 * @SPRD_DMA_TRANS_REQ: transaction request mo
71 * @SPRD_DMA_LIST_REQ: link-list request mode
72 *
73 * We have 4 types request mode: fragment mode
74 * and linklist mode. One transaction can cont
75 * contain several fragments. Link-list mode m
76 * configuration into one reserved memory, the
77 * configuration automatically to start transf
78 */
79 enum sprd_dma_req_mode {
80 SPRD_DMA_FRAG_REQ,
81 SPRD_DMA_BLK_REQ,
82 SPRD_DMA_TRANS_REQ,
83 SPRD_DMA_LIST_REQ,
84 };
85
86 /*
87 * enum sprd_dma_int_type: define the DMA inte
88 * @SPRD_DMA_NO_INT: do not need generate DMA
89 * @SPRD_DMA_FRAG_INT: fragment done interrupt
90 * is done.
91 * @SPRD_DMA_BLK_INT: block done interrupt whe
92 * @SPRD_DMA_BLK_FRAG_INT: block and fragment
93 * or one block request is done.
94 * @SPRD_DMA_TRANS_INT: tansaction done interr
95 * request is done.
96 * @SPRD_DMA_TRANS_FRAG_INT: transaction and f
97 * transaction request or fragment request is
98 * @SPRD_DMA_TRANS_BLK_INT: transaction and bl
99 * transaction request or block request is don
100 * @SPRD_DMA_LIST_INT: link-list done interrup
101 * is done.
102 * @SPRD_DMA_CFGERR_INT: configure error inter
103 * incorrect.
104 */
105 enum sprd_dma_int_type {
106 SPRD_DMA_NO_INT,
107 SPRD_DMA_FRAG_INT,
108 SPRD_DMA_BLK_INT,
109 SPRD_DMA_BLK_FRAG_INT,
110 SPRD_DMA_TRANS_INT,
111 SPRD_DMA_TRANS_FRAG_INT,
112 SPRD_DMA_TRANS_BLK_INT,
113 SPRD_DMA_LIST_INT,
114 SPRD_DMA_CFGERR_INT,
115 };
116
117 /*
118 * struct sprd_dma_linklist - DMA link-list ad
119 * @virt_addr: link-list virtual address to co
120 * @phy_addr: link-list physical address to li
121 * @wrap_addr: the wrap address for link-list
122 * transfer address reaches the wrap address,
123 * will jump to the address specified by wrap_
124 *
125 * The Spreadtrum DMA controller supports the
126 * can supply several groups configurations (e
127 * DMA transfer) saved in memory, and DMA cont
128 * configurations by writing the physical addr
129 * link-list register.
130 *
131 * Just as shown below, the link-list pointer
132 * physical address of 'configuration 1', and
133 * pointer will be pointed to 'configuration 2
134 * Once trigger the DMA transfer, the DMA cont
135 * 1' to its registers automatically, after 'c
136 * done, DMA controller will load 'configurati
137 * DMA transactions are done.
138 *
139 * Note: The last link-list pointer should poi
140 * of 'configuration 1', which can avoid DMA c
141 * configuration when the last configuration t
142 *
143 * DMA controller linkl
144 * ====================== --------
145 *| | | conf
146 *| DMA controller | ------->|
147 *| | | |
148 *| | | |
149 *| | | |
150 *| linklist pointer reg |---- ----| link
151 * ====================== | --------
152 * |
153 * | --------
154 * | | conf
155 * --->|
156 * |
157 * |
158 * |
159 * ----| link
160 * | --------
161 * |
162 * | --------
163 * | | conf
164 * --->|
165 * |
166 * |
167 *
168 *
169 *
170 * |
171 * | --------
172 * | | conf
173 * --->|
174 * |
175 * |
176 * |
177 * | link
178 * --------
179 *
180 * To support the link-list mode, DMA slaves s
181 * from always-on IRAM or dma coherent memory
182 * configuration, and pass the virtual and phy
183 */
184 struct sprd_dma_linklist {
185 unsigned long virt_addr;
186 phys_addr_t phy_addr;
187 phys_addr_t wrap_addr;
188 };
189
190 #endif
191
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.