1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* Freescale Integrated Flash Controller 1 /* Freescale Integrated Flash Controller
3 * 2 *
4 * Copyright 2011 Freescale Semiconductor, Inc 3 * Copyright 2011 Freescale Semiconductor, Inc
5 * 4 *
6 * Author: Dipen Dudhat <dipen.dudhat@freescal 5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License as published by
>> 9 * the Free Software Foundation; either version 2 of the License, or
>> 10 * (at your option) any later version.
>> 11 *
>> 12 * This program is distributed in the hope that it will be useful,
>> 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 15 * GNU General Public License for more details.
>> 16 *
>> 17 * You should have received a copy of the GNU General Public License
>> 18 * along with this program; if not, write to the Free Software
>> 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7 */ 20 */
8 21
9 #ifndef __ASM_FSL_IFC_H 22 #ifndef __ASM_FSL_IFC_H
10 #define __ASM_FSL_IFC_H 23 #define __ASM_FSL_IFC_H
11 24
12 #include <linux/compiler.h> 25 #include <linux/compiler.h>
13 #include <linux/types.h> 26 #include <linux/types.h>
14 #include <linux/io.h> 27 #include <linux/io.h>
15 28
16 #include <linux/of_platform.h> 29 #include <linux/of_platform.h>
17 #include <linux/interrupt.h> 30 #include <linux/interrupt.h>
18 31
19 /* 32 /*
20 * The actual number of banks implemented depe 33 * The actual number of banks implemented depends on the IFC version
21 * - IFC version 1.0 implements 4 banks. 34 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 ba 35 * - IFC version 1.1 onward implements 8 banks.
23 */ 36 */
24 #define FSL_IFC_BANK_COUNT 8 37 #define FSL_IFC_BANK_COUNT 8
25 38
26 #define FSL_IFC_VERSION_MASK 0x0F0F0000 39 #define FSL_IFC_VERSION_MASK 0x0F0F0000
27 #define FSL_IFC_VERSION_1_0_0 0x01000000 40 #define FSL_IFC_VERSION_1_0_0 0x01000000
28 #define FSL_IFC_VERSION_1_1_0 0x01010000 41 #define FSL_IFC_VERSION_1_1_0 0x01010000
29 #define FSL_IFC_VERSION_2_0_0 0x02000000 42 #define FSL_IFC_VERSION_2_0_0 0x02000000
30 43
31 #define PGOFFSET_64K (64*1024) 44 #define PGOFFSET_64K (64*1024)
32 #define PGOFFSET_4K (4*1024) 45 #define PGOFFSET_4K (4*1024)
33 46
34 /* 47 /*
35 * CSPR - Chip Select Property Register 48 * CSPR - Chip Select Property Register
36 */ 49 */
37 #define CSPR_BA 0xFFFF 50 #define CSPR_BA 0xFFFF0000
38 #define CSPR_BA_SHIFT 16 51 #define CSPR_BA_SHIFT 16
39 #define CSPR_PORT_SIZE 0x0000 52 #define CSPR_PORT_SIZE 0x00000180
40 #define CSPR_PORT_SIZE_SHIFT 7 53 #define CSPR_PORT_SIZE_SHIFT 7
41 /* Port Size 8 bit */ 54 /* Port Size 8 bit */
42 #define CSPR_PORT_SIZE_8 0x0000 55 #define CSPR_PORT_SIZE_8 0x00000080
43 /* Port Size 16 bit */ 56 /* Port Size 16 bit */
44 #define CSPR_PORT_SIZE_16 0x0000 57 #define CSPR_PORT_SIZE_16 0x00000100
45 /* Port Size 32 bit */ 58 /* Port Size 32 bit */
46 #define CSPR_PORT_SIZE_32 0x0000 59 #define CSPR_PORT_SIZE_32 0x00000180
47 /* Write Protect */ 60 /* Write Protect */
48 #define CSPR_WP 0x0000 61 #define CSPR_WP 0x00000040
49 #define CSPR_WP_SHIFT 6 62 #define CSPR_WP_SHIFT 6
50 /* Machine Select */ 63 /* Machine Select */
51 #define CSPR_MSEL 0x0000 64 #define CSPR_MSEL 0x00000006
52 #define CSPR_MSEL_SHIFT 1 65 #define CSPR_MSEL_SHIFT 1
53 /* NOR */ 66 /* NOR */
54 #define CSPR_MSEL_NOR 0x0000 67 #define CSPR_MSEL_NOR 0x00000000
55 /* NAND */ 68 /* NAND */
56 #define CSPR_MSEL_NAND 0x0000 69 #define CSPR_MSEL_NAND 0x00000002
57 /* GPCM */ 70 /* GPCM */
58 #define CSPR_MSEL_GPCM 0x0000 71 #define CSPR_MSEL_GPCM 0x00000004
59 /* Bank Valid */ 72 /* Bank Valid */
60 #define CSPR_V 0x0000 73 #define CSPR_V 0x00000001
61 #define CSPR_V_SHIFT 0 74 #define CSPR_V_SHIFT 0
62 75
63 /* 76 /*
64 * Address Mask Register 77 * Address Mask Register
65 */ 78 */
66 #define IFC_AMASK_MASK 0xFFFF 79 #define IFC_AMASK_MASK 0xFFFF0000
67 #define IFC_AMASK_SHIFT 16 80 #define IFC_AMASK_SHIFT 16
68 #define IFC_AMASK(n) (IFC_A 81 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
69 (__ilo 82 (__ilog2(n) - IFC_AMASK_SHIFT))
70 83
71 /* 84 /*
72 * Chip Select Option Register IFC_NAND Machin 85 * Chip Select Option Register IFC_NAND Machine
73 */ 86 */
74 /* Enable ECC Encoder */ 87 /* Enable ECC Encoder */
75 #define CSOR_NAND_ECC_ENC_EN 0x8000 88 #define CSOR_NAND_ECC_ENC_EN 0x80000000
76 #define CSOR_NAND_ECC_MODE_MASK 0x3000 89 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
77 /* 4 bit correction per 520 Byte sector */ 90 /* 4 bit correction per 520 Byte sector */
78 #define CSOR_NAND_ECC_MODE_4 0x0000 91 #define CSOR_NAND_ECC_MODE_4 0x00000000
79 /* 8 bit correction per 528 Byte sector */ 92 /* 8 bit correction per 528 Byte sector */
80 #define CSOR_NAND_ECC_MODE_8 0x1000 93 #define CSOR_NAND_ECC_MODE_8 0x10000000
81 /* Enable ECC Decoder */ 94 /* Enable ECC Decoder */
82 #define CSOR_NAND_ECC_DEC_EN 0x0400 95 #define CSOR_NAND_ECC_DEC_EN 0x04000000
83 /* Row Address Length */ 96 /* Row Address Length */
84 #define CSOR_NAND_RAL_MASK 0x0180 97 #define CSOR_NAND_RAL_MASK 0x01800000
85 #define CSOR_NAND_RAL_SHIFT 20 98 #define CSOR_NAND_RAL_SHIFT 20
86 #define CSOR_NAND_RAL_1 0x0000 99 #define CSOR_NAND_RAL_1 0x00000000
87 #define CSOR_NAND_RAL_2 0x0080 100 #define CSOR_NAND_RAL_2 0x00800000
88 #define CSOR_NAND_RAL_3 0x0100 101 #define CSOR_NAND_RAL_3 0x01000000
89 #define CSOR_NAND_RAL_4 0x0180 102 #define CSOR_NAND_RAL_4 0x01800000
90 /* Page Size 512b, 2k, 4k */ 103 /* Page Size 512b, 2k, 4k */
91 #define CSOR_NAND_PGS_MASK 0x0018 104 #define CSOR_NAND_PGS_MASK 0x00180000
92 #define CSOR_NAND_PGS_SHIFT 16 105 #define CSOR_NAND_PGS_SHIFT 16
93 #define CSOR_NAND_PGS_512 0x0000 106 #define CSOR_NAND_PGS_512 0x00000000
94 #define CSOR_NAND_PGS_2K 0x0008 107 #define CSOR_NAND_PGS_2K 0x00080000
95 #define CSOR_NAND_PGS_4K 0x0010 108 #define CSOR_NAND_PGS_4K 0x00100000
96 #define CSOR_NAND_PGS_8K 0x0018 109 #define CSOR_NAND_PGS_8K 0x00180000
97 /* Spare region Size */ 110 /* Spare region Size */
98 #define CSOR_NAND_SPRZ_MASK 0x0000 111 #define CSOR_NAND_SPRZ_MASK 0x0000E000
99 #define CSOR_NAND_SPRZ_SHIFT 13 112 #define CSOR_NAND_SPRZ_SHIFT 13
100 #define CSOR_NAND_SPRZ_16 0x0000 113 #define CSOR_NAND_SPRZ_16 0x00000000
101 #define CSOR_NAND_SPRZ_64 0x0000 114 #define CSOR_NAND_SPRZ_64 0x00002000
102 #define CSOR_NAND_SPRZ_128 0x0000 115 #define CSOR_NAND_SPRZ_128 0x00004000
103 #define CSOR_NAND_SPRZ_210 0x0000 116 #define CSOR_NAND_SPRZ_210 0x00006000
104 #define CSOR_NAND_SPRZ_218 0x0000 117 #define CSOR_NAND_SPRZ_218 0x00008000
105 #define CSOR_NAND_SPRZ_224 0x0000 118 #define CSOR_NAND_SPRZ_224 0x0000A000
106 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000 119 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
107 /* Pages Per Block */ 120 /* Pages Per Block */
108 #define CSOR_NAND_PB_MASK 0x0000 121 #define CSOR_NAND_PB_MASK 0x00000700
109 #define CSOR_NAND_PB_SHIFT 8 122 #define CSOR_NAND_PB_SHIFT 8
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 123 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
111 /* Time for Read Enable High to Output High Im 124 /* Time for Read Enable High to Output High Impedance */
112 #define CSOR_NAND_TRHZ_MASK 0x0000 125 #define CSOR_NAND_TRHZ_MASK 0x0000001C
113 #define CSOR_NAND_TRHZ_SHIFT 2 126 #define CSOR_NAND_TRHZ_SHIFT 2
114 #define CSOR_NAND_TRHZ_20 0x0000 127 #define CSOR_NAND_TRHZ_20 0x00000000
115 #define CSOR_NAND_TRHZ_40 0x0000 128 #define CSOR_NAND_TRHZ_40 0x00000004
116 #define CSOR_NAND_TRHZ_60 0x0000 129 #define CSOR_NAND_TRHZ_60 0x00000008
117 #define CSOR_NAND_TRHZ_80 0x0000 130 #define CSOR_NAND_TRHZ_80 0x0000000C
118 #define CSOR_NAND_TRHZ_100 0x0000 131 #define CSOR_NAND_TRHZ_100 0x00000010
119 /* Buffer control disable */ 132 /* Buffer control disable */
120 #define CSOR_NAND_BCTLD 0x0000 133 #define CSOR_NAND_BCTLD 0x00000001
121 134
122 /* 135 /*
123 * Chip Select Option Register - NOR Flash Mod 136 * Chip Select Option Register - NOR Flash Mode
124 */ 137 */
125 /* Enable Address shift Mode */ 138 /* Enable Address shift Mode */
126 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x8000 139 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
127 /* Page Read Enable from NOR device */ 140 /* Page Read Enable from NOR device */
128 #define CSOR_NOR_PGRD_EN 0x1000 141 #define CSOR_NOR_PGRD_EN 0x10000000
129 /* AVD Toggle Enable during Burst Program */ 142 /* AVD Toggle Enable during Burst Program */
130 #define CSOR_NOR_AVD_TGL_PGM_EN 0x0100 143 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
131 /* Address Data Multiplexing Shift */ 144 /* Address Data Multiplexing Shift */
132 #define CSOR_NOR_ADM_MASK 0x0003 145 #define CSOR_NOR_ADM_MASK 0x0003E000
133 #define CSOR_NOR_ADM_SHIFT_SHIFT 13 146 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
134 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_N 147 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
135 /* Type of the NOR device hooked */ 148 /* Type of the NOR device hooked */
136 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x0000 149 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
137 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x0000 150 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
138 /* Time for Read Enable High to Output High Im 151 /* Time for Read Enable High to Output High Impedance */
139 #define CSOR_NOR_TRHZ_MASK 0x0000 152 #define CSOR_NOR_TRHZ_MASK 0x0000001C
140 #define CSOR_NOR_TRHZ_SHIFT 2 153 #define CSOR_NOR_TRHZ_SHIFT 2
141 #define CSOR_NOR_TRHZ_20 0x0000 154 #define CSOR_NOR_TRHZ_20 0x00000000
142 #define CSOR_NOR_TRHZ_40 0x0000 155 #define CSOR_NOR_TRHZ_40 0x00000004
143 #define CSOR_NOR_TRHZ_60 0x0000 156 #define CSOR_NOR_TRHZ_60 0x00000008
144 #define CSOR_NOR_TRHZ_80 0x0000 157 #define CSOR_NOR_TRHZ_80 0x0000000C
145 #define CSOR_NOR_TRHZ_100 0x0000 158 #define CSOR_NOR_TRHZ_100 0x00000010
146 /* Buffer control disable */ 159 /* Buffer control disable */
147 #define CSOR_NOR_BCTLD 0x0000 160 #define CSOR_NOR_BCTLD 0x00000001
148 161
149 /* 162 /*
150 * Chip Select Option Register - GPCM Mode 163 * Chip Select Option Register - GPCM Mode
151 */ 164 */
152 /* GPCM Mode - Normal */ 165 /* GPCM Mode - Normal */
153 #define CSOR_GPCM_GPMODE_NORMAL 0x0000 166 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
154 /* GPCM Mode - GenericASIC */ 167 /* GPCM Mode - GenericASIC */
155 #define CSOR_GPCM_GPMODE_ASIC 0x8000 168 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
156 /* Parity Mode odd/even */ 169 /* Parity Mode odd/even */
157 #define CSOR_GPCM_PARITY_EVEN 0x4000 170 #define CSOR_GPCM_PARITY_EVEN 0x40000000
158 /* Parity Checking enable/disable */ 171 /* Parity Checking enable/disable */
159 #define CSOR_GPCM_PAR_EN 0x2000 172 #define CSOR_GPCM_PAR_EN 0x20000000
160 /* GPCM Timeout Count */ 173 /* GPCM Timeout Count */
161 #define CSOR_GPCM_GPTO_MASK 0x0F00 174 #define CSOR_GPCM_GPTO_MASK 0x0F000000
162 #define CSOR_GPCM_GPTO_SHIFT 24 175 #define CSOR_GPCM_GPTO_SHIFT 24
163 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 176 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
164 /* GPCM External Access Termination mode for r 177 /* GPCM External Access Termination mode for read access */
165 #define CSOR_GPCM_RGETA_EXT 0x0008 178 #define CSOR_GPCM_RGETA_EXT 0x00080000
166 /* GPCM External Access Termination mode for w 179 /* GPCM External Access Termination mode for write access */
167 #define CSOR_GPCM_WGETA_EXT 0x0004 180 #define CSOR_GPCM_WGETA_EXT 0x00040000
168 /* Address Data Multiplexing Shift */ 181 /* Address Data Multiplexing Shift */
169 #define CSOR_GPCM_ADM_MASK 0x0003 182 #define CSOR_GPCM_ADM_MASK 0x0003E000
170 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13 183 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
171 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_G 184 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
172 /* Generic ASIC Parity error indication delay 185 /* Generic ASIC Parity error indication delay */
173 #define CSOR_GPCM_GAPERRD_MASK 0x0000 186 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
174 #define CSOR_GPCM_GAPERRD_SHIFT 7 187 #define CSOR_GPCM_GAPERRD_SHIFT 7
175 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << 188 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
176 /* Time for Read Enable High to Output High Im 189 /* Time for Read Enable High to Output High Impedance */
177 #define CSOR_GPCM_TRHZ_MASK 0x0000 190 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
178 #define CSOR_GPCM_TRHZ_20 0x0000 191 #define CSOR_GPCM_TRHZ_20 0x00000000
179 #define CSOR_GPCM_TRHZ_40 0x0000 192 #define CSOR_GPCM_TRHZ_40 0x00000004
180 #define CSOR_GPCM_TRHZ_60 0x0000 193 #define CSOR_GPCM_TRHZ_60 0x00000008
181 #define CSOR_GPCM_TRHZ_80 0x0000 194 #define CSOR_GPCM_TRHZ_80 0x0000000C
182 #define CSOR_GPCM_TRHZ_100 0x0000 195 #define CSOR_GPCM_TRHZ_100 0x00000010
183 /* Buffer control disable */ 196 /* Buffer control disable */
184 #define CSOR_GPCM_BCTLD 0x0000 197 #define CSOR_GPCM_BCTLD 0x00000001
185 198
186 /* 199 /*
187 * Ready Busy Status Register (RB_STAT) 200 * Ready Busy Status Register (RB_STAT)
188 */ 201 */
189 /* CSn is READY */ 202 /* CSn is READY */
190 #define IFC_RB_STAT_READY_CS0 0x8000 203 #define IFC_RB_STAT_READY_CS0 0x80000000
191 #define IFC_RB_STAT_READY_CS1 0x4000 204 #define IFC_RB_STAT_READY_CS1 0x40000000
192 #define IFC_RB_STAT_READY_CS2 0x2000 205 #define IFC_RB_STAT_READY_CS2 0x20000000
193 #define IFC_RB_STAT_READY_CS3 0x1000 206 #define IFC_RB_STAT_READY_CS3 0x10000000
194 207
195 /* 208 /*
196 * General Control Register (GCR) 209 * General Control Register (GCR)
197 */ 210 */
198 #define IFC_GCR_MASK 0x8000 211 #define IFC_GCR_MASK 0x8000F800
199 /* reset all IFC hardware */ 212 /* reset all IFC hardware */
200 #define IFC_GCR_SOFT_RST_ALL 0x8000 213 #define IFC_GCR_SOFT_RST_ALL 0x80000000
201 /* Turnaroud Time of external buffer */ 214 /* Turnaroud Time of external buffer */
202 #define IFC_GCR_TBCTL_TRN_TIME 0x0000 215 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
203 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 216 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
204 217
205 /* 218 /*
206 * Common Event and Error Status Register (CM_ 219 * Common Event and Error Status Register (CM_EVTER_STAT)
207 */ 220 */
208 /* Chip select error */ 221 /* Chip select error */
209 #define IFC_CM_EVTER_STAT_CSER 0x8000 222 #define IFC_CM_EVTER_STAT_CSER 0x80000000
210 223
211 /* 224 /*
212 * Common Event and Error Enable Register (CM_ 225 * Common Event and Error Enable Register (CM_EVTER_EN)
213 */ 226 */
214 /* Chip select error checking enable */ 227 /* Chip select error checking enable */
215 #define IFC_CM_EVTER_EN_CSEREN 0x8000 228 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
216 229
217 /* 230 /*
218 * Common Event and Error Interrupt Enable Reg 231 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
219 */ 232 */
220 /* Chip select error interrupt enable */ 233 /* Chip select error interrupt enable */
221 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x8000 234 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
222 235
223 /* 236 /*
224 * Common Transfer Error Attribute Register-0 237 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
225 */ 238 */
226 /* transaction type of error Read/Write */ 239 /* transaction type of error Read/Write */
227 #define IFC_CM_ERATTR0_ERTYP_READ 0x8000 240 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
228 #define IFC_CM_ERATTR0_ERAID 0x0FF0 241 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
229 #define IFC_CM_ERATTR0_ERAID_SHIFT 20 242 #define IFC_CM_ERATTR0_ERAID_SHIFT 20
230 #define IFC_CM_ERATTR0_ESRCID 0x0000 243 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
231 #define IFC_CM_ERATTR0_ESRCID_SHIFT 8 244 #define IFC_CM_ERATTR0_ESRCID_SHIFT 8
232 245
233 /* 246 /*
234 * Clock Control Register (CCR) 247 * Clock Control Register (CCR)
235 */ 248 */
236 #define IFC_CCR_MASK 0x0F0F 249 #define IFC_CCR_MASK 0x0F0F8800
237 /* Clock division ratio */ 250 /* Clock division ratio */
238 #define IFC_CCR_CLK_DIV_MASK 0x0F00 251 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
239 #define IFC_CCR_CLK_DIV_SHIFT 24 252 #define IFC_CCR_CLK_DIV_SHIFT 24
240 #define IFC_CCR_CLK_DIV(n) ((n-1) 253 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
241 /* IFC Clock Delay */ 254 /* IFC Clock Delay */
242 #define IFC_CCR_CLK_DLY_MASK 0x000F 255 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
243 #define IFC_CCR_CLK_DLY_SHIFT 16 256 #define IFC_CCR_CLK_DLY_SHIFT 16
244 #define IFC_CCR_CLK_DLY(n) ((n) < 257 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
245 /* Invert IFC clock before sending out */ 258 /* Invert IFC clock before sending out */
246 #define IFC_CCR_INV_CLK_EN 0x0000 259 #define IFC_CCR_INV_CLK_EN 0x00008000
247 /* Fedback IFC Clock */ 260 /* Fedback IFC Clock */
248 #define IFC_CCR_FB_IFC_CLK_SEL 0x0000 261 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
249 262
250 /* 263 /*
251 * Clock Status Register (CSR) 264 * Clock Status Register (CSR)
252 */ 265 */
253 /* Clk is stable */ 266 /* Clk is stable */
254 #define IFC_CSR_CLK_STAT_STABLE 0x8000 267 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
255 268
256 /* 269 /*
257 * IFC_NAND Machine Specific Registers 270 * IFC_NAND Machine Specific Registers
258 */ 271 */
259 /* 272 /*
260 * NAND Configuration Register (NCFGR) 273 * NAND Configuration Register (NCFGR)
261 */ 274 */
262 /* Auto Boot Mode */ 275 /* Auto Boot Mode */
263 #define IFC_NAND_NCFGR_BOOT 0x8000 276 #define IFC_NAND_NCFGR_BOOT 0x80000000
264 /* SRAM Initialization */ <<
265 #define IFC_NAND_NCFGR_SRAM_INIT_EN 0x2000 <<
266 /* Addressing Mode-ROW0+n/COL0 */ 277 /* Addressing Mode-ROW0+n/COL0 */
267 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x0000 278 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
268 /* Addressing Mode-ROW0+n/COL0+n */ 279 /* Addressing Mode-ROW0+n/COL0+n */
269 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x0040 280 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
270 /* Number of loop iterations of FIR sequences 281 /* Number of loop iterations of FIR sequences for multi page operations */
271 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000 282 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
272 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 283 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
273 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) < 284 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
274 /* Number of wait cycles */ 285 /* Number of wait cycles */
275 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x0000 286 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
276 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 287 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
277 288
278 /* 289 /*
279 * NAND Flash Command Registers (NAND_FCR0/NAN 290 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
280 */ 291 */
281 /* General purpose FCM flash command bytes CMD 292 /* General purpose FCM flash command bytes CMD0-CMD7 */
282 #define IFC_NAND_FCR0_CMD0 0xFF00 293 #define IFC_NAND_FCR0_CMD0 0xFF000000
283 #define IFC_NAND_FCR0_CMD0_SHIFT 24 294 #define IFC_NAND_FCR0_CMD0_SHIFT 24
284 #define IFC_NAND_FCR0_CMD1 0x00FF 295 #define IFC_NAND_FCR0_CMD1 0x00FF0000
285 #define IFC_NAND_FCR0_CMD1_SHIFT 16 296 #define IFC_NAND_FCR0_CMD1_SHIFT 16
286 #define IFC_NAND_FCR0_CMD2 0x0000 297 #define IFC_NAND_FCR0_CMD2 0x0000FF00
287 #define IFC_NAND_FCR0_CMD2_SHIFT 8 298 #define IFC_NAND_FCR0_CMD2_SHIFT 8
288 #define IFC_NAND_FCR0_CMD3 0x0000 299 #define IFC_NAND_FCR0_CMD3 0x000000FF
289 #define IFC_NAND_FCR0_CMD3_SHIFT 0 300 #define IFC_NAND_FCR0_CMD3_SHIFT 0
290 #define IFC_NAND_FCR1_CMD4 0xFF00 301 #define IFC_NAND_FCR1_CMD4 0xFF000000
291 #define IFC_NAND_FCR1_CMD4_SHIFT 24 302 #define IFC_NAND_FCR1_CMD4_SHIFT 24
292 #define IFC_NAND_FCR1_CMD5 0x00FF 303 #define IFC_NAND_FCR1_CMD5 0x00FF0000
293 #define IFC_NAND_FCR1_CMD5_SHIFT 16 304 #define IFC_NAND_FCR1_CMD5_SHIFT 16
294 #define IFC_NAND_FCR1_CMD6 0x0000 305 #define IFC_NAND_FCR1_CMD6 0x0000FF00
295 #define IFC_NAND_FCR1_CMD6_SHIFT 8 306 #define IFC_NAND_FCR1_CMD6_SHIFT 8
296 #define IFC_NAND_FCR1_CMD7 0x0000 307 #define IFC_NAND_FCR1_CMD7 0x000000FF
297 #define IFC_NAND_FCR1_CMD7_SHIFT 0 308 #define IFC_NAND_FCR1_CMD7_SHIFT 0
298 309
299 /* 310 /*
300 * Flash ROW and COL Address Register (ROWn, C 311 * Flash ROW and COL Address Register (ROWn, COLn)
301 */ 312 */
302 /* Main/spare region locator */ 313 /* Main/spare region locator */
303 #define IFC_NAND_COL_MS 0x8000 314 #define IFC_NAND_COL_MS 0x80000000
304 /* Column Address */ 315 /* Column Address */
305 #define IFC_NAND_COL_CA_MASK 0x0000 316 #define IFC_NAND_COL_CA_MASK 0x00000FFF
306 317
307 /* 318 /*
308 * NAND Flash Byte Count Register (NAND_BC) 319 * NAND Flash Byte Count Register (NAND_BC)
309 */ 320 */
310 /* Byte Count for read/Write */ 321 /* Byte Count for read/Write */
311 #define IFC_NAND_BC 0x0000 322 #define IFC_NAND_BC 0x000001FF
312 323
313 /* 324 /*
314 * NAND Flash Instruction Registers (NAND_FIR0 325 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
315 */ 326 */
316 /* NAND Machine specific opcodes OP0-OP14*/ 327 /* NAND Machine specific opcodes OP0-OP14*/
317 #define IFC_NAND_FIR0_OP0 0xFC00 328 #define IFC_NAND_FIR0_OP0 0xFC000000
318 #define IFC_NAND_FIR0_OP0_SHIFT 26 329 #define IFC_NAND_FIR0_OP0_SHIFT 26
319 #define IFC_NAND_FIR0_OP1 0x03F0 330 #define IFC_NAND_FIR0_OP1 0x03F00000
320 #define IFC_NAND_FIR0_OP1_SHIFT 20 331 #define IFC_NAND_FIR0_OP1_SHIFT 20
321 #define IFC_NAND_FIR0_OP2 0x000F 332 #define IFC_NAND_FIR0_OP2 0x000FC000
322 #define IFC_NAND_FIR0_OP2_SHIFT 14 333 #define IFC_NAND_FIR0_OP2_SHIFT 14
323 #define IFC_NAND_FIR0_OP3 0x0000 334 #define IFC_NAND_FIR0_OP3 0x00003F00
324 #define IFC_NAND_FIR0_OP3_SHIFT 8 335 #define IFC_NAND_FIR0_OP3_SHIFT 8
325 #define IFC_NAND_FIR0_OP4 0x0000 336 #define IFC_NAND_FIR0_OP4 0x000000FC
326 #define IFC_NAND_FIR0_OP4_SHIFT 2 337 #define IFC_NAND_FIR0_OP4_SHIFT 2
327 #define IFC_NAND_FIR1_OP5 0xFC00 338 #define IFC_NAND_FIR1_OP5 0xFC000000
328 #define IFC_NAND_FIR1_OP5_SHIFT 26 339 #define IFC_NAND_FIR1_OP5_SHIFT 26
329 #define IFC_NAND_FIR1_OP6 0x03F0 340 #define IFC_NAND_FIR1_OP6 0x03F00000
330 #define IFC_NAND_FIR1_OP6_SHIFT 20 341 #define IFC_NAND_FIR1_OP6_SHIFT 20
331 #define IFC_NAND_FIR1_OP7 0x000F 342 #define IFC_NAND_FIR1_OP7 0x000FC000
332 #define IFC_NAND_FIR1_OP7_SHIFT 14 343 #define IFC_NAND_FIR1_OP7_SHIFT 14
333 #define IFC_NAND_FIR1_OP8 0x0000 344 #define IFC_NAND_FIR1_OP8 0x00003F00
334 #define IFC_NAND_FIR1_OP8_SHIFT 8 345 #define IFC_NAND_FIR1_OP8_SHIFT 8
335 #define IFC_NAND_FIR1_OP9 0x0000 346 #define IFC_NAND_FIR1_OP9 0x000000FC
336 #define IFC_NAND_FIR1_OP9_SHIFT 2 347 #define IFC_NAND_FIR1_OP9_SHIFT 2
337 #define IFC_NAND_FIR2_OP10 0xFC00 348 #define IFC_NAND_FIR2_OP10 0xFC000000
338 #define IFC_NAND_FIR2_OP10_SHIFT 26 349 #define IFC_NAND_FIR2_OP10_SHIFT 26
339 #define IFC_NAND_FIR2_OP11 0x03F0 350 #define IFC_NAND_FIR2_OP11 0x03F00000
340 #define IFC_NAND_FIR2_OP11_SHIFT 20 351 #define IFC_NAND_FIR2_OP11_SHIFT 20
341 #define IFC_NAND_FIR2_OP12 0x000F 352 #define IFC_NAND_FIR2_OP12 0x000FC000
342 #define IFC_NAND_FIR2_OP12_SHIFT 14 353 #define IFC_NAND_FIR2_OP12_SHIFT 14
343 #define IFC_NAND_FIR2_OP13 0x0000 354 #define IFC_NAND_FIR2_OP13 0x00003F00
344 #define IFC_NAND_FIR2_OP13_SHIFT 8 355 #define IFC_NAND_FIR2_OP13_SHIFT 8
345 #define IFC_NAND_FIR2_OP14 0x0000 356 #define IFC_NAND_FIR2_OP14 0x000000FC
346 #define IFC_NAND_FIR2_OP14_SHIFT 2 357 #define IFC_NAND_FIR2_OP14_SHIFT 2
347 358
348 /* 359 /*
349 * Instruction opcodes to be programmed 360 * Instruction opcodes to be programmed
350 * in FIR registers- 6bits 361 * in FIR registers- 6bits
351 */ 362 */
352 enum ifc_nand_fir_opcodes { 363 enum ifc_nand_fir_opcodes {
353 IFC_FIR_OP_NOP, 364 IFC_FIR_OP_NOP,
354 IFC_FIR_OP_CA0, 365 IFC_FIR_OP_CA0,
355 IFC_FIR_OP_CA1, 366 IFC_FIR_OP_CA1,
356 IFC_FIR_OP_CA2, 367 IFC_FIR_OP_CA2,
357 IFC_FIR_OP_CA3, 368 IFC_FIR_OP_CA3,
358 IFC_FIR_OP_RA0, 369 IFC_FIR_OP_RA0,
359 IFC_FIR_OP_RA1, 370 IFC_FIR_OP_RA1,
360 IFC_FIR_OP_RA2, 371 IFC_FIR_OP_RA2,
361 IFC_FIR_OP_RA3, 372 IFC_FIR_OP_RA3,
362 IFC_FIR_OP_CMD0, 373 IFC_FIR_OP_CMD0,
363 IFC_FIR_OP_CMD1, 374 IFC_FIR_OP_CMD1,
364 IFC_FIR_OP_CMD2, 375 IFC_FIR_OP_CMD2,
365 IFC_FIR_OP_CMD3, 376 IFC_FIR_OP_CMD3,
366 IFC_FIR_OP_CMD4, 377 IFC_FIR_OP_CMD4,
367 IFC_FIR_OP_CMD5, 378 IFC_FIR_OP_CMD5,
368 IFC_FIR_OP_CMD6, 379 IFC_FIR_OP_CMD6,
369 IFC_FIR_OP_CMD7, 380 IFC_FIR_OP_CMD7,
370 IFC_FIR_OP_CW0, 381 IFC_FIR_OP_CW0,
371 IFC_FIR_OP_CW1, 382 IFC_FIR_OP_CW1,
372 IFC_FIR_OP_CW2, 383 IFC_FIR_OP_CW2,
373 IFC_FIR_OP_CW3, 384 IFC_FIR_OP_CW3,
374 IFC_FIR_OP_CW4, 385 IFC_FIR_OP_CW4,
375 IFC_FIR_OP_CW5, 386 IFC_FIR_OP_CW5,
376 IFC_FIR_OP_CW6, 387 IFC_FIR_OP_CW6,
377 IFC_FIR_OP_CW7, 388 IFC_FIR_OP_CW7,
378 IFC_FIR_OP_WBCD, 389 IFC_FIR_OP_WBCD,
379 IFC_FIR_OP_RBCD, 390 IFC_FIR_OP_RBCD,
380 IFC_FIR_OP_BTRD, 391 IFC_FIR_OP_BTRD,
381 IFC_FIR_OP_RDSTAT, 392 IFC_FIR_OP_RDSTAT,
382 IFC_FIR_OP_NWAIT, 393 IFC_FIR_OP_NWAIT,
383 IFC_FIR_OP_WFR, 394 IFC_FIR_OP_WFR,
384 IFC_FIR_OP_SBRD, 395 IFC_FIR_OP_SBRD,
385 IFC_FIR_OP_UA, 396 IFC_FIR_OP_UA,
386 IFC_FIR_OP_RB, 397 IFC_FIR_OP_RB,
387 }; 398 };
388 399
389 /* 400 /*
390 * NAND Chip Select Register (NAND_CSEL) 401 * NAND Chip Select Register (NAND_CSEL)
391 */ 402 */
392 #define IFC_NAND_CSEL 0x0C00 403 #define IFC_NAND_CSEL 0x0C000000
393 #define IFC_NAND_CSEL_SHIFT 26 404 #define IFC_NAND_CSEL_SHIFT 26
394 #define IFC_NAND_CSEL_CS0 0x0000 405 #define IFC_NAND_CSEL_CS0 0x00000000
395 #define IFC_NAND_CSEL_CS1 0x0400 406 #define IFC_NAND_CSEL_CS1 0x04000000
396 #define IFC_NAND_CSEL_CS2 0x0800 407 #define IFC_NAND_CSEL_CS2 0x08000000
397 #define IFC_NAND_CSEL_CS3 0x0C00 408 #define IFC_NAND_CSEL_CS3 0x0C000000
398 409
399 /* 410 /*
400 * NAND Operation Sequence Start (NANDSEQ_STRT 411 * NAND Operation Sequence Start (NANDSEQ_STRT)
401 */ 412 */
402 /* NAND Flash Operation Start */ 413 /* NAND Flash Operation Start */
403 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x8000 414 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
404 /* Automatic Erase */ 415 /* Automatic Erase */
405 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x0080 416 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
406 /* Automatic Program */ 417 /* Automatic Program */
407 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x0010 418 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
408 /* Automatic Copyback */ 419 /* Automatic Copyback */
409 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x0002 420 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
410 /* Automatic Read Operation */ 421 /* Automatic Read Operation */
411 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x0000 422 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
412 /* Automatic Status Read */ 423 /* Automatic Status Read */
413 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x0000 424 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
414 425
415 /* 426 /*
416 * NAND Event and Error Status Register (NAND_ 427 * NAND Event and Error Status Register (NAND_EVTER_STAT)
417 */ 428 */
418 /* Operation Complete */ 429 /* Operation Complete */
419 #define IFC_NAND_EVTER_STAT_OPC 0x8000 430 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
420 /* Flash Timeout Error */ 431 /* Flash Timeout Error */
421 #define IFC_NAND_EVTER_STAT_FTOER 0x0800 432 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
422 /* Write Protect Error */ 433 /* Write Protect Error */
423 #define IFC_NAND_EVTER_STAT_WPER 0x0400 434 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
424 /* ECC Error */ 435 /* ECC Error */
425 #define IFC_NAND_EVTER_STAT_ECCER 0x0200 436 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
426 /* RCW Load Done */ 437 /* RCW Load Done */
427 #define IFC_NAND_EVTER_STAT_RCW_DN 0x0000 438 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
428 /* Boot Loadr Done */ 439 /* Boot Loadr Done */
429 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x0000 440 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
430 /* Bad Block Indicator search select */ 441 /* Bad Block Indicator search select */
431 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x0000 442 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
432 443
433 /* 444 /*
434 * NAND Flash Page Read Completion Event Statu 445 * NAND Flash Page Read Completion Event Status Register
435 * (PGRDCMPL_EVT_STAT) 446 * (PGRDCMPL_EVT_STAT)
436 */ 447 */
437 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF 448 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
438 /* Small Page 0-15 Done */ 449 /* Small Page 0-15 Done */
439 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << 450 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
440 /* Large Page(2K) 0-3 Done */ 451 /* Large Page(2K) 0-3 Done */
441 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF < 452 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
442 /* Large Page(4K) 0-1 Done */ 453 /* Large Page(4K) 0-1 Done */
443 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF 454 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
444 455
445 /* 456 /*
446 * NAND Event and Error Enable Register (NAND_ 457 * NAND Event and Error Enable Register (NAND_EVTER_EN)
447 */ 458 */
448 /* Operation complete event enable */ 459 /* Operation complete event enable */
449 #define IFC_NAND_EVTER_EN_OPC_EN 0x8000 460 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
450 /* Page read complete event enable */ 461 /* Page read complete event enable */
451 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x2000 462 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
452 /* Flash Timeout error enable */ 463 /* Flash Timeout error enable */
453 #define IFC_NAND_EVTER_EN_FTOER_EN 0x0800 464 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
454 /* Write Protect error enable */ 465 /* Write Protect error enable */
455 #define IFC_NAND_EVTER_EN_WPER_EN 0x0400 466 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
456 /* ECC error logging enable */ 467 /* ECC error logging enable */
457 #define IFC_NAND_EVTER_EN_ECCER_EN 0x0200 468 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
458 469
459 /* 470 /*
460 * NAND Event and Error Interrupt Enable Regis 471 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
461 */ 472 */
462 /* Enable interrupt for operation complete */ 473 /* Enable interrupt for operation complete */
463 #define IFC_NAND_EVTER_INTR_OPCIR_EN 474 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
464 /* Enable interrupt for Page read complete */ 475 /* Enable interrupt for Page read complete */
465 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 476 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
466 /* Enable interrupt for Flash timeout error */ 477 /* Enable interrupt for Flash timeout error */
467 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 478 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
468 /* Enable interrupt for Write protect error */ 479 /* Enable interrupt for Write protect error */
469 #define IFC_NAND_EVTER_INTR_WPERIR_EN 480 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
470 /* Enable interrupt for ECC error*/ 481 /* Enable interrupt for ECC error*/
471 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 482 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
472 483
473 /* 484 /*
474 * NAND Transfer Error Attribute Register-0 (N 485 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
475 */ 486 */
476 #define IFC_NAND_ERATTR0_MASK 0x0C08 487 #define IFC_NAND_ERATTR0_MASK 0x0C080000
477 /* Error on CS0-3 for NAND */ 488 /* Error on CS0-3 for NAND */
478 #define IFC_NAND_ERATTR0_ERCS_CS0 0x0000 489 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
479 #define IFC_NAND_ERATTR0_ERCS_CS1 0x0400 490 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
480 #define IFC_NAND_ERATTR0_ERCS_CS2 0x0800 491 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
481 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C00 492 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
482 /* Transaction type of error Read/Write */ 493 /* Transaction type of error Read/Write */
483 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x0008 494 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
484 495
485 /* 496 /*
486 * NAND Flash Status Register (NAND_FSR) 497 * NAND Flash Status Register (NAND_FSR)
487 */ 498 */
488 /* First byte of data read from read status op 499 /* First byte of data read from read status op */
489 #define IFC_NAND_NFSR_RS0 0xFF00 500 #define IFC_NAND_NFSR_RS0 0xFF000000
490 /* Second byte of data read from read status o 501 /* Second byte of data read from read status op */
491 #define IFC_NAND_NFSR_RS1 0x00FF 502 #define IFC_NAND_NFSR_RS1 0x00FF0000
492 503
493 /* 504 /*
494 * ECC Error Status Registers (ECCSTAT0-ECCSTA 505 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
495 */ 506 */
496 /* Number of ECC errors on sector n (n = 0-15) 507 /* Number of ECC errors on sector n (n = 0-15) */
497 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 508 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
498 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 509 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
499 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 510 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
500 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 511 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
501 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 512 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
502 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 513 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
503 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 514 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
504 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 515 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
505 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 516 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
506 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 517 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
507 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 518 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
508 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 519 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
509 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 520 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
510 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 521 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
511 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 522 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
512 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 523 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
513 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 524 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
514 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 525 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
515 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 526 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
516 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 527 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
517 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 528 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
518 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIF 529 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
519 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 530 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
520 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIF 531 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
521 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 532 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
522 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIF 533 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
523 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 534 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
524 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIF 535 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
525 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 536 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
526 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIF 537 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
527 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 538 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
528 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIF 539 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
529 540
530 /* 541 /*
531 * NAND Control Register (NANDCR) 542 * NAND Control Register (NANDCR)
532 */ 543 */
533 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E00 544 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
534 #define IFC_NAND_NCR_FTOCNT_SHIFT 25 545 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
535 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 546 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
536 547
537 /* 548 /*
538 * NAND_AUTOBOOT_TRGR 549 * NAND_AUTOBOOT_TRGR
539 */ 550 */
540 /* Trigger RCW load */ 551 /* Trigger RCW load */
541 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x8000 552 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
542 /* Trigget Auto Boot */ 553 /* Trigget Auto Boot */
543 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x2000 554 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
544 555
545 /* 556 /*
546 * NAND_MDR 557 * NAND_MDR
547 */ 558 */
548 /* 1st read data byte when opcode SBRD */ 559 /* 1st read data byte when opcode SBRD */
549 #define IFC_NAND_MDR_RDATA0 0xFF00 560 #define IFC_NAND_MDR_RDATA0 0xFF000000
550 /* 2nd read data byte when opcode SBRD */ 561 /* 2nd read data byte when opcode SBRD */
551 #define IFC_NAND_MDR_RDATA1 0x00FF 562 #define IFC_NAND_MDR_RDATA1 0x00FF0000
552 563
553 /* 564 /*
554 * NOR Machine Specific Registers 565 * NOR Machine Specific Registers
555 */ 566 */
556 /* 567 /*
557 * NOR Event and Error Status Register (NOR_EV 568 * NOR Event and Error Status Register (NOR_EVTER_STAT)
558 */ 569 */
559 /* NOR Command Sequence Operation Complete */ 570 /* NOR Command Sequence Operation Complete */
560 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x8000 571 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
561 /* Write Protect Error */ 572 /* Write Protect Error */
562 #define IFC_NOR_EVTER_STAT_WPER 0x0400 573 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
563 /* Command Sequence Timeout Error */ 574 /* Command Sequence Timeout Error */
564 #define IFC_NOR_EVTER_STAT_STOER 0x0100 575 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
565 576
566 /* 577 /*
567 * NOR Event and Error Enable Register (NOR_EV 578 * NOR Event and Error Enable Register (NOR_EVTER_EN)
568 */ 579 */
569 /* NOR Command Seq complete event enable */ 580 /* NOR Command Seq complete event enable */
570 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x8000 581 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
571 /* Write Protect Error Checking Enable */ 582 /* Write Protect Error Checking Enable */
572 #define IFC_NOR_EVTER_EN_WPEREN 0x0400 583 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
573 /* Timeout Error Enable */ 584 /* Timeout Error Enable */
574 #define IFC_NOR_EVTER_EN_STOEREN 0x0100 585 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
575 586
576 /* 587 /*
577 * NOR Event and Error Interrupt Enable Regist 588 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
578 */ 589 */
579 /* Enable interrupt for OPC complete */ 590 /* Enable interrupt for OPC complete */
580 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x8000 591 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
581 /* Enable interrupt for write protect error */ 592 /* Enable interrupt for write protect error */
582 #define IFC_NOR_EVTER_INTR_WPEREN 0x0400 593 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
583 /* Enable interrupt for timeout error */ 594 /* Enable interrupt for timeout error */
584 #define IFC_NOR_EVTER_INTR_STOEREN 0x0100 595 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
585 596
586 /* 597 /*
587 * NOR Transfer Error Attribute Register-0 (NO 598 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
588 */ 599 */
589 /* Source ID for error transaction */ 600 /* Source ID for error transaction */
590 #define IFC_NOR_ERATTR0_ERSRCID 0xFF00 601 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
591 /* AXI ID for error transation */ 602 /* AXI ID for error transation */
592 #define IFC_NOR_ERATTR0_ERAID 0x000F 603 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
593 /* Chip select corresponds to NOR error */ 604 /* Chip select corresponds to NOR error */
594 #define IFC_NOR_ERATTR0_ERCS_CS0 0x0000 605 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
595 #define IFC_NOR_ERATTR0_ERCS_CS1 0x0000 606 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
596 #define IFC_NOR_ERATTR0_ERCS_CS2 0x0000 607 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
597 #define IFC_NOR_ERATTR0_ERCS_CS3 0x0000 608 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
598 /* Type of transaction read/write */ 609 /* Type of transaction read/write */
599 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x0000 610 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
600 611
601 /* 612 /*
602 * NOR Transfer Error Attribute Register-2 (NO 613 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
603 */ 614 */
604 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 615 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
605 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 616 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
606 617
607 /* 618 /*
608 * NOR Control Register (NORCR) 619 * NOR Control Register (NORCR)
609 */ 620 */
610 #define IFC_NORCR_MASK 0x0F0F 621 #define IFC_NORCR_MASK 0x0F0F0000
611 /* No. of Address/Data Phase */ 622 /* No. of Address/Data Phase */
612 #define IFC_NORCR_NUM_PHASE_MASK 0x0F00 623 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
613 #define IFC_NORCR_NUM_PHASE_SHIFT 24 624 #define IFC_NORCR_NUM_PHASE_SHIFT 24
614 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_ 625 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
615 /* Sequence Timeout Count */ 626 /* Sequence Timeout Count */
616 #define IFC_NORCR_STOCNT_MASK 0x000F 627 #define IFC_NORCR_STOCNT_MASK 0x000F0000
617 #define IFC_NORCR_STOCNT_SHIFT 16 628 #define IFC_NORCR_STOCNT_SHIFT 16
618 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 629 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
619 630
620 /* 631 /*
621 * GPCM Machine specific registers 632 * GPCM Machine specific registers
622 */ 633 */
623 /* 634 /*
624 * GPCM Event and Error Status Register (GPCM_ 635 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
625 */ 636 */
626 /* Timeout error */ 637 /* Timeout error */
627 #define IFC_GPCM_EVTER_STAT_TOER 0x0400 638 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
628 /* Parity error */ 639 /* Parity error */
629 #define IFC_GPCM_EVTER_STAT_PER 0x0100 640 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
630 641
631 /* 642 /*
632 * GPCM Event and Error Enable Register (GPCM_ 643 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
633 */ 644 */
634 /* Timeout error enable */ 645 /* Timeout error enable */
635 #define IFC_GPCM_EVTER_EN_TOER_EN 0x0400 646 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
636 /* Parity error enable */ 647 /* Parity error enable */
637 #define IFC_GPCM_EVTER_EN_PER_EN 0x0100 648 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
638 649
639 /* 650 /*
640 * GPCM Event and Error Interrupt Enable Regis 651 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
641 */ 652 */
642 /* Enable Interrupt for timeout error */ 653 /* Enable Interrupt for timeout error */
643 #define IFC_GPCM_EEIER_TOERIR_EN 0x0400 654 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
644 /* Enable Interrupt for Parity error */ 655 /* Enable Interrupt for Parity error */
645 #define IFC_GPCM_EEIER_PERIR_EN 0x0100 656 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
646 657
647 /* 658 /*
648 * GPCM Transfer Error Attribute Register-0 (G 659 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
649 */ 660 */
650 /* Source ID for error transaction */ 661 /* Source ID for error transaction */
651 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF00 662 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
652 /* AXI ID for error transaction */ 663 /* AXI ID for error transaction */
653 #define IFC_GPCM_ERATTR0_ERAID 0x000F 664 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
654 /* Chip select corresponds to GPCM error */ 665 /* Chip select corresponds to GPCM error */
655 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x0000 666 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
656 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x0000 667 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
657 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x0000 668 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
658 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x0000 669 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
659 /* Type of transaction read/Write */ 670 /* Type of transaction read/Write */
660 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x0000 671 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
661 672
662 /* 673 /*
663 * GPCM Transfer Error Attribute Register-2 (G 674 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
664 */ 675 */
665 /* On which beat of address/data parity error 676 /* On which beat of address/data parity error is observed */
666 #define IFC_GPCM_ERATTR2_PERR_BEAT 677 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
667 /* Parity Error on byte */ 678 /* Parity Error on byte */
668 #define IFC_GPCM_ERATTR2_PERR_BYTE 679 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
669 /* Parity Error reported in addr or data phase 680 /* Parity Error reported in addr or data phase */
670 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 681 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
671 682
672 /* 683 /*
673 * GPCM Status Register (GPCM_STAT) 684 * GPCM Status Register (GPCM_STAT)
674 */ 685 */
675 #define IFC_GPCM_STAT_BSY 0x8000 686 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
676 687
677 /* 688 /*
678 * IFC Controller NAND Machine registers 689 * IFC Controller NAND Machine registers
679 */ 690 */
680 struct fsl_ifc_nand { 691 struct fsl_ifc_nand {
681 __be32 ncfgr; 692 __be32 ncfgr;
682 u32 res1[0x4]; 693 u32 res1[0x4];
683 __be32 nand_fcr0; 694 __be32 nand_fcr0;
684 __be32 nand_fcr1; 695 __be32 nand_fcr1;
685 u32 res2[0x8]; 696 u32 res2[0x8];
686 __be32 row0; 697 __be32 row0;
687 u32 res3; 698 u32 res3;
688 __be32 col0; 699 __be32 col0;
689 u32 res4; 700 u32 res4;
690 __be32 row1; 701 __be32 row1;
691 u32 res5; 702 u32 res5;
692 __be32 col1; 703 __be32 col1;
693 u32 res6; 704 u32 res6;
694 __be32 row2; 705 __be32 row2;
695 u32 res7; 706 u32 res7;
696 __be32 col2; 707 __be32 col2;
697 u32 res8; 708 u32 res8;
698 __be32 row3; 709 __be32 row3;
699 u32 res9; 710 u32 res9;
700 __be32 col3; 711 __be32 col3;
701 u32 res10[0x24]; 712 u32 res10[0x24];
702 __be32 nand_fbcr; 713 __be32 nand_fbcr;
703 u32 res11; 714 u32 res11;
704 __be32 nand_fir0; 715 __be32 nand_fir0;
705 __be32 nand_fir1; 716 __be32 nand_fir1;
706 __be32 nand_fir2; 717 __be32 nand_fir2;
707 u32 res12[0x10]; 718 u32 res12[0x10];
708 __be32 nand_csel; 719 __be32 nand_csel;
709 u32 res13; 720 u32 res13;
710 __be32 nandseq_strt; 721 __be32 nandseq_strt;
711 u32 res14; 722 u32 res14;
712 __be32 nand_evter_stat; 723 __be32 nand_evter_stat;
713 u32 res15; 724 u32 res15;
714 __be32 pgrdcmpl_evt_stat; 725 __be32 pgrdcmpl_evt_stat;
715 u32 res16[0x2]; 726 u32 res16[0x2];
716 __be32 nand_evter_en; 727 __be32 nand_evter_en;
717 u32 res17[0x2]; 728 u32 res17[0x2];
718 __be32 nand_evter_intr_en; 729 __be32 nand_evter_intr_en;
719 __be32 nand_vol_addr_stat; 730 __be32 nand_vol_addr_stat;
720 u32 res18; 731 u32 res18;
721 __be32 nand_erattr0; 732 __be32 nand_erattr0;
722 __be32 nand_erattr1; 733 __be32 nand_erattr1;
723 u32 res19[0x10]; 734 u32 res19[0x10];
724 __be32 nand_fsr; 735 __be32 nand_fsr;
725 u32 res20; 736 u32 res20;
726 __be32 nand_eccstat[8]; 737 __be32 nand_eccstat[8];
727 u32 res21[0x1c]; 738 u32 res21[0x1c];
728 __be32 nanndcr; 739 __be32 nanndcr;
729 u32 res22[0x2]; 740 u32 res22[0x2];
730 __be32 nand_autoboot_trgr; 741 __be32 nand_autoboot_trgr;
731 u32 res23; 742 u32 res23;
732 __be32 nand_mdr; 743 __be32 nand_mdr;
733 u32 res24[0x1C]; 744 u32 res24[0x1C];
734 __be32 nand_dll_lowcfg0; 745 __be32 nand_dll_lowcfg0;
735 __be32 nand_dll_lowcfg1; 746 __be32 nand_dll_lowcfg1;
736 u32 res25; 747 u32 res25;
737 __be32 nand_dll_lowstat; 748 __be32 nand_dll_lowstat;
738 u32 res26[0x3c]; 749 u32 res26[0x3c];
739 }; 750 };
740 751
741 /* 752 /*
742 * IFC controller NOR Machine registers 753 * IFC controller NOR Machine registers
743 */ 754 */
744 struct fsl_ifc_nor { 755 struct fsl_ifc_nor {
745 __be32 nor_evter_stat; 756 __be32 nor_evter_stat;
746 u32 res1[0x2]; 757 u32 res1[0x2];
747 __be32 nor_evter_en; 758 __be32 nor_evter_en;
748 u32 res2[0x2]; 759 u32 res2[0x2];
749 __be32 nor_evter_intr_en; 760 __be32 nor_evter_intr_en;
750 u32 res3[0x2]; 761 u32 res3[0x2];
751 __be32 nor_erattr0; 762 __be32 nor_erattr0;
752 __be32 nor_erattr1; 763 __be32 nor_erattr1;
753 __be32 nor_erattr2; 764 __be32 nor_erattr2;
754 u32 res4[0x4]; 765 u32 res4[0x4];
755 __be32 norcr; 766 __be32 norcr;
756 u32 res5[0xEF]; 767 u32 res5[0xEF];
757 }; 768 };
758 769
759 /* 770 /*
760 * IFC controller GPCM Machine registers 771 * IFC controller GPCM Machine registers
761 */ 772 */
762 struct fsl_ifc_gpcm { 773 struct fsl_ifc_gpcm {
763 __be32 gpcm_evter_stat; 774 __be32 gpcm_evter_stat;
764 u32 res1[0x2]; 775 u32 res1[0x2];
765 __be32 gpcm_evter_en; 776 __be32 gpcm_evter_en;
766 u32 res2[0x2]; 777 u32 res2[0x2];
767 __be32 gpcm_evter_intr_en; 778 __be32 gpcm_evter_intr_en;
768 u32 res3[0x2]; 779 u32 res3[0x2];
769 __be32 gpcm_erattr0; 780 __be32 gpcm_erattr0;
770 __be32 gpcm_erattr1; 781 __be32 gpcm_erattr1;
771 __be32 gpcm_erattr2; 782 __be32 gpcm_erattr2;
772 __be32 gpcm_stat; 783 __be32 gpcm_stat;
773 }; 784 };
774 785
775 /* 786 /*
776 * IFC Controller Registers 787 * IFC Controller Registers
777 */ 788 */
778 struct fsl_ifc_global { 789 struct fsl_ifc_global {
779 __be32 ifc_rev; 790 __be32 ifc_rev;
780 u32 res1[0x2]; 791 u32 res1[0x2];
781 struct { 792 struct {
782 __be32 cspr_ext; 793 __be32 cspr_ext;
783 __be32 cspr; 794 __be32 cspr;
784 u32 res2; 795 u32 res2;
785 } cspr_cs[FSL_IFC_BANK_COUNT]; 796 } cspr_cs[FSL_IFC_BANK_COUNT];
786 u32 res3[0xd]; 797 u32 res3[0xd];
787 struct { 798 struct {
788 __be32 amask; 799 __be32 amask;
789 u32 res4[0x2]; 800 u32 res4[0x2];
790 } amask_cs[FSL_IFC_BANK_COUNT]; 801 } amask_cs[FSL_IFC_BANK_COUNT];
791 u32 res5[0xc]; 802 u32 res5[0xc];
792 struct { 803 struct {
793 __be32 csor; 804 __be32 csor;
794 __be32 csor_ext; 805 __be32 csor_ext;
795 u32 res6; 806 u32 res6;
796 } csor_cs[FSL_IFC_BANK_COUNT]; 807 } csor_cs[FSL_IFC_BANK_COUNT];
797 u32 res7[0xc]; 808 u32 res7[0xc];
798 struct { 809 struct {
799 __be32 ftim[4]; 810 __be32 ftim[4];
800 u32 res8[0x8]; 811 u32 res8[0x8];
801 } ftim_cs[FSL_IFC_BANK_COUNT]; 812 } ftim_cs[FSL_IFC_BANK_COUNT];
802 u32 res9[0x30]; 813 u32 res9[0x30];
803 __be32 rb_stat; 814 __be32 rb_stat;
804 __be32 rb_map; 815 __be32 rb_map;
805 __be32 wb_map; 816 __be32 wb_map;
806 __be32 ifc_gcr; 817 __be32 ifc_gcr;
807 u32 res10[0x2]; 818 u32 res10[0x2];
808 __be32 cm_evter_stat; 819 __be32 cm_evter_stat;
809 u32 res11[0x2]; 820 u32 res11[0x2];
810 __be32 cm_evter_en; 821 __be32 cm_evter_en;
811 u32 res12[0x2]; 822 u32 res12[0x2];
812 __be32 cm_evter_intr_en; 823 __be32 cm_evter_intr_en;
813 u32 res13[0x2]; 824 u32 res13[0x2];
814 __be32 cm_erattr0; 825 __be32 cm_erattr0;
815 __be32 cm_erattr1; 826 __be32 cm_erattr1;
816 u32 res14[0x2]; 827 u32 res14[0x2];
817 __be32 ifc_ccr; 828 __be32 ifc_ccr;
818 __be32 ifc_csr; 829 __be32 ifc_csr;
819 __be32 ddr_ccr_low; 830 __be32 ddr_ccr_low;
820 }; 831 };
821 832
822 833
823 struct fsl_ifc_runtime { 834 struct fsl_ifc_runtime {
824 struct fsl_ifc_nand ifc_nand; 835 struct fsl_ifc_nand ifc_nand;
825 struct fsl_ifc_nor ifc_nor; 836 struct fsl_ifc_nor ifc_nor;
826 struct fsl_ifc_gpcm ifc_gpcm; 837 struct fsl_ifc_gpcm ifc_gpcm;
827 }; 838 };
828 839
829 extern unsigned int convert_ifc_address(phys_a 840 extern unsigned int convert_ifc_address(phys_addr_t addr_base);
830 extern int fsl_ifc_find(phys_addr_t addr_base) 841 extern int fsl_ifc_find(phys_addr_t addr_base);
831 842
832 /* overview of the fsl ifc controller */ 843 /* overview of the fsl ifc controller */
833 844
834 struct fsl_ifc_ctrl { 845 struct fsl_ifc_ctrl {
835 /* device info */ 846 /* device info */
836 struct device *dev; 847 struct device *dev;
837 struct fsl_ifc_global __iomem *gregs 848 struct fsl_ifc_global __iomem *gregs;
838 struct fsl_ifc_runtime __iomem *rregs 849 struct fsl_ifc_runtime __iomem *rregs;
839 int irq; 850 int irq;
840 int nand_i 851 int nand_irq;
841 spinlock_t lock; 852 spinlock_t lock;
842 void *nand; 853 void *nand;
843 int versio 854 int version;
844 int banks; 855 int banks;
845 856
846 u32 nand_stat; 857 u32 nand_stat;
847 wait_queue_head_t nand_wait; 858 wait_queue_head_t nand_wait;
848 bool little_endian; 859 bool little_endian;
849 }; 860 };
850 861
851 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; 862 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
852 863
853 static inline u32 ifc_in32(void __iomem *addr) 864 static inline u32 ifc_in32(void __iomem *addr)
854 { 865 {
855 u32 val; 866 u32 val;
856 867
857 if (fsl_ifc_ctrl_dev->little_endian) 868 if (fsl_ifc_ctrl_dev->little_endian)
858 val = ioread32(addr); 869 val = ioread32(addr);
859 else 870 else
860 val = ioread32be(addr); 871 val = ioread32be(addr);
861 872
862 return val; 873 return val;
863 } 874 }
864 875
865 static inline u16 ifc_in16(void __iomem *addr) 876 static inline u16 ifc_in16(void __iomem *addr)
866 { 877 {
867 u16 val; 878 u16 val;
868 879
869 if (fsl_ifc_ctrl_dev->little_endian) 880 if (fsl_ifc_ctrl_dev->little_endian)
870 val = ioread16(addr); 881 val = ioread16(addr);
871 else 882 else
872 val = ioread16be(addr); 883 val = ioread16be(addr);
873 884
874 return val; 885 return val;
875 } 886 }
876 887
877 static inline u8 ifc_in8(void __iomem *addr) 888 static inline u8 ifc_in8(void __iomem *addr)
878 { 889 {
879 return ioread8(addr); 890 return ioread8(addr);
880 } 891 }
881 892
882 static inline void ifc_out32(u32 val, void __i 893 static inline void ifc_out32(u32 val, void __iomem *addr)
883 { 894 {
884 if (fsl_ifc_ctrl_dev->little_endian) 895 if (fsl_ifc_ctrl_dev->little_endian)
885 iowrite32(val, addr); 896 iowrite32(val, addr);
886 else 897 else
887 iowrite32be(val, addr); 898 iowrite32be(val, addr);
888 } 899 }
889 900
890 static inline void ifc_out16(u16 val, void __i 901 static inline void ifc_out16(u16 val, void __iomem *addr)
891 { 902 {
892 if (fsl_ifc_ctrl_dev->little_endian) 903 if (fsl_ifc_ctrl_dev->little_endian)
893 iowrite16(val, addr); 904 iowrite16(val, addr);
894 else 905 else
895 iowrite16be(val, addr); 906 iowrite16be(val, addr);
896 } 907 }
897 908
898 static inline void ifc_out8(u8 val, void __iom 909 static inline void ifc_out8(u8 val, void __iomem *addr)
899 { 910 {
900 iowrite8(val, addr); 911 iowrite8(val, addr);
901 } 912 }
902 913
903 #endif /* __ASM_FSL_IFC_H */ 914 #endif /* __ASM_FSL_IFC_H */
904 915
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.