1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * ADF4350/ADF4351 SPI PLL driver
4 *
5 * Copyright 2012-2013 Analog Devices Inc.
6 */
7
8 #ifndef IIO_PLL_ADF4350_H_
9 #define IIO_PLL_ADF4350_H_
10
11 /* Registers */
12 #define ADF4350_REG0 0
13 #define ADF4350_REG1 1
14 #define ADF4350_REG2 2
15 #define ADF4350_REG3 3
16 #define ADF4350_REG4 4
17 #define ADF4350_REG5 5
18
19 /* REG0 Bit Definitions */
20 #define ADF4350_REG0_FRACT(x)
21 #define ADF4350_REG0_INT(x)
22
23 /* REG1 Bit Definitions */
24 #define ADF4350_REG1_MOD(x)
25 #define ADF4350_REG1_PHASE(x)
26 #define ADF4350_REG1_PRESCALER
27
28 /* REG2 Bit Definitions */
29 #define ADF4350_REG2_COUNTER_RESET_EN
30 #define ADF4350_REG2_CP_THREESTATE_EN
31 #define ADF4350_REG2_POWER_DOWN_EN
32 #define ADF4350_REG2_PD_POLARITY_POS
33 #define ADF4350_REG2_LDP_6ns
34 #define ADF4350_REG2_LDP_10ns
35 #define ADF4350_REG2_LDF_FRACT_N
36 #define ADF4350_REG2_LDF_INT_N
37 #define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x)
38 #define ADF4350_REG2_DOUBLE_BUFF_EN
39 #define ADF4350_REG2_10BIT_R_CNT(x)
40 #define ADF4350_REG2_RDIV2_EN
41 #define ADF4350_REG2_RMULT2_EN
42 #define ADF4350_REG2_MUXOUT(x)
43 #define ADF4350_REG2_NOISE_MODE(x)
44 #define ADF4350_MUXOUT_THREESTATE
45 #define ADF4350_MUXOUT_DVDD
46 #define ADF4350_MUXOUT_GND
47 #define ADF4350_MUXOUT_R_DIV_OUT
48 #define ADF4350_MUXOUT_N_DIV_OUT
49 #define ADF4350_MUXOUT_ANALOG_LOCK_DETECT
50 #define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT
51
52 /* REG3 Bit Definitions */
53 #define ADF4350_REG3_12BIT_CLKDIV(x)
54 #define ADF4350_REG3_12BIT_CLKDIV_MODE(x)
55 #define ADF4350_REG3_12BIT_CSR_EN
56 #define ADF4351_REG3_CHARGE_CANCELLATION_EN
57 #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN
58 #define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH
59
60 /* REG4 Bit Definitions */
61 #define ADF4350_REG4_OUTPUT_PWR(x)
62 #define ADF4350_REG4_RF_OUT_EN
63 #define ADF4350_REG4_AUX_OUTPUT_PWR(x)
64 #define ADF4350_REG4_AUX_OUTPUT_EN
65 #define ADF4350_REG4_AUX_OUTPUT_FUND
66 #define ADF4350_REG4_AUX_OUTPUT_DIV
67 #define ADF4350_REG4_MUTE_TILL_LOCK_EN
68 #define ADF4350_REG4_VCO_PWRDOWN_EN
69 #define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x)
70 #define ADF4350_REG4_RF_DIV_SEL(x)
71 #define ADF4350_REG4_FEEDBACK_DIVIDED
72 #define ADF4350_REG4_FEEDBACK_FUND
73
74 /* REG5 Bit Definitions */
75 #define ADF4350_REG5_LD_PIN_MODE_LOW
76 #define ADF4350_REG5_LD_PIN_MODE_DIGITAL
77 #define ADF4350_REG5_LD_PIN_MODE_HIGH
78
79 /* Specifications */
80 #define ADF4350_MAX_OUT_FREQ 440000
81 #define ADF4350_MIN_OUT_FREQ 137500
82 #define ADF4351_MIN_OUT_FREQ 343750
83 #define ADF4350_MIN_VCO_FREQ 220000
84 #define ADF4350_MAX_FREQ_45_PRESC 300000
85 #define ADF4350_MAX_FREQ_PFD 320000
86 #define ADF4350_MAX_BANDSEL_CLK 125000
87 #define ADF4350_MAX_FREQ_REFIN 250000
88 #define ADF4350_MAX_MODULUS 4095
89 #define ADF4350_MAX_R_CNT 1023
90
91
92 /**
93 * struct adf4350_platform_data - platform spe
94 * @name: Optional device name.
95 * @clkin: REFin frequency in Hz.
96 * @channel_spacing: Channel spacing in Hz
97 * @power_up_frequency: Optional, If set in Hz
98 * frequency on probe.
99 * @ref_div_factor: Optional, if set the d
100 * and uses this default
101 * @ref_doubler_en: Enables reference doub
102 * @ref_div2_en: Enables reference divi
103 * @r2_user_settings: User defined settings
104 * @r3_user_settings: User defined settings
105 * @r4_user_settings: User defined settings
106 */
107
108 struct adf4350_platform_data {
109 char name[32];
110 unsigned long clkin;
111 unsigned long channel_spacin
112 unsigned long long power_up_frequ
113
114 unsigned short ref_div_factor
115 bool ref_doubler_en
116 bool ref_div2_en;
117
118 unsigned r2_user_settin
119 unsigned r3_user_settin
120 unsigned r4_user_settin
121 };
122
123 #endif /* IIO_PLL_ADF4350_H_ */
124
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