1 /* SPDX-License-Identifier: GPL-2.0 */ 1
2 #ifndef _INTEL_VSEC_H
3 #define _INTEL_VSEC_H
4
5 #include <linux/auxiliary_bus.h>
6 #include <linux/bits.h>
7
8 #define VSEC_CAP_TELEMETRY BIT(0)
9 #define VSEC_CAP_WATCHER BIT(1)
10 #define VSEC_CAP_CRASHLOG BIT(2)
11 #define VSEC_CAP_SDSI BIT(3)
12 #define VSEC_CAP_TPMI BIT(4)
13
14 /* Intel DVSEC offsets */
15 #define INTEL_DVSEC_ENTRIES 0xA
16 #define INTEL_DVSEC_SIZE 0xB
17 #define INTEL_DVSEC_TABLE 0xC
18 #define INTEL_DVSEC_TABLE_BAR(x) ((x) &
19 #define INTEL_DVSEC_TABLE_OFFSET(x) ((x) &
20 #define TABLE_OFFSET_SHIFT 3
21
22 struct pci_dev;
23 struct resource;
24
25 enum intel_vsec_id {
26 VSEC_ID_TELEMETRY = 2,
27 VSEC_ID_WATCHER = 3,
28 VSEC_ID_CRASHLOG = 4,
29 VSEC_ID_SDSI = 65,
30 VSEC_ID_TPMI = 66,
31 };
32
33 /**
34 * struct intel_vsec_header - Common fields of
35 * @rev: Revision ID of the VSEC/DVSEC
36 * @length: Length of the VSEC/DVSEC regi
37 * @id: ID of the feature
38 * @num_entries: Number of instances of the fe
39 * @entry_size: Size of the discovery table f
40 * @tbir: BAR containing the discovery
41 * @offset: BAR offset of start of the fi
42 */
43 struct intel_vsec_header {
44 u8 rev;
45 u16 length;
46 u16 id;
47 u8 num_entries;
48 u8 entry_size;
49 u8 tbir;
50 u32 offset;
51 };
52
53 enum intel_vsec_quirks {
54 /* Watcher feature not supported */
55 VSEC_QUIRK_NO_WATCHER = BIT(0),
56
57 /* Crashlog feature not supported */
58 VSEC_QUIRK_NO_CRASHLOG = BIT(1),
59
60 /* Use shift instead of mask to read d
61 VSEC_QUIRK_TABLE_SHIFT = BIT(2),
62
63 /* DVSEC not present (provided in driv
64 VSEC_QUIRK_NO_DVSEC = BIT(3),
65
66 /* Platforms requiring quirk in the au
67 VSEC_QUIRK_EARLY_HW = BIT(4),
68 };
69
70 /**
71 * struct pmt_callbacks - Callback infrastruct
72 * ->read_telem() when specified, called by cl
73 * of direct copy).
74 * @pdev: PCI device reference for the callba
75 * @guid: ID of data to acccss
76 * @data: buffer for the data to be copied
77 * @count: size of buffer
78 */
79 struct pmt_callbacks {
80 int (*read_telem)(struct pci_dev *pdev
81 };
82
83 /**
84 * struct intel_vsec_platform_info - Platform
85 * @parent: parent device in the auxbus cha
86 * @headers: list of headers to define the P
87 * @priv_data: private data, usable by parent
88 * @caps: bitmask of PMT capabilities for
89 * @quirks: bitmask of VSEC device quirks
90 * @base_addr: allow a base address to be spec
91 */
92 struct intel_vsec_platform_info {
93 struct device *parent;
94 struct intel_vsec_header **headers;
95 void *priv_data;
96 unsigned long caps;
97 unsigned long quirks;
98 u64 base_addr;
99 };
100
101 /**
102 * struct intel_sec_device - Auxbus specific d
103 * @auxdev: auxbus device struct for au
104 * @pcidev: pci device associated with
105 * @resource: any resources shared by the
106 * @ida: id reference
107 * @num_resources: number of resources
108 * @id: xarray id
109 * @priv_data: any private data needed
110 * @quirks: specified quirks
111 * @base_addr: base address of entries (if
112 */
113 struct intel_vsec_device {
114 struct auxiliary_device auxdev;
115 struct pci_dev *pcidev;
116 struct resource *resource;
117 struct ida *ida;
118 int num_resources;
119 int id; /* xa */
120 void *priv_data;
121 size_t priv_data_size;
122 unsigned long quirks;
123 u64 base_addr;
124 };
125
126 int intel_vsec_add_aux(struct pci_dev *pdev, s
127 struct intel_vsec_devic
128 const char *name);
129
130 static inline struct intel_vsec_device *dev_to
131 {
132 return container_of(dev, struct intel_
133 }
134
135 static inline struct intel_vsec_device *auxdev
136 {
137 return container_of(auxdev, struct int
138 }
139
140 #if IS_ENABLED(CONFIG_INTEL_VSEC)
141 void intel_vsec_register(struct pci_dev *pdev,
142 struct intel_vsec_pla
143 #else
144 static inline void intel_vsec_register(struct
145 struct
146 {
147 }
148 #endif
149 #endif
150
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