1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 3 * cs42l43 register definitions 4 * 5 * Copyright (c) 2022-2023 Cirrus Logic, Inc. 6 * Cirrus Logic Intern 7 */ 8 9 #ifndef CS42L43_CORE_REGS_H 10 #define CS42L43_CORE_REGS_H 11 12 /* Registers */ 13 #define CS42L43_GEN_INT_STAT_1 14 #define CS42L43_GEN_INT_MASK_1 15 #define CS42L43_DEVID 16 #define CS42L43_REVID 17 #define CS42L43_RELID 18 #define CS42L43_SFT_RESET 19 #define CS42L43_DRV_CTRL1 20 #define CS42L43_DRV_CTRL3 21 #define CS42L43_DRV_CTRL4 22 #define CS42L43_DRV_CTRL_5 23 #define CS42L43_GPIO_CTRL1 24 #define CS42L43_GPIO_CTRL2 25 #define CS42L43_GPIO_STS 26 #define CS42L43_GPIO_FN_SEL 27 #define CS42L43_MCLK_SRC_SEL 28 #define CS42L43_CCM_BLK_CLK_CONTROL 29 #define CS42L43_SAMPLE_RATE1 30 #define CS42L43_SAMPLE_RATE2 31 #define CS42L43_SAMPLE_RATE3 32 #define CS42L43_SAMPLE_RATE4 33 #define CS42L43_PLL_CONTROL 34 #define CS42L43_FS_SELECT1 35 #define CS42L43_FS_SELECT2 36 #define CS42L43_FS_SELECT3 37 #define CS42L43_FS_SELECT4 38 #define CS42L43_PDM_CONTROL 39 #define CS42L43_ASP_CLK_CONFIG1 40 #define CS42L43_ASP_CLK_CONFIG2 41 #define CS42L43_OSC_DIV_SEL 42 #define CS42L43_ADC_B_CTRL1 43 #define CS42L43_ADC_B_CTRL2 44 #define CS42L43_DECIM_HPF_WNF_CTRL1 45 #define CS42L43_DECIM_HPF_WNF_CTRL2 46 #define CS42L43_DECIM_HPF_WNF_CTRL3 47 #define CS42L43_DECIM_HPF_WNF_CTRL4 48 #define CS42L43_DMIC_PDM_CTRL 49 #define CS42L43_DECIM_VOL_CTRL_CH1_CH2 50 #define CS42L43_DECIM_VOL_CTRL_CH3_CH4 51 #define CS42L43_DECIM_VOL_CTRL_UPDATE 52 #define CS42L43_INTP_VOLUME_CTRL1 53 #define CS42L43_INTP_VOLUME_CTRL2 54 #define CS42L43_AMP1_2_VOL_RAMP 55 #define CS42L43_ASP_CTRL 56 #define CS42L43_ASP_FSYNC_CTRL1 57 #define CS42L43_ASP_FSYNC_CTRL2 58 #define CS42L43_ASP_FSYNC_CTRL3 59 #define CS42L43_ASP_FSYNC_CTRL4 60 #define CS42L43_ASP_DATA_CTRL 61 #define CS42L43_ASP_RX_EN 62 #define CS42L43_ASP_TX_EN 63 #define CS42L43_ASP_RX_CH1_CTRL 64 #define CS42L43_ASP_RX_CH2_CTRL 65 #define CS42L43_ASP_RX_CH3_CTRL 66 #define CS42L43_ASP_RX_CH4_CTRL 67 #define CS42L43_ASP_RX_CH5_CTRL 68 #define CS42L43_ASP_RX_CH6_CTRL 69 #define CS42L43_ASP_TX_CH1_CTRL 70 #define CS42L43_ASP_TX_CH2_CTRL 71 #define CS42L43_ASP_TX_CH3_CTRL 72 #define CS42L43_ASP_TX_CH4_CTRL 73 #define CS42L43_ASP_TX_CH5_CTRL 74 #define CS42L43_ASP_TX_CH6_CTRL 75 #define CS42L43_OTP_REVISION_ID 76 #define CS42L43_ASPTX1_INPUT 77 #define CS42L43_ASPTX2_INPUT 78 #define CS42L43_ASPTX3_INPUT 79 #define CS42L43_ASPTX4_INPUT 80 #define CS42L43_ASPTX5_INPUT 81 #define CS42L43_ASPTX6_INPUT 82 #define CS42L43_SWIRE_DP1_CH1_INPUT 83 #define CS42L43_SWIRE_DP1_CH2_INPUT 84 #define CS42L43_SWIRE_DP1_CH3_INPUT 85 #define CS42L43_SWIRE_DP1_CH4_INPUT 86 #define CS42L43_SWIRE_DP2_CH1_INPUT 87 #define CS42L43_SWIRE_DP2_CH2_INPUT 88 #define CS42L43_SWIRE_DP3_CH1_INPUT 89 #define CS42L43_SWIRE_DP3_CH2_INPUT 90 #define CS42L43_SWIRE_DP4_CH1_INPUT 91 #define CS42L43_SWIRE_DP4_CH2_INPUT 92 #define CS42L43_ASRC_INT1_INPUT1 93 #define CS42L43_ASRC_INT2_INPUT1 94 #define CS42L43_ASRC_INT3_INPUT1 95 #define CS42L43_ASRC_INT4_INPUT1 96 #define CS42L43_ASRC_DEC1_INPUT1 97 #define CS42L43_ASRC_DEC2_INPUT1 98 #define CS42L43_ASRC_DEC3_INPUT1 99 #define CS42L43_ASRC_DEC4_INPUT1 100 #define CS42L43_ISRC1INT1_INPUT1 101 #define CS42L43_ISRC1INT2_INPUT1 102 #define CS42L43_ISRC1DEC1_INPUT1 103 #define CS42L43_ISRC1DEC2_INPUT1 104 #define CS42L43_ISRC2INT1_INPUT1 105 #define CS42L43_ISRC2INT2_INPUT1 106 #define CS42L43_ISRC2DEC1_INPUT1 107 #define CS42L43_ISRC2DEC2_INPUT1 108 #define CS42L43_EQ1MIX_INPUT1 109 #define CS42L43_EQ1MIX_INPUT2 110 #define CS42L43_EQ1MIX_INPUT3 111 #define CS42L43_EQ1MIX_INPUT4 112 #define CS42L43_EQ2MIX_INPUT1 113 #define CS42L43_EQ2MIX_INPUT2 114 #define CS42L43_EQ2MIX_INPUT3 115 #define CS42L43_EQ2MIX_INPUT4 116 #define CS42L43_SPDIF1_INPUT1 117 #define CS42L43_SPDIF2_INPUT1 118 #define CS42L43_AMP1MIX_INPUT1 119 #define CS42L43_AMP1MIX_INPUT2 120 #define CS42L43_AMP1MIX_INPUT3 121 #define CS42L43_AMP1MIX_INPUT4 122 #define CS42L43_AMP2MIX_INPUT1 123 #define CS42L43_AMP2MIX_INPUT2 124 #define CS42L43_AMP2MIX_INPUT3 125 #define CS42L43_AMP2MIX_INPUT4 126 #define CS42L43_AMP3MIX_INPUT1 127 #define CS42L43_AMP3MIX_INPUT2 128 #define CS42L43_AMP3MIX_INPUT3 129 #define CS42L43_AMP3MIX_INPUT4 130 #define CS42L43_AMP4MIX_INPUT1 131 #define CS42L43_AMP4MIX_INPUT2 132 #define CS42L43_AMP4MIX_INPUT3 133 #define CS42L43_AMP4MIX_INPUT4 134 #define CS42L43_ASRC_INT_ENABLES 135 #define CS42L43_ASRC_DEC_ENABLES 136 #define CS42L43_PDNCNTL 137 #define CS42L43_RINGSENSE_DEB_CTRL 138 #define CS42L43_TIPSENSE_DEB_CTRL 139 #define CS42L43_TIP_RING_SENSE_INTERRUPT_STATU 140 #define CS42L43_HS2 141 #define CS42L43_HS_STAT 142 #define CS42L43_MCU_SW_INTERRUPT 143 #define CS42L43_STEREO_MIC_CTRL 144 #define CS42L43_STEREO_MIC_CLAMP_CTRL 145 #define CS42L43_BLOCK_EN2 146 #define CS42L43_BLOCK_EN3 147 #define CS42L43_BLOCK_EN4 148 #define CS42L43_BLOCK_EN5 149 #define CS42L43_BLOCK_EN6 150 #define CS42L43_BLOCK_EN7 151 #define CS42L43_BLOCK_EN8 152 #define CS42L43_BLOCK_EN9 153 #define CS42L43_BLOCK_EN10 154 #define CS42L43_BLOCK_EN11 155 #define CS42L43_TONE_CH1_CTRL 156 #define CS42L43_TONE_CH2_CTRL 157 #define CS42L43_MIC_DETECT_CONTROL_1 158 #define CS42L43_DETECT_STATUS_1 159 #define CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCO 160 #define CS42L43_MIC_DETECT_CONTROL_ANDROID 161 #define CS42L43_ISRC1_CTRL 162 #define CS42L43_ISRC2_CTRL 163 #define CS42L43_CTRL_REG 164 #define CS42L43_FDIV_FRAC 165 #define CS42L43_CAL_RATIO 166 #define CS42L43_SPI_CLK_CONFIG1 167 #define CS42L43_SPI_CONFIG1 168 #define CS42L43_SPI_CONFIG2 169 #define CS42L43_SPI_CONFIG3 170 #define CS42L43_SPI_CONFIG4 171 #define CS42L43_SPI_STATUS1 172 #define CS42L43_SPI_STATUS2 173 #define CS42L43_TRAN_CONFIG1 174 #define CS42L43_TRAN_CONFIG2 175 #define CS42L43_TRAN_CONFIG3 176 #define CS42L43_TRAN_CONFIG4 177 #define CS42L43_TRAN_CONFIG5 178 #define CS42L43_TRAN_CONFIG6 179 #define CS42L43_TRAN_CONFIG7 180 #define CS42L43_TRAN_CONFIG8 181 #define CS42L43_TRAN_STATUS1 182 #define CS42L43_TRAN_STATUS2 183 #define CS42L43_TRAN_STATUS3 184 #define CS42L43_TX_DATA 185 #define CS42L43_RX_DATA 186 #define CS42L43_DACCNFG1 187 #define CS42L43_DACCNFG2 188 #define CS42L43_HPPATHVOL 189 #define CS42L43_PGAVOL 190 #define CS42L43_LOADDETRESULTS 191 #define CS42L43_LOADDETENA 192 #define CS42L43_CTRL 193 #define CS42L43_COEFF_DATA_IN0 194 #define CS42L43_COEFF_RD_WR0 195 #define CS42L43_INIT_DONE0 196 #define CS42L43_START_EQZ0 197 #define CS42L43_MUTE_EQ_IN0 198 #define CS42L43_DECIM_INT 199 #define CS42L43_EQ_INT 200 #define CS42L43_ASP_INT 201 #define CS42L43_PLL_INT 202 #define CS42L43_SOFT_INT 203 #define CS42L43_SWIRE_INT 204 #define CS42L43_MSM_INT 205 #define CS42L43_ACC_DET_INT 206 #define CS42L43_I2C_TGT_INT 207 #define CS42L43_SPI_MSTR_INT 208 #define CS42L43_SW_TO_SPI_BRIDGE_INT 209 #define CS42L43_OTP_INT 210 #define CS42L43_CLASS_D_AMP_INT 211 #define CS42L43_GPIO_INT 212 #define CS42L43_ASRC_INT 213 #define CS42L43_HPOUT_INT 214 #define CS42L43_DECIM_MASK 215 #define CS42L43_EQ_MIX_MASK 216 #define CS42L43_ASP_MASK 217 #define CS42L43_PLL_MASK 218 #define CS42L43_SOFT_MASK 219 #define CS42L43_SWIRE_MASK 220 #define CS42L43_MSM_MASK 221 #define CS42L43_ACC_DET_MASK 222 #define CS42L43_I2C_TGT_MASK 223 #define CS42L43_SPI_MSTR_MASK 224 #define CS42L43_SW_TO_SPI_BRIDGE_MASK 225 #define CS42L43_OTP_MASK 226 #define CS42L43_CLASS_D_AMP_MASK 227 #define CS42L43_GPIO_INT_MASK 228 #define CS42L43_ASRC_MASK 229 #define CS42L43_HPOUT_MASK 230 #define CS42L43_DECIM_INT_SHADOW 231 #define CS42L43_EQ_MIX_INT_SHADOW 232 #define CS42L43_ASP_INT_SHADOW 233 #define CS42L43_PLL_INT_SHADOW 234 #define CS42L43_SOFT_INT_SHADOW 235 #define CS42L43_SWIRE_INT_SHADOW 236 #define CS42L43_MSM_INT_SHADOW 237 #define CS42L43_ACC_DET_INT_SHADOW 238 #define CS42L43_I2C_TGT_INT_SHADOW 239 #define CS42L43_SPI_MSTR_INT_SHADOW 240 #define CS42L43_SW_TO_SPI_BRIDGE_SHADOW 241 #define CS42L43_OTP_INT_SHADOW 242 #define CS42L43_CLASS_D_AMP_INT_SHADOW 243 #define CS42L43_GPIO_SHADOW 244 #define CS42L43_ASRC_SHADOW 245 #define CS42L43_HP_OUT_SHADOW 246 #define CS42L43_BOOT_CONTROL 247 #define CS42L43_BLOCK_EN 248 #define CS42L43_SHUTTER_CONTROL 249 #define CS42L43_MCU_SW_REV 250 #define CS42L43_PATCH_START_ADDR 251 #define CS42L43_NEED_CONFIGS 252 #define CS42L43_BOOT_STATUS 253 #define CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS 254 #define CS42L43_FW_MISSION_CTRL_NEED_CONFIGS 255 #define CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS 256 #define CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECT 257 #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG 258 #define CS42L43_MCU_RAM_MAX 259 260 /* CS42L43_DEVID */ 261 #define CS42L43_DEVID_VAL 262 263 /* CS42L43_GEN_INT_STAT_1 */ 264 #define CS42L43_INT_STAT_GEN1_MASK 265 #define CS42L43_INT_STAT_GEN1_SHIFT 266 267 /* CS42L43_SFT_RESET */ 268 #define CS42L43_SFT_RESET_MASK 269 #define CS42L43_SFT_RESET_SHIFT 270 271 #define CS42L43_SFT_RESET_VAL 272 273 /* CS42L43_DRV_CTRL1 */ 274 #define CS42L43_ASP_DOUT_DRV_MASK 275 #define CS42L43_ASP_DOUT_DRV_SHIFT 276 #define CS42L43_ASP_FSYNC_DRV_MASK 277 #define CS42L43_ASP_FSYNC_DRV_SHIFT 278 #define CS42L43_ASP_BCLK_DRV_MASK 279 #define CS42L43_ASP_BCLK_DRV_SHIFT 280 281 /* CS42L43_DRV_CTRL3 */ 282 #define CS42L43_I2C_ADDR_DRV_MASK 283 #define CS42L43_I2C_ADDR_DRV_SHIFT 284 #define CS42L43_I2C_SDA_DRV_MASK 285 #define CS42L43_I2C_SDA_DRV_SHIFT 286 #define CS42L43_PDMOUT2_CLK_DRV_MASK 287 #define CS42L43_PDMOUT2_CLK_DRV_SHIFT 288 #define CS42L43_PDMOUT2_DATA_DRV_MASK 289 #define CS42L43_PDMOUT2_DATA_DRV_SHIFT 290 #define CS42L43_PDMOUT1_CLK_DRV_MASK 291 #define CS42L43_PDMOUT1_CLK_DRV_SHIFT 292 #define CS42L43_PDMOUT1_DATA_DRV_MASK 293 #define CS42L43_PDMOUT1_DATA_DRV_SHIFT 294 #define CS42L43_SPI_MISO_DRV_MASK 295 #define CS42L43_SPI_MISO_DRV_SHIFT 296 297 /* CS42L43_DRV_CTRL4 */ 298 #define CS42L43_GPIO3_DRV_MASK 299 #define CS42L43_GPIO3_DRV_SHIFT 300 #define CS42L43_GPIO2_DRV_MASK 301 #define CS42L43_GPIO2_DRV_SHIFT 302 #define CS42L43_GPIO1_DRV_MASK 303 #define CS42L43_GPIO1_DRV_SHIFT 304 305 /* CS42L43_DRV_CTRL_5 */ 306 #define CS42L43_I2C_SCL_DRV_MASK 307 #define CS42L43_I2C_SCL_DRV_SHIFT 308 #define CS42L43_SPI_SCK_DRV_MASK 309 #define CS42L43_SPI_SCK_DRV_SHIFT 310 #define CS42L43_SPI_MOSI_DRV_MASK 311 #define CS42L43_SPI_MOSI_DRV_SHIFT 312 #define CS42L43_SPI_SSB_DRV_MASK 313 #define CS42L43_SPI_SSB_DRV_SHIFT 314 #define CS42L43_ASP_DIN_DRV_MASK 315 #define CS42L43_ASP_DIN_DRV_SHIFT 316 317 /* CS42L43_GPIO_CTRL1 */ 318 #define CS42L43_GPIO3_POL_MASK 319 #define CS42L43_GPIO3_POL_SHIFT 320 #define CS42L43_GPIO2_POL_MASK 321 #define CS42L43_GPIO2_POL_SHIFT 322 #define CS42L43_GPIO1_POL_MASK 323 #define CS42L43_GPIO1_POL_SHIFT 324 #define CS42L43_GPIO3_LVL_MASK 325 #define CS42L43_GPIO3_LVL_SHIFT 326 #define CS42L43_GPIO2_LVL_MASK 327 #define CS42L43_GPIO2_LVL_SHIFT 328 #define CS42L43_GPIO1_LVL_MASK 329 #define CS42L43_GPIO1_LVL_SHIFT 330 #define CS42L43_GPIO3_DIR_MASK 331 #define CS42L43_GPIO3_DIR_SHIFT 332 #define CS42L43_GPIO2_DIR_MASK 333 #define CS42L43_GPIO2_DIR_SHIFT 334 #define CS42L43_GPIO1_DIR_MASK 335 #define CS42L43_GPIO1_DIR_SHIFT 336 337 /* CS42L43_GPIO_CTRL2 */ 338 #define CS42L43_GPIO3_DEGLITCH_BYP_MASK 339 #define CS42L43_GPIO3_DEGLITCH_BYP_SHIFT 340 #define CS42L43_GPIO2_DEGLITCH_BYP_MASK 341 #define CS42L43_GPIO2_DEGLITCH_BYP_SHIFT 342 #define CS42L43_GPIO1_DEGLITCH_BYP_MASK 343 #define CS42L43_GPIO1_DEGLITCH_BYP_SHIFT 344 345 /* CS42L43_GPIO_STS */ 346 #define CS42L43_GPIO3_STS_MASK 347 #define CS42L43_GPIO3_STS_SHIFT 348 #define CS42L43_GPIO2_STS_MASK 349 #define CS42L43_GPIO2_STS_SHIFT 350 #define CS42L43_GPIO1_STS_MASK 351 #define CS42L43_GPIO1_STS_SHIFT 352 353 /* CS42L43_GPIO_FN_SEL */ 354 #define CS42L43_GPIO3_FN_SEL_MASK 355 #define CS42L43_GPIO3_FN_SEL_SHIFT 356 #define CS42L43_GPIO1_FN_SEL_MASK 357 #define CS42L43_GPIO1_FN_SEL_SHIFT 358 359 /* CS42L43_MCLK_SRC_SEL */ 360 #define CS42L43_OSC_PLL_MCLK_SEL_MASK 361 #define CS42L43_OSC_PLL_MCLK_SEL_SHIFT 362 363 /* CS42L43_SAMPLE_RATE1..CS42L43_SAMPLE_RATE4 364 #define CS42L43_SAMPLE_RATE_MASK 365 #define CS42L43_SAMPLE_RATE_SHIFT 366 367 /* CS42L43_PLL_CONTROL */ 368 #define CS42L43_PLL_REFCLK_EN_MASK 369 #define CS42L43_PLL_REFCLK_EN_SHIFT 370 #define CS42L43_PLL_REFCLK_DIV_MASK 371 #define CS42L43_PLL_REFCLK_DIV_SHIFT 372 #define CS42L43_PLL_REFCLK_SRC_MASK 373 #define CS42L43_PLL_REFCLK_SRC_SHIFT 374 375 /* CS42L43_FS_SELECT1 */ 376 #define CS42L43_ASP_RATE_MASK 377 #define CS42L43_ASP_RATE_SHIFT 378 379 /* CS42L43_FS_SELECT2 */ 380 #define CS42L43_ASRC_DEC_OUT_RATE_MASK 381 #define CS42L43_ASRC_DEC_OUT_RATE_SHIFT 382 #define CS42L43_ASRC_INT_OUT_RATE_MASK 383 #define CS42L43_ASRC_INT_OUT_RATE_SHIFT 384 #define CS42L43_ASRC_DEC_IN_RATE_MASK 385 #define CS42L43_ASRC_DEC_IN_RATE_SHIFT 386 #define CS42L43_ASRC_INT_IN_RATE_MASK 387 #define CS42L43_ASRC_INT_IN_RATE_SHIFT 388 389 /* CS42L43_FS_SELECT3 */ 390 #define CS42L43_HPOUT_RATE_MASK 391 #define CS42L43_HPOUT_RATE_SHIFT 392 #define CS42L43_EQZ_RATE_MASK 393 #define CS42L43_EQZ_RATE_SHIFT 394 #define CS42L43_DIAGGEN_RATE_MASK 395 #define CS42L43_DIAGGEN_RATE_SHIFT 396 #define CS42L43_DECIM_CH4_RATE_MASK 397 #define CS42L43_DECIM_CH4_RATE_SHIFT 398 #define CS42L43_DECIM_CH3_RATE_MASK 399 #define CS42L43_DECIM_CH3_RATE_SHIFT 400 #define CS42L43_DECIM_CH2_RATE_MASK 401 #define CS42L43_DECIM_CH2_RATE_SHIFT 402 #define CS42L43_DECIM_CH1_RATE_MASK 403 #define CS42L43_DECIM_CH1_RATE_SHIFT 404 #define CS42L43_AMP1_2_RATE_MASK 405 #define CS42L43_AMP1_2_RATE_SHIFT 406 407 /* CS42L43_FS_SELECT4 */ 408 #define CS42L43_SW_DP7_RATE_MASK 409 #define CS42L43_SW_DP7_RATE_SHIFT 410 #define CS42L43_SW_DP6_RATE_MASK 411 #define CS42L43_SW_DP6_RATE_SHIFT 412 #define CS42L43_SPDIF_RATE_MASK 413 #define CS42L43_SPDIF_RATE_SHIFT 414 #define CS42L43_SW_DP5_RATE_MASK 415 #define CS42L43_SW_DP5_RATE_SHIFT 416 #define CS42L43_SW_DP4_RATE_MASK 417 #define CS42L43_SW_DP4_RATE_SHIFT 418 #define CS42L43_SW_DP3_RATE_MASK 419 #define CS42L43_SW_DP3_RATE_SHIFT 420 #define CS42L43_SW_DP2_RATE_MASK 421 #define CS42L43_SW_DP2_RATE_SHIFT 422 #define CS42L43_SW_DP1_RATE_MASK 423 #define CS42L43_SW_DP1_RATE_SHIFT 424 #define CS42L43_ISRC2_LOW_RATE_MASK 425 #define CS42L43_ISRC2_LOW_RATE_SHIFT 426 #define CS42L43_ISRC2_HIGH_RATE_MASK 427 #define CS42L43_ISRC2_HIGH_RATE_SHIFT 428 #define CS42L43_ISRC1_LOW_RATE_MASK 429 #define CS42L43_ISRC1_LOW_RATE_SHIFT 430 #define CS42L43_ISRC1_HIGH_RATE_MASK 431 #define CS42L43_ISRC1_HIGH_RATE_SHIFT 432 433 /* CS42L43_PDM_CONTROL */ 434 #define CS42L43_PDM2_CLK_DIV_MASK 435 #define CS42L43_PDM2_CLK_DIV_SHIFT 436 #define CS42L43_PDM1_CLK_DIV_MASK 437 #define CS42L43_PDM1_CLK_DIV_SHIFT 438 439 /* CS42L43_ASP_CLK_CONFIG1 */ 440 #define CS42L43_ASP_BCLK_N_MASK 441 #define CS42L43_ASP_BCLK_N_SHIFT 442 #define CS42L43_ASP_BCLK_M_MASK 443 #define CS42L43_ASP_BCLK_M_SHIFT 444 445 /* CS42L43_ASP_CLK_CONFIG2 */ 446 #define CS42L43_ASP_MASTER_MODE_MASK 447 #define CS42L43_ASP_MASTER_MODE_SHIFT 448 #define CS42L43_ASP_BCLK_INV_MASK 449 #define CS42L43_ASP_BCLK_INV_SHIFT 450 451 /* CS42L43_OSC_DIV_SEL */ 452 #define CS42L43_OSC_DIV2_EN_MASK 453 #define CS42L43_OSC_DIV2_EN_SHIFT 454 455 /* CS42L43_ADC_B_CTRL1..CS42L43_ADC_B_CTRL1 */ 456 #define CS42L43_PGA_WIDESWING_MODE_EN_MASK 457 #define CS42L43_PGA_WIDESWING_MODE_EN_SHIFT 458 #define CS42L43_ADC_AIN_SEL_MASK 459 #define CS42L43_ADC_AIN_SEL_SHIFT 460 #define CS42L43_ADC_PGA_GAIN_MASK 461 #define CS42L43_ADC_PGA_GAIN_SHIFT 462 463 /* CS42L43_DECIM_HPF_WNF_CTRL1..CS42L43_DECIM_ 464 #define CS42L43_DECIM_WNF_CF_MASK 465 #define CS42L43_DECIM_WNF_CF_SHIFT 466 #define CS42L43_DECIM_WNF_EN_MASK 467 #define CS42L43_DECIM_WNF_EN_SHIFT 468 #define CS42L43_DECIM_HPF_CF_MASK 469 #define CS42L43_DECIM_HPF_CF_SHIFT 470 #define CS42L43_DECIM_HPF_EN_MASK 471 #define CS42L43_DECIM_HPF_EN_SHIFT 472 473 /* CS42L43_DMIC_PDM_CTRL */ 474 #define CS42L43_PDM2R_INV_MASK 475 #define CS42L43_PDM2R_INV_SHIFT 476 #define CS42L43_PDM2L_INV_MASK 477 #define CS42L43_PDM2L_INV_SHIFT 478 #define CS42L43_PDM1R_INV_MASK 479 #define CS42L43_PDM1R_INV_SHIFT 480 #define CS42L43_PDM1L_INV_MASK 481 #define CS42L43_PDM1L_INV_SHIFT 482 483 /* CS42L43_DECIM_VOL_CTRL_CH1_CH2 */ 484 #define CS42L43_DECIM2_MUTE_MASK 485 #define CS42L43_DECIM2_MUTE_SHIFT 486 #define CS42L43_DECIM2_VOL_MASK 487 #define CS42L43_DECIM2_VOL_SHIFT 488 #define CS42L43_DECIM2_VD_RAMP_MASK 489 #define CS42L43_DECIM2_VD_RAMP_SHIFT 490 #define CS42L43_DECIM2_VI_RAMP_MASK 491 #define CS42L43_DECIM2_VI_RAMP_SHIFT 492 #define CS42L43_DECIM1_MUTE_MASK 493 #define CS42L43_DECIM1_MUTE_SHIFT 494 #define CS42L43_DECIM1_VOL_MASK 495 #define CS42L43_DECIM1_VOL_SHIFT 496 #define CS42L43_DECIM1_VD_RAMP_MASK 497 #define CS42L43_DECIM1_VD_RAMP_SHIFT 498 #define CS42L43_DECIM1_VI_RAMP_MASK 499 #define CS42L43_DECIM1_VI_RAMP_SHIFT 500 501 /* CS42L43_DECIM_VOL_CTRL_CH3_CH4 */ 502 #define CS42L43_DECIM4_MUTE_MASK 503 #define CS42L43_DECIM4_MUTE_SHIFT 504 #define CS42L43_DECIM4_VOL_MASK 505 #define CS42L43_DECIM4_VOL_SHIFT 506 #define CS42L43_DECIM4_VD_RAMP_MASK 507 #define CS42L43_DECIM4_VD_RAMP_SHIFT 508 #define CS42L43_DECIM4_VI_RAMP_MASK 509 #define CS42L43_DECIM4_VI_RAMP_SHIFT 510 #define CS42L43_DECIM3_MUTE_MASK 511 #define CS42L43_DECIM3_MUTE_SHIFT 512 #define CS42L43_DECIM3_VOL_MASK 513 #define CS42L43_DECIM3_VOL_SHIFT 514 #define CS42L43_DECIM3_VD_RAMP_MASK 515 #define CS42L43_DECIM3_VD_RAMP_SHIFT 516 #define CS42L43_DECIM3_VI_RAMP_MASK 517 #define CS42L43_DECIM3_VI_RAMP_SHIFT 518 519 /* CS42L43_DECIM_VOL_CTRL_UPDATE */ 520 #define CS42L43_DECIM4_VOL_UPDATE_MASK 521 #define CS42L43_DECIM4_VOL_UPDATE_SHIFT 522 #define CS42L43_DECIM3_VOL_UPDATE_MASK 523 #define CS42L43_DECIM3_VOL_UPDATE_SHIFT 524 #define CS42L43_DECIM2_VOL_UPDATE_MASK 525 #define CS42L43_DECIM2_VOL_UPDATE_SHIFT 526 #define CS42L43_DECIM1_VOL_UPDATE_MASK 527 #define CS42L43_DECIM1_VOL_UPDATE_SHIFT 528 529 /* CS42L43_INTP_VOLUME_CTRL1..CS42L43_INTP_VOL 530 #define CS42L43_AMP1_2_VU_MASK 531 #define CS42L43_AMP1_2_VU_SHIFT 532 #define CS42L43_AMP_MUTE_MASK 533 #define CS42L43_AMP_MUTE_SHIFT 534 #define CS42L43_AMP_VOL_MASK 535 #define CS42L43_AMP_VOL_SHIFT 536 537 /* CS42L43_AMP1_2_VOL_RAMP */ 538 #define CS42L43_AMP1_2_VD_RAMP_MASK 539 #define CS42L43_AMP1_2_VD_RAMP_SHIFT 540 #define CS42L43_AMP1_2_VI_RAMP_MASK 541 #define CS42L43_AMP1_2_VI_RAMP_SHIFT 542 543 /* CS42L43_ASP_CTRL */ 544 #define CS42L43_ASP_FSYNC_MODE_MASK 545 #define CS42L43_ASP_FSYNC_MODE_SHIFT 546 #define CS42L43_ASP_BCLK_EN_MASK 547 #define CS42L43_ASP_BCLK_EN_SHIFT 548 #define CS42L43_ASP_FSYNC_EN_MASK 549 #define CS42L43_ASP_FSYNC_EN_SHIFT 550 551 /* CS42L43_ASP_FSYNC_CTRL1 */ 552 #define CS42L43_ASP_FSYNC_M_MASK 553 #define CS42L43_ASP_FSYNC_M_SHIFT 554 555 /* CS42L43_ASP_FSYNC_CTRL3 */ 556 #define CS42L43_ASP_FSYNC_IN_INV_MASK 557 #define CS42L43_ASP_FSYNC_IN_INV_SHIFT 558 #define CS42L43_ASP_FSYNC_OUT_INV_MASK 559 #define CS42L43_ASP_FSYNC_OUT_INV_SHIFT 560 561 /* CS42L43_ASP_FSYNC_CTRL4 */ 562 #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_MASK 563 #define CS42L43_ASP_NUM_BCLKS_PER_FSYNC_SHIFT 564 565 /* CS42L43_ASP_DATA_CTRL */ 566 #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_MA 567 #define CS42L43_ASP_FSYNC_FRAME_START_PHASE_SH 568 #define CS42L43_ASP_FSYNC_FRAME_START_DLY_MASK 569 #define CS42L43_ASP_FSYNC_FRAME_START_DLY_SHIF 570 571 /* CS42L43_ASP_RX_EN */ 572 #define CS42L43_ASP_RX_CH6_EN_MASK 573 #define CS42L43_ASP_RX_CH6_EN_SHIFT 574 #define CS42L43_ASP_RX_CH5_EN_MASK 575 #define CS42L43_ASP_RX_CH5_EN_SHIFT 576 #define CS42L43_ASP_RX_CH4_EN_MASK 577 #define CS42L43_ASP_RX_CH4_EN_SHIFT 578 #define CS42L43_ASP_RX_CH3_EN_MASK 579 #define CS42L43_ASP_RX_CH3_EN_SHIFT 580 #define CS42L43_ASP_RX_CH2_EN_MASK 581 #define CS42L43_ASP_RX_CH2_EN_SHIFT 582 #define CS42L43_ASP_RX_CH1_EN_MASK 583 #define CS42L43_ASP_RX_CH1_EN_SHIFT 584 585 /* CS42L43_ASP_TX_EN */ 586 #define CS42L43_ASP_TX_CH6_EN_MASK 587 #define CS42L43_ASP_TX_CH6_EN_SHIFT 588 #define CS42L43_ASP_TX_CH5_EN_MASK 589 #define CS42L43_ASP_TX_CH5_EN_SHIFT 590 #define CS42L43_ASP_TX_CH4_EN_MASK 591 #define CS42L43_ASP_TX_CH4_EN_SHIFT 592 #define CS42L43_ASP_TX_CH3_EN_MASK 593 #define CS42L43_ASP_TX_CH3_EN_SHIFT 594 #define CS42L43_ASP_TX_CH2_EN_MASK 595 #define CS42L43_ASP_TX_CH2_EN_SHIFT 596 #define CS42L43_ASP_TX_CH1_EN_MASK 597 #define CS42L43_ASP_TX_CH1_EN_SHIFT 598 599 /* CS42L43_ASP_RX_CH1_CTRL..CS42L43_ASP_TX_CH6 600 #define CS42L43_ASP_CH_WIDTH_MASK 601 #define CS42L43_ASP_CH_WIDTH_SHIFT 602 #define CS42L43_ASP_CH_SLOT_MASK 603 #define CS42L43_ASP_CH_SLOT_SHIFT 604 #define CS42L43_ASP_CH_SLOT_PHASE_MASK 605 #define CS42L43_ASP_CH_SLOT_PHASE_SHIFT 606 607 /* CS42L43_ASPTX1_INPUT..CS42L43_AMP4MIX_INPUT 608 #define CS42L43_MIXER_VOL_MASK 609 #define CS42L43_MIXER_VOL_SHIFT 610 #define CS42L43_MIXER_SRC_MASK 611 #define CS42L43_MIXER_SRC_SHIFT 612 613 /* CS42L43_ASRC_INT_ENABLES */ 614 #define CS42L43_ASRC_INT4_EN_MASK 615 #define CS42L43_ASRC_INT4_EN_SHIFT 616 #define CS42L43_ASRC_INT3_EN_MASK 617 #define CS42L43_ASRC_INT3_EN_SHIFT 618 #define CS42L43_ASRC_INT2_EN_MASK 619 #define CS42L43_ASRC_INT2_EN_SHIFT 620 #define CS42L43_ASRC_INT1_EN_MASK 621 #define CS42L43_ASRC_INT1_EN_SHIFT 622 623 /* CS42L43_ASRC_DEC_ENABLES */ 624 #define CS42L43_ASRC_DEC4_EN_MASK 625 #define CS42L43_ASRC_DEC4_EN_SHIFT 626 #define CS42L43_ASRC_DEC3_EN_MASK 627 #define CS42L43_ASRC_DEC3_EN_SHIFT 628 #define CS42L43_ASRC_DEC2_EN_MASK 629 #define CS42L43_ASRC_DEC2_EN_SHIFT 630 #define CS42L43_ASRC_DEC1_EN_MASK 631 #define CS42L43_ASRC_DEC1_EN_SHIFT 632 633 /* CS42L43_PDNCNTL */ 634 #define CS42L43_RING_SENSE_EN_MASK 635 #define CS42L43_RING_SENSE_EN_SHIFT 636 637 /* CS42L43_RINGSENSE_DEB_CTRL */ 638 #define CS42L43_RINGSENSE_INV_MASK 639 #define CS42L43_RINGSENSE_INV_SHIFT 640 #define CS42L43_RINGSENSE_PULLUP_PDNB_MASK 641 #define CS42L43_RINGSENSE_PULLUP_PDNB_SHIFT 642 #define CS42L43_RINGSENSE_FALLING_DB_TIME_MASK 643 #define CS42L43_RINGSENSE_FALLING_DB_TIME_SHIF 644 #define CS42L43_RINGSENSE_RISING_DB_TIME_MASK 645 #define CS42L43_RINGSENSE_RISING_DB_TIME_SHIFT 646 647 /* CS42L43_TIPSENSE_DEB_CTRL */ 648 #define CS42L43_TIPSENSE_INV_MASK 649 #define CS42L43_TIPSENSE_INV_SHIFT 650 #define CS42L43_TIPSENSE_FALLING_DB_TIME_MASK 651 #define CS42L43_TIPSENSE_FALLING_DB_TIME_SHIFT 652 #define CS42L43_TIPSENSE_RISING_DB_TIME_MASK 653 #define CS42L43_TIPSENSE_RISING_DB_TIME_SHIFT 654 655 /* CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS */ 656 #define CS42L43_TIPSENSE_UNPLUG_DB_STS_MASK 657 #define CS42L43_TIPSENSE_UNPLUG_DB_STS_SHIFT 658 #define CS42L43_TIPSENSE_PLUG_DB_STS_MASK 659 #define CS42L43_TIPSENSE_PLUG_DB_STS_SHIFT 660 #define CS42L43_RINGSENSE_UNPLUG_DB_STS_MASK 661 #define CS42L43_RINGSENSE_UNPLUG_DB_STS_SHIFT 662 #define CS42L43_RINGSENSE_PLUG_DB_STS_MASK 663 #define CS42L43_RINGSENSE_PLUG_DB_STS_SHIFT 664 665 /* CS42L43_HS2 */ 666 #define CS42L43_HS_CLAMP_DISABLE_MASK 667 #define CS42L43_HS_CLAMP_DISABLE_SHIFT 668 #define CS42L43_HSBIAS_RAMP_MASK 669 #define CS42L43_HSBIAS_RAMP_SHIFT 670 #define CS42L43_HSDET_MODE_MASK 671 #define CS42L43_HSDET_MODE_SHIFT 672 #define CS42L43_HSDET_MANUAL_MODE_MASK 673 #define CS42L43_HSDET_MANUAL_MODE_SHIFT 674 #define CS42L43_AUTO_HSDET_TIME_MASK 675 #define CS42L43_AUTO_HSDET_TIME_SHIFT 676 #define CS42L43_AMP3_4_GNDREF_HS3_SEL_MASK 677 #define CS42L43_AMP3_4_GNDREF_HS3_SEL_SHIFT 678 #define CS42L43_AMP3_4_GNDREF_HS4_SEL_MASK 679 #define CS42L43_AMP3_4_GNDREF_HS4_SEL_SHIFT 680 #define CS42L43_HSBIAS_GNDREF_HS3_SEL_MASK 681 #define CS42L43_HSBIAS_GNDREF_HS3_SEL_SHIFT 682 #define CS42L43_HSBIAS_GNDREF_HS4_SEL_MASK 683 #define CS42L43_HSBIAS_GNDREF_HS4_SEL_SHIFT 684 #define CS42L43_HSBIAS_OUT_HS3_SEL_MASK 685 #define CS42L43_HSBIAS_OUT_HS3_SEL_SHIFT 686 #define CS42L43_HSBIAS_OUT_HS4_SEL_MASK 687 #define CS42L43_HSBIAS_OUT_HS4_SEL_SHIFT 688 #define CS42L43_HSGND_HS3_SEL_MASK 689 #define CS42L43_HSGND_HS3_SEL_SHIFT 690 #define CS42L43_HSGND_HS4_SEL_MASK 691 #define CS42L43_HSGND_HS4_SEL_SHIFT 692 693 /* CS42L43_HS_STAT */ 694 #define CS42L43_HSDET_TYPE_STS_MASK 695 #define CS42L43_HSDET_TYPE_STS_SHIFT 696 697 /* CS42L43_MCU_SW_INTERRUPT */ 698 #define CS42L43_CONTROL_IND_MASK 699 #define CS42L43_CONTROL_IND_SHIFT 700 #define CS42L43_CONFIGS_IND_MASK 701 #define CS42L43_CONFIGS_IND_SHIFT 702 #define CS42L43_PATCH_IND_MASK 703 #define CS42L43_PATCH_IND_SHIFT 704 705 /* CS42L43_STEREO_MIC_CTRL */ 706 #define CS42L43_HS2_BIAS_SENSE_EN_MASK 707 #define CS42L43_HS2_BIAS_SENSE_EN_SHIFT 708 #define CS42L43_HS1_BIAS_SENSE_EN_MASK 709 #define CS42L43_HS1_BIAS_SENSE_EN_SHIFT 710 #define CS42L43_HS2_BIAS_EN_MASK 711 #define CS42L43_HS2_BIAS_EN_SHIFT 712 #define CS42L43_HS1_BIAS_EN_MASK 713 #define CS42L43_HS1_BIAS_EN_SHIFT 714 #define CS42L43_JACK_STEREO_CONFIG_MASK 715 #define CS42L43_JACK_STEREO_CONFIG_SHIFT 716 717 /* CS42L43_STEREO_MIC_CLAMP_CTRL */ 718 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_M 719 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_VAL_S 720 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_MASK 721 #define CS42L43_SMIC_HPAMP_CLAMP_DIS_FRC_SHIFT 722 723 /* CS42L43_BLOCK_EN2 */ 724 #define CS42L43_SPI_MSTR_EN_MASK 725 #define CS42L43_SPI_MSTR_EN_SHIFT 726 727 /* CS42L43_BLOCK_EN3 */ 728 #define CS42L43_PDM2_DIN_R_EN_MASK 729 #define CS42L43_PDM2_DIN_R_EN_SHIFT 730 #define CS42L43_PDM2_DIN_L_EN_MASK 731 #define CS42L43_PDM2_DIN_L_EN_SHIFT 732 #define CS42L43_PDM1_DIN_R_EN_MASK 733 #define CS42L43_PDM1_DIN_R_EN_SHIFT 734 #define CS42L43_PDM1_DIN_L_EN_MASK 735 #define CS42L43_PDM1_DIN_L_EN_SHIFT 736 #define CS42L43_ADC2_EN_MASK 737 #define CS42L43_ADC2_EN_SHIFT 738 #define CS42L43_ADC1_EN_MASK 739 #define CS42L43_ADC1_EN_SHIFT 740 741 /* CS42L43_BLOCK_EN4 */ 742 #define CS42L43_ASRC_DEC_BANK_EN_MASK 743 #define CS42L43_ASRC_DEC_BANK_EN_SHIFT 744 #define CS42L43_ASRC_INT_BANK_EN_MASK 745 #define CS42L43_ASRC_INT_BANK_EN_SHIFT 746 747 /* CS42L43_BLOCK_EN5 */ 748 #define CS42L43_ISRC2_BANK_EN_MASK 749 #define CS42L43_ISRC2_BANK_EN_SHIFT 750 #define CS42L43_ISRC1_BANK_EN_MASK 751 #define CS42L43_ISRC1_BANK_EN_SHIFT 752 753 /* CS42L43_BLOCK_EN6 */ 754 #define CS42L43_MIXER_EN_MASK 755 #define CS42L43_MIXER_EN_SHIFT 756 757 /* CS42L43_BLOCK_EN7 */ 758 #define CS42L43_EQ_EN_MASK 759 #define CS42L43_EQ_EN_SHIFT 760 761 /* CS42L43_BLOCK_EN8 */ 762 #define CS42L43_HP_EN_MASK 763 #define CS42L43_HP_EN_SHIFT 764 765 /* CS42L43_BLOCK_EN9 */ 766 #define CS42L43_TONE_EN_MASK 767 #define CS42L43_TONE_EN_SHIFT 768 769 /* CS42L43_BLOCK_EN10 */ 770 #define CS42L43_AMP2_EN_MASK 771 #define CS42L43_AMP2_EN_SHIFT 772 #define CS42L43_AMP1_EN_MASK 773 #define CS42L43_AMP1_EN_SHIFT 774 775 /* CS42L43_BLOCK_EN11 */ 776 #define CS42L43_SPDIF_EN_MASK 777 #define CS42L43_SPDIF_EN_SHIFT 778 779 /* CS42L43_TONE_CH1_CTRL..CS42L43_TONE_CH2_CTR 780 #define CS42L43_TONE_FREQ_MASK 781 #define CS42L43_TONE_FREQ_SHIFT 782 #define CS42L43_TONE_SEL_MASK 783 #define CS42L43_TONE_SEL_SHIFT 784 785 /* CS42L43_MIC_DETECT_CONTROL_1 */ 786 #define CS42L43_BUTTON_DETECT_MODE_MASK 787 #define CS42L43_BUTTON_DETECT_MODE_SHIFT 788 #define CS42L43_HSBIAS_MODE_MASK 789 #define CS42L43_HSBIAS_MODE_SHIFT 790 #define CS42L43_MIC_LVL_DET_DISABLE_MASK 791 #define CS42L43_MIC_LVL_DET_DISABLE_SHIFT 792 793 /* CS42L43_DETECT_STATUS_1 */ 794 #define CS42L43_HSDET_DC_STS_MASK 795 #define CS42L43_HSDET_DC_STS_SHIFT 796 #define CS42L43_JACKDET_STS_MASK 797 #define CS42L43_JACKDET_STS_SHIFT 798 #define CS42L43_HSBIAS_CLAMP_STS_MASK 799 #define CS42L43_HSBIAS_CLAMP_STS_SHIFT 800 801 /* CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL 802 #define CS42L43_JACKDET_MODE_MASK 803 #define CS42L43_JACKDET_MODE_SHIFT 804 #define CS42L43_JACKDET_INV_MASK 805 #define CS42L43_JACKDET_INV_SHIFT 806 #define CS42L43_JACKDET_DB_TIME_MASK 807 #define CS42L43_JACKDET_DB_TIME_SHIFT 808 #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_MASK 809 #define CS42L43_S0_AUTO_ADCMUTE_DISABLE_SHIFT 810 #define CS42L43_HSBIAS_SENSE_EN_MASK 811 #define CS42L43_HSBIAS_SENSE_EN_SHIFT 812 #define CS42L43_AUTO_HSBIAS_CLAMP_EN_MASK 813 #define CS42L43_AUTO_HSBIAS_CLAMP_EN_SHIFT 814 #define CS42L43_JACKDET_SENSE_EN_MASK 815 #define CS42L43_JACKDET_SENSE_EN_SHIFT 816 #define CS42L43_HSBIAS_SENSE_TRIP_MASK 817 #define CS42L43_HSBIAS_SENSE_TRIP_SHIFT 818 819 /* CS42L43_MIC_DETECT_CONTROL_ANDROID */ 820 #define CS42L43_HSDET_LVL_COMBWIDTH_MASK 821 #define CS42L43_HSDET_LVL_COMBWIDTH_SHIFT 822 #define CS42L43_HSDET_LVL2_THRESH_MASK 823 #define CS42L43_HSDET_LVL2_THRESH_SHIFT 824 #define CS42L43_HSDET_LVL1_THRESH_MASK 825 #define CS42L43_HSDET_LVL1_THRESH_SHIFT 826 827 /* CS42L43_ISRC1_CTRL..CS42L43_ISRC2_CTRL */ 828 #define CS42L43_ISRC_INT2_EN_MASK 829 #define CS42L43_ISRC_INT2_EN_SHIFT 830 #define CS42L43_ISRC_INT1_EN_MASK 831 #define CS42L43_ISRC_INT1_EN_SHIFT 832 #define CS42L43_ISRC_DEC2_EN_MASK 833 #define CS42L43_ISRC_DEC2_EN_SHIFT 834 #define CS42L43_ISRC_DEC1_EN_MASK 835 #define CS42L43_ISRC_DEC1_EN_SHIFT 836 837 /* CS42L43_CTRL_REG */ 838 #define CS42L43_PLL_MODE_BYPASS_500_MASK 839 #define CS42L43_PLL_MODE_BYPASS_500_SHIFT 840 #define CS42L43_PLL_MODE_BYPASS_1029_MASK 841 #define CS42L43_PLL_MODE_BYPASS_1029_SHIFT 842 #define CS42L43_PLL_EN_MASK 843 #define CS42L43_PLL_EN_SHIFT 844 845 /* CS42L43_FDIV_FRAC */ 846 #define CS42L43_PLL_DIV_INT_MASK 847 #define CS42L43_PLL_DIV_INT_SHIFT 848 #define CS42L43_PLL_DIV_FRAC_BYTE2_MASK 849 #define CS42L43_PLL_DIV_FRAC_BYTE2_SHIFT 850 #define CS42L43_PLL_DIV_FRAC_BYTE1_MASK 851 #define CS42L43_PLL_DIV_FRAC_BYTE1_SHIFT 852 #define CS42L43_PLL_DIV_FRAC_BYTE0_MASK 853 #define CS42L43_PLL_DIV_FRAC_BYTE0_SHIFT 854 855 /* CS42L43_CAL_RATIO */ 856 #define CS42L43_PLL_CAL_RATIO_MASK 857 #define CS42L43_PLL_CAL_RATIO_SHIFT 858 859 /* CS42L43_SPI_CLK_CONFIG1 */ 860 #define CS42L43_SCLK_DIV_MASK 861 #define CS42L43_SCLK_DIV_SHIFT 862 863 /* CS42L43_SPI_CONFIG1 */ 864 #define CS42L43_SPI_SS_IDLE_DUR_MASK 865 #define CS42L43_SPI_SS_IDLE_DUR_SHIFT 866 #define CS42L43_SPI_SS_DELAY_DUR_MASK 867 #define CS42L43_SPI_SS_DELAY_DUR_SHIFT 868 #define CS42L43_SPI_THREE_WIRE_MASK 869 #define CS42L43_SPI_THREE_WIRE_SHIFT 870 #define CS42L43_SPI_DPHA_MASK 871 #define CS42L43_SPI_DPHA_SHIFT 872 #define CS42L43_SPI_CPHA_MASK 873 #define CS42L43_SPI_CPHA_SHIFT 874 #define CS42L43_SPI_CPOL_MASK 875 #define CS42L43_SPI_CPOL_SHIFT 876 #define CS42L43_SPI_SS_SEL_MASK 877 #define CS42L43_SPI_SS_SEL_SHIFT 878 879 /* CS42L43_SPI_CONFIG2 */ 880 #define CS42L43_SPI_SS_FRC_MASK 881 #define CS42L43_SPI_SS_FRC_SHIFT 882 883 /* CS42L43_SPI_CONFIG3 */ 884 #define CS42L43_SPI_WDT_ENA_MASK 885 #define CS42L43_SPI_WDT_ENA_SHIFT 886 887 /* CS42L43_SPI_CONFIG4 */ 888 #define CS42L43_SPI_STALL_ENA_MASK 889 #define CS42L43_SPI_STALL_ENA_SHIFT 890 891 /* CS42L43_SPI_STATUS1 */ 892 #define CS42L43_SPI_ABORT_STS_MASK 893 #define CS42L43_SPI_ABORT_STS_SHIFT 894 #define CS42L43_SPI_DONE_STS_MASK 895 #define CS42L43_SPI_DONE_STS_SHIFT 896 897 /* CS42L43_SPI_STATUS2 */ 898 #define CS42L43_SPI_RX_DONE_STS_MASK 899 #define CS42L43_SPI_RX_DONE_STS_SHIFT 900 #define CS42L43_SPI_TX_DONE_STS_MASK 901 #define CS42L43_SPI_TX_DONE_STS_SHIFT 902 903 /* CS42L43_TRAN_CONFIG1 */ 904 #define CS42L43_SPI_START_MASK 905 #define CS42L43_SPI_START_SHIFT 906 907 /* CS42L43_TRAN_CONFIG2 */ 908 #define CS42L43_SPI_ABORT_MASK 909 #define CS42L43_SPI_ABORT_SHIFT 910 911 /* CS42L43_TRAN_CONFIG3 */ 912 #define CS42L43_SPI_WORD_SIZE_MASK 913 #define CS42L43_SPI_WORD_SIZE_SHIFT 914 #define CS42L43_SPI_CMD_MASK 915 #define CS42L43_SPI_CMD_SHIFT 916 917 /* CS42L43_TRAN_CONFIG4 */ 918 #define CS42L43_SPI_TX_LENGTH_MASK 919 #define CS42L43_SPI_TX_LENGTH_SHIFT 920 921 /* CS42L43_TRAN_CONFIG5 */ 922 #define CS42L43_SPI_RX_LENGTH_MASK 923 #define CS42L43_SPI_RX_LENGTH_SHIFT 924 925 /* CS42L43_TRAN_CONFIG6 */ 926 #define CS42L43_SPI_TX_BLOCK_LENGTH_MASK 927 #define CS42L43_SPI_TX_BLOCK_LENGTH_SHIFT 928 929 /* CS42L43_TRAN_CONFIG7 */ 930 #define CS42L43_SPI_RX_BLOCK_LENGTH_MASK 931 #define CS42L43_SPI_RX_BLOCK_LENGTH_SHIFT 932 933 /* CS42L43_TRAN_CONFIG8 */ 934 #define CS42L43_SPI_RX_DONE_MASK 935 #define CS42L43_SPI_RX_DONE_SHIFT 936 #define CS42L43_SPI_TX_DONE_MASK 937 #define CS42L43_SPI_TX_DONE_SHIFT 938 939 /* CS42L43_TRAN_STATUS1 */ 940 #define CS42L43_SPI_BUSY_STS_MASK 941 #define CS42L43_SPI_BUSY_STS_SHIFT 942 #define CS42L43_SPI_RX_REQUEST_MASK 943 #define CS42L43_SPI_RX_REQUEST_SHIFT 944 #define CS42L43_SPI_TX_REQUEST_MASK 945 #define CS42L43_SPI_TX_REQUEST_SHIFT 946 947 /* CS42L43_TRAN_STATUS2 */ 948 #define CS42L43_SPI_TX_BYTE_COUNT_MASK 949 #define CS42L43_SPI_TX_BYTE_COUNT_SHIFT 950 951 /* CS42L43_TRAN_STATUS3 */ 952 #define CS42L43_SPI_RX_BYTE_COUNT_MASK 953 #define CS42L43_SPI_RX_BYTE_COUNT_SHIFT 954 955 /* CS42L43_TX_DATA */ 956 #define CS42L43_SPI_TX_DATA_MASK 957 #define CS42L43_SPI_TX_DATA_SHIFT 958 959 /* CS42L43_RX_DATA */ 960 #define CS42L43_SPI_RX_DATA_MASK 961 #define CS42L43_SPI_RX_DATA_SHIFT 962 963 /* CS42L43_DACCNFG1 */ 964 #define CS42L43_HP_MSTR_VOL_CTRL_EN_MASK 965 #define CS42L43_HP_MSTR_VOL_CTRL_EN_SHIFT 966 #define CS42L43_AMP4_INV_MASK 967 #define CS42L43_AMP4_INV_SHIFT 968 #define CS42L43_AMP3_INV_MASK 969 #define CS42L43_AMP3_INV_SHIFT 970 971 /* CS42L43_DACCNFG2 */ 972 #define CS42L43_HP_AUTO_CLAMP_DISABLE_MASK 973 #define CS42L43_HP_AUTO_CLAMP_DISABLE_SHIFT 974 #define CS42L43_HP_HPF_EN_MASK 975 #define CS42L43_HP_HPF_EN_SHIFT 976 977 /* CS42L43_HPPATHVOL */ 978 #define CS42L43_AMP4_PATH_VOL_MASK 979 #define CS42L43_AMP4_PATH_VOL_SHIFT 980 #define CS42L43_AMP3_PATH_VOL_MASK 981 #define CS42L43_AMP3_PATH_VOL_SHIFT 982 983 /* CS42L43_PGAVOL */ 984 #define CS42L43_HP_PATH_VOL_RAMP_MASK 985 #define CS42L43_HP_PATH_VOL_RAMP_SHIFT 986 #define CS42L43_HP_PATH_VOL_ZC_MASK 987 #define CS42L43_HP_PATH_VOL_ZC_SHIFT 988 #define CS42L43_HP_PATH_VOL_SFT_MASK 989 #define CS42L43_HP_PATH_VOL_SFT_SHIFT 990 #define CS42L43_HP_DIG_VOL_RAMP_MASK 991 #define CS42L43_HP_DIG_VOL_RAMP_SHIFT 992 #define CS42L43_HP_ANA_VOL_RAMP_MASK 993 #define CS42L43_HP_ANA_VOL_RAMP_SHIFT 994 995 /* CS42L43_LOADDETRESULTS */ 996 #define CS42L43_AMP3_RES_DET_MASK 997 #define CS42L43_AMP3_RES_DET_SHIFT 998 999 /* CS42L43_LOADDETENA */ 1000 #define CS42L43_HPLOAD_DET_EN_MASK 1001 #define CS42L43_HPLOAD_DET_EN_SHIFT 1002 1003 /* CS42L43_CTRL */ 1004 #define CS42L43_ADPTPWR_MODE_MASK 1005 #define CS42L43_ADPTPWR_MODE_SHIFT 1006 1007 /* CS42L43_COEFF_RD_WR0 */ 1008 #define CS42L43_WRITE_MODE_MASK 1009 #define CS42L43_WRITE_MODE_SHIFT 1010 1011 /* CS42L43_INIT_DONE0 */ 1012 #define CS42L43_INITIALIZE_DONE_MASK 1013 #define CS42L43_INITIALIZE_DONE_SHIFT 1014 1015 /* CS42L43_START_EQZ0 */ 1016 #define CS42L43_START_FILTER_MASK 1017 #define CS42L43_START_FILTER_SHIFT 1018 1019 /* CS42L43_MUTE_EQ_IN0 */ 1020 #define CS42L43_MUTE_EQ_CH2_MASK 1021 #define CS42L43_MUTE_EQ_CH2_SHIFT 1022 #define CS42L43_MUTE_EQ_CH1_MASK 1023 #define CS42L43_MUTE_EQ_CH1_SHIFT 1024 1025 /* CS42L43_PLL_INT */ 1026 #define CS42L43_PLL_LOST_LOCK_INT_MASK 1027 #define CS42L43_PLL_LOST_LOCK_INT_SHIFT 1028 #define CS42L43_PLL_READY_INT_MASK 1029 #define CS42L43_PLL_READY_INT_SHIFT 1030 1031 /* CS42L43_SOFT_INT */ 1032 #define CS42L43_CONTROL_APPLIED_INT_MASK 1033 #define CS42L43_CONTROL_APPLIED_INT_SHIFT 1034 #define CS42L43_CONTROL_WARN_INT_MASK 1035 #define CS42L43_CONTROL_WARN_INT_SHIFT 1036 #define CS42L43_PATCH_WARN_INT_MASK 1037 #define CS42L43_PATCH_WARN_INT_SHIFT 1038 #define CS42L43_PATCH_APPLIED_INT_MASK 1039 #define CS42L43_PATCH_APPLIED_INT_SHIFT 1040 1041 /* CS42L43_MSM_INT */ 1042 #define CS42L43_HP_STARTUP_DONE_INT_MASK 1043 #define CS42L43_HP_STARTUP_DONE_INT_SHIFT 1044 #define CS42L43_HP_SHUTDOWN_DONE_INT_MASK 1045 #define CS42L43_HP_SHUTDOWN_DONE_INT_SHIFT 1046 #define CS42L43_HSDET_DONE_INT_MASK 1047 #define CS42L43_HSDET_DONE_INT_SHIFT 1048 #define CS42L43_TIPSENSE_UNPLUG_DB_INT_MASK 1049 #define CS42L43_TIPSENSE_UNPLUG_DB_INT_SHIFT 1050 #define CS42L43_TIPSENSE_PLUG_DB_INT_MASK 1051 #define CS42L43_TIPSENSE_PLUG_DB_INT_SHIFT 1052 #define CS42L43_RINGSENSE_UNPLUG_DB_INT_MASK 1053 #define CS42L43_RINGSENSE_UNPLUG_DB_INT_SHIFT 1054 #define CS42L43_RINGSENSE_PLUG_DB_INT_MASK 1055 #define CS42L43_RINGSENSE_PLUG_DB_INT_SHIFT 1056 #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_MASK 1057 #define CS42L43_TIPSENSE_UNPLUG_PDET_INT_SHIF 1058 #define CS42L43_TIPSENSE_PLUG_PDET_INT_MASK 1059 #define CS42L43_TIPSENSE_PLUG_PDET_INT_SHIFT 1060 #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_MAS 1061 #define CS42L43_RINGSENSE_UNPLUG_PDET_INT_SHI 1062 #define CS42L43_RINGSENSE_PLUG_PDET_INT_MASK 1063 #define CS42L43_RINGSENSE_PLUG_PDET_INT_SHIFT 1064 1065 /* CS42L43_ACC_DET_INT */ 1066 #define CS42L43_HS2_BIAS_SENSE_INT_MASK 1067 #define CS42L43_HS2_BIAS_SENSE_INT_SHIFT 1068 #define CS42L43_HS1_BIAS_SENSE_INT_MASK 1069 #define CS42L43_HS1_BIAS_SENSE_INT_SHIFT 1070 #define CS42L43_DC_DETECT1_FALSE_INT_MASK 1071 #define CS42L43_DC_DETECT1_FALSE_INT_SHIFT 1072 #define CS42L43_DC_DETECT1_TRUE_INT_MASK 1073 #define CS42L43_DC_DETECT1_TRUE_INT_SHIFT 1074 #define CS42L43_HSBIAS_CLAMPED_INT_MASK 1075 #define CS42L43_HSBIAS_CLAMPED_INT_SHIFT 1076 #define CS42L43_HS3_4_BIAS_SENSE_INT_MASK 1077 #define CS42L43_HS3_4_BIAS_SENSE_INT_SHIFT 1078 1079 /* CS42L43_SPI_MSTR_INT */ 1080 #define CS42L43_IRQ_SPI_STALLING_INT_MASK 1081 #define CS42L43_IRQ_SPI_STALLING_INT_SHIFT 1082 #define CS42L43_IRQ_SPI_STS_INT_MASK 1083 #define CS42L43_IRQ_SPI_STS_INT_SHIFT 1084 #define CS42L43_IRQ_SPI_BLOCK_INT_MASK 1085 #define CS42L43_IRQ_SPI_BLOCK_INT_SHIFT 1086 1087 /* CS42L43_SW_TO_SPI_BRIDGE_INT */ 1088 #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_MASK 1089 #define CS42L43_SW2SPI_BUF_OVF_UDF_INT_SHIFT 1090 1091 /* CS42L43_CLASS_D_AMP_INT */ 1092 #define CS42L43_AMP2_CLK_STOP_FAULT_INT_MASK 1093 #define CS42L43_AMP2_CLK_STOP_FAULT_INT_SHIFT 1094 #define CS42L43_AMP1_CLK_STOP_FAULT_INT_MASK 1095 #define CS42L43_AMP1_CLK_STOP_FAULT_INT_SHIFT 1096 #define CS42L43_AMP2_VDDSPK_FAULT_INT_MASK 1097 #define CS42L43_AMP2_VDDSPK_FAULT_INT_SHIFT 1098 #define CS42L43_AMP1_VDDSPK_FAULT_INT_MASK 1099 #define CS42L43_AMP1_VDDSPK_FAULT_INT_SHIFT 1100 #define CS42L43_AMP2_SHUTDOWN_DONE_INT_MASK 1101 #define CS42L43_AMP2_SHUTDOWN_DONE_INT_SHIFT 1102 #define CS42L43_AMP1_SHUTDOWN_DONE_INT_MASK 1103 #define CS42L43_AMP1_SHUTDOWN_DONE_INT_SHIFT 1104 #define CS42L43_AMP2_STARTUP_DONE_INT_MASK 1105 #define CS42L43_AMP2_STARTUP_DONE_INT_SHIFT 1106 #define CS42L43_AMP1_STARTUP_DONE_INT_MASK 1107 #define CS42L43_AMP1_STARTUP_DONE_INT_SHIFT 1108 #define CS42L43_AMP2_THERM_SHDN_INT_MASK 1109 #define CS42L43_AMP2_THERM_SHDN_INT_SHIFT 1110 #define CS42L43_AMP1_THERM_SHDN_INT_MASK 1111 #define CS42L43_AMP1_THERM_SHDN_INT_SHIFT 1112 #define CS42L43_AMP2_THERM_WARN_INT_MASK 1113 #define CS42L43_AMP2_THERM_WARN_INT_SHIFT 1114 #define CS42L43_AMP1_THERM_WARN_INT_MASK 1115 #define CS42L43_AMP1_THERM_WARN_INT_SHIFT 1116 #define CS42L43_AMP2_SCDET_INT_MASK 1117 #define CS42L43_AMP2_SCDET_INT_SHIFT 1118 #define CS42L43_AMP1_SCDET_INT_MASK 1119 #define CS42L43_AMP1_SCDET_INT_SHIFT 1120 1121 /* CS42L43_GPIO_INT */ 1122 #define CS42L43_GPIO3_FALL_INT_MASK 1123 #define CS42L43_GPIO3_FALL_INT_SHIFT 1124 #define CS42L43_GPIO3_RISE_INT_MASK 1125 #define CS42L43_GPIO3_RISE_INT_SHIFT 1126 #define CS42L43_GPIO2_FALL_INT_MASK 1127 #define CS42L43_GPIO2_FALL_INT_SHIFT 1128 #define CS42L43_GPIO2_RISE_INT_MASK 1129 #define CS42L43_GPIO2_RISE_INT_SHIFT 1130 #define CS42L43_GPIO1_FALL_INT_MASK 1131 #define CS42L43_GPIO1_FALL_INT_SHIFT 1132 #define CS42L43_GPIO1_RISE_INT_MASK 1133 #define CS42L43_GPIO1_RISE_INT_SHIFT 1134 1135 /* CS42L43_HPOUT_INT */ 1136 #define CS42L43_HP_ILIMIT_INT_MASK 1137 #define CS42L43_HP_ILIMIT_INT_SHIFT 1138 #define CS42L43_HP_LOADDET_DONE_INT_MASK 1139 #define CS42L43_HP_LOADDET_DONE_INT_SHIFT 1140 1141 /* CS42L43_BOOT_CONTROL */ 1142 #define CS42L43_LOCK_HW_STS_MASK 1143 #define CS42L43_LOCK_HW_STS_SHIFT 1144 1145 /* CS42L43_BLOCK_EN */ 1146 #define CS42L43_MCU_EN_MASK 1147 #define CS42L43_MCU_EN_SHIFT 1148 1149 /* CS42L43_SHUTTER_CONTROL */ 1150 #define CS42L43_STATUS_SPK_SHUTTER_MUTE_MASK 1151 #define CS42L43_STATUS_SPK_SHUTTER_MUTE_SHIFT 1152 #define CS42L43_SPK_SHUTTER_CFG_MASK 1153 #define CS42L43_SPK_SHUTTER_CFG_SHIFT 1154 #define CS42L43_STATUS_MIC_SHUTTER_MUTE_MASK 1155 #define CS42L43_STATUS_MIC_SHUTTER_MUTE_SHIFT 1156 #define CS42L43_MIC_SHUTTER_CFG_MASK 1157 #define CS42L43_MIC_SHUTTER_CFG_SHIFT 1158 1159 /* CS42L43_MCU_SW_REV */ 1160 #define CS42L43_BIOS_SUBMINOR_REV_MASK 1161 #define CS42L43_BIOS_SUBMINOR_REV_SHIFT 1162 #define CS42L43_BIOS_MINOR_REV_MASK 1163 #define CS42L43_BIOS_MINOR_REV_SHIFT 1164 #define CS42L43_BIOS_MAJOR_REV_MASK 1165 #define CS42L43_BIOS_MAJOR_REV_SHIFT 1166 #define CS42L43_FW_SUBMINOR_REV_MASK 1167 #define CS42L43_FW_SUBMINOR_REV_SHIFT 1168 #define CS42L43_FW_MINOR_REV_MASK 1169 #define CS42L43_FW_MINOR_REV_SHIFT 1170 #define CS42L43_FW_MAJOR_REV_MASK 1171 #define CS42L43_FW_MAJOR_REV_SHIFT 1172 1173 /* CS42L43_NEED_CONFIGS */ 1174 #define CS42L43_FW_PATCH_NEED_CFG_MASK 1175 #define CS42L43_FW_PATCH_NEED_CFG_SHIFT 1176 1177 /* CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION 1178 #define CS42L43_FW_MM_CTRL_MCU_SEL_MASK 1179 #define CS42L43_FW_MM_CTRL_MCU_SEL_SHIFT 1180 1181 /* CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG */ 1182 #define CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DI 1183 1184 #endif /* CS42L43_CORE_REGS_H */ 1185
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