1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 2 /* 3 * DA9150 MFD Driver - Registers 3 * DA9150 MFD Driver - Registers 4 * 4 * 5 * Copyright (c) 2014 Dialog Semiconductor 5 * Copyright (c) 2014 Dialog Semiconductor 6 * 6 * 7 * Author: Adam Thomson <Adam.Thomson.Opensour 7 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> 8 */ 8 */ 9 9 10 #ifndef __DA9150_REGISTERS_H 10 #ifndef __DA9150_REGISTERS_H 11 #define __DA9150_REGISTERS_H 11 #define __DA9150_REGISTERS_H 12 12 13 #include <linux/bitops.h> 13 #include <linux/bitops.h> 14 14 15 /* Registers */ 15 /* Registers */ 16 #define DA9150_PAGE_CON 0x000 16 #define DA9150_PAGE_CON 0x000 17 #define DA9150_STATUS_A 0x068 17 #define DA9150_STATUS_A 0x068 18 #define DA9150_STATUS_B 0x069 18 #define DA9150_STATUS_B 0x069 19 #define DA9150_STATUS_C 0x06A 19 #define DA9150_STATUS_C 0x06A 20 #define DA9150_STATUS_D 0x06B 20 #define DA9150_STATUS_D 0x06B 21 #define DA9150_STATUS_E 0x06C 21 #define DA9150_STATUS_E 0x06C 22 #define DA9150_STATUS_F 0x06D 22 #define DA9150_STATUS_F 0x06D 23 #define DA9150_STATUS_G 0x06E 23 #define DA9150_STATUS_G 0x06E 24 #define DA9150_STATUS_H 0x06F 24 #define DA9150_STATUS_H 0x06F 25 #define DA9150_STATUS_I 0x070 25 #define DA9150_STATUS_I 0x070 26 #define DA9150_STATUS_J 0x071 26 #define DA9150_STATUS_J 0x071 27 #define DA9150_STATUS_K 0x072 27 #define DA9150_STATUS_K 0x072 28 #define DA9150_STATUS_L 0x073 28 #define DA9150_STATUS_L 0x073 29 #define DA9150_STATUS_N 0x074 29 #define DA9150_STATUS_N 0x074 30 #define DA9150_FAULT_LOG_A 0x076 30 #define DA9150_FAULT_LOG_A 0x076 31 #define DA9150_FAULT_LOG_B 0x077 31 #define DA9150_FAULT_LOG_B 0x077 32 #define DA9150_EVENT_E 0x078 32 #define DA9150_EVENT_E 0x078 33 #define DA9150_EVENT_F 0x079 33 #define DA9150_EVENT_F 0x079 34 #define DA9150_EVENT_G 0x07A 34 #define DA9150_EVENT_G 0x07A 35 #define DA9150_EVENT_H 0x07B 35 #define DA9150_EVENT_H 0x07B 36 #define DA9150_IRQ_MASK_E 0x07C 36 #define DA9150_IRQ_MASK_E 0x07C 37 #define DA9150_IRQ_MASK_F 0x07D 37 #define DA9150_IRQ_MASK_F 0x07D 38 #define DA9150_IRQ_MASK_G 0x07E 38 #define DA9150_IRQ_MASK_G 0x07E 39 #define DA9150_IRQ_MASK_H 0x07F 39 #define DA9150_IRQ_MASK_H 0x07F 40 #define DA9150_PAGE_CON_1 0x080 40 #define DA9150_PAGE_CON_1 0x080 41 #define DA9150_CONFIG_A 0x0E0 41 #define DA9150_CONFIG_A 0x0E0 42 #define DA9150_CONFIG_B 0x0E1 42 #define DA9150_CONFIG_B 0x0E1 43 #define DA9150_CONFIG_C 0x0E2 43 #define DA9150_CONFIG_C 0x0E2 44 #define DA9150_CONFIG_D 0x0E3 44 #define DA9150_CONFIG_D 0x0E3 45 #define DA9150_CONFIG_E 0x0E4 45 #define DA9150_CONFIG_E 0x0E4 46 #define DA9150_CONTROL_A 0x0E5 46 #define DA9150_CONTROL_A 0x0E5 47 #define DA9150_CONTROL_B 0x0E6 47 #define DA9150_CONTROL_B 0x0E6 48 #define DA9150_CONTROL_C 0x0E7 48 #define DA9150_CONTROL_C 0x0E7 49 #define DA9150_GPIO_A_B 0x0E8 49 #define DA9150_GPIO_A_B 0x0E8 50 #define DA9150_GPIO_C_D 0x0E9 50 #define DA9150_GPIO_C_D 0x0E9 51 #define DA9150_GPIO_MODE_CONT 0x0EA 51 #define DA9150_GPIO_MODE_CONT 0x0EA 52 #define DA9150_GPIO_CTRL_B 0x0EB 52 #define DA9150_GPIO_CTRL_B 0x0EB 53 #define DA9150_GPIO_CTRL_A 0x0EC 53 #define DA9150_GPIO_CTRL_A 0x0EC 54 #define DA9150_GPIO_CTRL_C 0x0ED 54 #define DA9150_GPIO_CTRL_C 0x0ED 55 #define DA9150_GPIO_CFG_A 0x0EE 55 #define DA9150_GPIO_CFG_A 0x0EE 56 #define DA9150_GPIO_CFG_B 0x0EF 56 #define DA9150_GPIO_CFG_B 0x0EF 57 #define DA9150_GPIO_CFG_C 0x0F0 57 #define DA9150_GPIO_CFG_C 0x0F0 58 #define DA9150_GPADC_MAN 0x0F2 58 #define DA9150_GPADC_MAN 0x0F2 59 #define DA9150_GPADC_RES_A 0x0F4 59 #define DA9150_GPADC_RES_A 0x0F4 60 #define DA9150_GPADC_RES_B 0x0F5 60 #define DA9150_GPADC_RES_B 0x0F5 61 #define DA9150_PAGE_CON_2 0x100 61 #define DA9150_PAGE_CON_2 0x100 62 #define DA9150_OTP_CONT_SHARED 0x101 62 #define DA9150_OTP_CONT_SHARED 0x101 63 #define DA9150_INTERFACE_SHARED 0x105 63 #define DA9150_INTERFACE_SHARED 0x105 64 #define DA9150_CONFIG_A_SHARED 0x106 64 #define DA9150_CONFIG_A_SHARED 0x106 65 #define DA9150_CONFIG_D_SHARED 0x109 65 #define DA9150_CONFIG_D_SHARED 0x109 66 #define DA9150_ADETVB_CFG_C 0x150 66 #define DA9150_ADETVB_CFG_C 0x150 67 #define DA9150_ADETD_STAT 0x151 67 #define DA9150_ADETD_STAT 0x151 68 #define DA9150_ADET_CMPSTAT 0x152 68 #define DA9150_ADET_CMPSTAT 0x152 69 #define DA9150_ADET_CTRL_A 0x153 69 #define DA9150_ADET_CTRL_A 0x153 70 #define DA9150_ADETVB_CFG_B 0x154 70 #define DA9150_ADETVB_CFG_B 0x154 71 #define DA9150_ADETVB_CFG_A 0x155 71 #define DA9150_ADETVB_CFG_A 0x155 72 #define DA9150_ADETAC_CFG_A 0x156 72 #define DA9150_ADETAC_CFG_A 0x156 73 #define DA9150_ADDETAC_CFG_B 0x157 73 #define DA9150_ADDETAC_CFG_B 0x157 74 #define DA9150_ADETAC_CFG_C 0x158 74 #define DA9150_ADETAC_CFG_C 0x158 75 #define DA9150_ADETAC_CFG_D 0x159 75 #define DA9150_ADETAC_CFG_D 0x159 76 #define DA9150_ADETVB_CFG_D 0x15A 76 #define DA9150_ADETVB_CFG_D 0x15A 77 #define DA9150_ADETID_CFG_A 0x15B 77 #define DA9150_ADETID_CFG_A 0x15B 78 #define DA9150_ADET_RID_PT_CHG_H 0x15C 78 #define DA9150_ADET_RID_PT_CHG_H 0x15C 79 #define DA9150_ADET_RID_PT_CHG_L 0x15D 79 #define DA9150_ADET_RID_PT_CHG_L 0x15D 80 #define DA9150_PPR_TCTR_B 0x160 80 #define DA9150_PPR_TCTR_B 0x160 81 #define DA9150_PPR_BKCTRL_A 0x163 81 #define DA9150_PPR_BKCTRL_A 0x163 82 #define DA9150_PPR_BKCFG_A 0x164 82 #define DA9150_PPR_BKCFG_A 0x164 83 #define DA9150_PPR_BKCFG_B 0x165 83 #define DA9150_PPR_BKCFG_B 0x165 84 #define DA9150_PPR_CHGCTRL_A 0x166 84 #define DA9150_PPR_CHGCTRL_A 0x166 85 #define DA9150_PPR_CHGCTRL_B 0x167 85 #define DA9150_PPR_CHGCTRL_B 0x167 86 #define DA9150_PPR_CHGCTRL_C 0x168 86 #define DA9150_PPR_CHGCTRL_C 0x168 87 #define DA9150_PPR_TCTR_A 0x169 87 #define DA9150_PPR_TCTR_A 0x169 88 #define DA9150_PPR_CHGCTRL_D 0x16A 88 #define DA9150_PPR_CHGCTRL_D 0x16A 89 #define DA9150_PPR_CHGCTRL_E 0x16B 89 #define DA9150_PPR_CHGCTRL_E 0x16B 90 #define DA9150_PPR_CHGCTRL_F 0x16C 90 #define DA9150_PPR_CHGCTRL_F 0x16C 91 #define DA9150_PPR_CHGCTRL_G 0x16D 91 #define DA9150_PPR_CHGCTRL_G 0x16D 92 #define DA9150_PPR_CHGCTRL_H 0x16E 92 #define DA9150_PPR_CHGCTRL_H 0x16E 93 #define DA9150_PPR_CHGCTRL_I 0x16F 93 #define DA9150_PPR_CHGCTRL_I 0x16F 94 #define DA9150_PPR_CHGCTRL_J 0x170 94 #define DA9150_PPR_CHGCTRL_J 0x170 95 #define DA9150_PPR_CHGCTRL_K 0x171 95 #define DA9150_PPR_CHGCTRL_K 0x171 96 #define DA9150_PPR_CHGCTRL_L 0x172 96 #define DA9150_PPR_CHGCTRL_L 0x172 97 #define DA9150_PPR_CHGCTRL_M 0x173 97 #define DA9150_PPR_CHGCTRL_M 0x173 98 #define DA9150_PPR_THYST_A 0x174 98 #define DA9150_PPR_THYST_A 0x174 99 #define DA9150_PPR_THYST_B 0x175 99 #define DA9150_PPR_THYST_B 0x175 100 #define DA9150_PPR_THYST_C 0x176 100 #define DA9150_PPR_THYST_C 0x176 101 #define DA9150_PPR_THYST_D 0x177 101 #define DA9150_PPR_THYST_D 0x177 102 #define DA9150_PPR_THYST_E 0x178 102 #define DA9150_PPR_THYST_E 0x178 103 #define DA9150_PPR_THYST_F 0x179 103 #define DA9150_PPR_THYST_F 0x179 104 #define DA9150_PPR_THYST_G 0x17A 104 #define DA9150_PPR_THYST_G 0x17A 105 #define DA9150_PAGE_CON_3 0x180 105 #define DA9150_PAGE_CON_3 0x180 106 #define DA9150_PAGE_CON_4 0x200 106 #define DA9150_PAGE_CON_4 0x200 107 #define DA9150_PAGE_CON_5 0x280 107 #define DA9150_PAGE_CON_5 0x280 108 #define DA9150_PAGE_CON_6 0x300 108 #define DA9150_PAGE_CON_6 0x300 109 #define DA9150_COREBTLD_STAT_A 0x302 109 #define DA9150_COREBTLD_STAT_A 0x302 110 #define DA9150_COREBTLD_CTRL_A 0x303 110 #define DA9150_COREBTLD_CTRL_A 0x303 111 #define DA9150_CORE_CONFIG_A 0x304 111 #define DA9150_CORE_CONFIG_A 0x304 112 #define DA9150_CORE_CONFIG_C 0x305 112 #define DA9150_CORE_CONFIG_C 0x305 113 #define DA9150_CORE_CONFIG_B 0x306 113 #define DA9150_CORE_CONFIG_B 0x306 114 #define DA9150_CORE_CFG_DATA_A 0x307 114 #define DA9150_CORE_CFG_DATA_A 0x307 115 #define DA9150_CORE_CFG_DATA_B 0x308 115 #define DA9150_CORE_CFG_DATA_B 0x308 116 #define DA9150_CORE_CMD_A 0x309 116 #define DA9150_CORE_CMD_A 0x309 117 #define DA9150_CORE_DATA_A 0x30A 117 #define DA9150_CORE_DATA_A 0x30A 118 #define DA9150_CORE_DATA_B 0x30B 118 #define DA9150_CORE_DATA_B 0x30B 119 #define DA9150_CORE_DATA_C 0x30C 119 #define DA9150_CORE_DATA_C 0x30C 120 #define DA9150_CORE_DATA_D 0x30D 120 #define DA9150_CORE_DATA_D 0x30D 121 #define DA9150_CORE2WIRE_STAT_A 0x310 121 #define DA9150_CORE2WIRE_STAT_A 0x310 122 #define DA9150_CORE2WIRE_CTRL_A 0x311 122 #define DA9150_CORE2WIRE_CTRL_A 0x311 123 #define DA9150_FW_CTRL_A 0x312 123 #define DA9150_FW_CTRL_A 0x312 124 #define DA9150_FW_CTRL_C 0x313 124 #define DA9150_FW_CTRL_C 0x313 125 #define DA9150_FW_CTRL_D 0x314 125 #define DA9150_FW_CTRL_D 0x314 126 #define DA9150_FG_CTRL_A 0x315 126 #define DA9150_FG_CTRL_A 0x315 127 #define DA9150_FG_CTRL_B 0x316 127 #define DA9150_FG_CTRL_B 0x316 128 #define DA9150_FW_CTRL_E 0x317 128 #define DA9150_FW_CTRL_E 0x317 129 #define DA9150_FW_CTRL_B 0x318 129 #define DA9150_FW_CTRL_B 0x318 130 #define DA9150_GPADC_CMAN 0x320 130 #define DA9150_GPADC_CMAN 0x320 131 #define DA9150_GPADC_CRES_A 0x322 131 #define DA9150_GPADC_CRES_A 0x322 132 #define DA9150_GPADC_CRES_B 0x323 132 #define DA9150_GPADC_CRES_B 0x323 133 #define DA9150_CC_CFG_A 0x328 133 #define DA9150_CC_CFG_A 0x328 134 #define DA9150_CC_CFG_B 0x329 134 #define DA9150_CC_CFG_B 0x329 135 #define DA9150_CC_ICHG_RES_A 0x32A 135 #define DA9150_CC_ICHG_RES_A 0x32A 136 #define DA9150_CC_ICHG_RES_B 0x32B 136 #define DA9150_CC_ICHG_RES_B 0x32B 137 #define DA9150_CC_IAVG_RES_A 0x32C 137 #define DA9150_CC_IAVG_RES_A 0x32C 138 #define DA9150_CC_IAVG_RES_B 0x32D 138 #define DA9150_CC_IAVG_RES_B 0x32D 139 #define DA9150_TAUX_CTRL_A 0x330 139 #define DA9150_TAUX_CTRL_A 0x330 140 #define DA9150_TAUX_RELOAD_H 0x332 140 #define DA9150_TAUX_RELOAD_H 0x332 141 #define DA9150_TAUX_RELOAD_L 0x333 141 #define DA9150_TAUX_RELOAD_L 0x333 142 #define DA9150_TAUX_VALUE_H 0x334 142 #define DA9150_TAUX_VALUE_H 0x334 143 #define DA9150_TAUX_VALUE_L 0x335 143 #define DA9150_TAUX_VALUE_L 0x335 144 #define DA9150_AUX_DATA_0 0x338 144 #define DA9150_AUX_DATA_0 0x338 145 #define DA9150_AUX_DATA_1 0x339 145 #define DA9150_AUX_DATA_1 0x339 146 #define DA9150_AUX_DATA_2 0x33A 146 #define DA9150_AUX_DATA_2 0x33A 147 #define DA9150_AUX_DATA_3 0x33B 147 #define DA9150_AUX_DATA_3 0x33B 148 #define DA9150_BIF_CTRL 0x340 148 #define DA9150_BIF_CTRL 0x340 149 #define DA9150_TBAT_CTRL_A 0x342 149 #define DA9150_TBAT_CTRL_A 0x342 150 #define DA9150_TBAT_CTRL_B 0x343 150 #define DA9150_TBAT_CTRL_B 0x343 151 #define DA9150_TBAT_RES_A 0x344 151 #define DA9150_TBAT_RES_A 0x344 152 #define DA9150_TBAT_RES_B 0x345 152 #define DA9150_TBAT_RES_B 0x345 153 153 154 /* DA9150_PAGE_CON = 0x000 */ 154 /* DA9150_PAGE_CON = 0x000 */ 155 #define DA9150_PAGE_SHIFT 155 #define DA9150_PAGE_SHIFT 0 156 #define DA9150_PAGE_MASK 156 #define DA9150_PAGE_MASK (0x3f << 0) 157 #define DA9150_I2C_PAGE_SHIFT 157 #define DA9150_I2C_PAGE_SHIFT 1 158 #define DA9150_I2C_PAGE_MASK 158 #define DA9150_I2C_PAGE_MASK (0x1f << 1) 159 #define DA9150_WRITE_MODE_SHIFT 159 #define DA9150_WRITE_MODE_SHIFT 6 160 #define DA9150_WRITE_MODE_MASK 160 #define DA9150_WRITE_MODE_MASK BIT(6) 161 #define DA9150_REVERT_SHIFT 161 #define DA9150_REVERT_SHIFT 7 162 #define DA9150_REVERT_MASK 162 #define DA9150_REVERT_MASK BIT(7) 163 163 164 /* DA9150_STATUS_A = 0x068 */ 164 /* DA9150_STATUS_A = 0x068 */ 165 #define DA9150_WKUP_STAT_SHIFT 165 #define DA9150_WKUP_STAT_SHIFT 2 166 #define DA9150_WKUP_STAT_MASK 166 #define DA9150_WKUP_STAT_MASK (0x0f << 2) 167 #define DA9150_SLEEP_STAT_SHIFT 167 #define DA9150_SLEEP_STAT_SHIFT 6 168 #define DA9150_SLEEP_STAT_MASK 168 #define DA9150_SLEEP_STAT_MASK (0x03 << 6) 169 169 170 /* DA9150_STATUS_B = 0x069 */ 170 /* DA9150_STATUS_B = 0x069 */ 171 #define DA9150_VFAULT_STAT_SHIFT 171 #define DA9150_VFAULT_STAT_SHIFT 0 172 #define DA9150_VFAULT_STAT_MASK 172 #define DA9150_VFAULT_STAT_MASK BIT(0) 173 #define DA9150_TFAULT_STAT_SHIFT 173 #define DA9150_TFAULT_STAT_SHIFT 1 174 #define DA9150_TFAULT_STAT_MASK 174 #define DA9150_TFAULT_STAT_MASK BIT(1) 175 175 176 /* DA9150_STATUS_C = 0x06A */ 176 /* DA9150_STATUS_C = 0x06A */ 177 #define DA9150_VDD33_STAT_SHIFT 177 #define DA9150_VDD33_STAT_SHIFT 0 178 #define DA9150_VDD33_STAT_MASK 178 #define DA9150_VDD33_STAT_MASK BIT(0) 179 #define DA9150_VDD33_SLEEP_SHIFT 179 #define DA9150_VDD33_SLEEP_SHIFT 1 180 #define DA9150_VDD33_SLEEP_MASK 180 #define DA9150_VDD33_SLEEP_MASK BIT(1) 181 #define DA9150_LFOSC_STAT_SHIFT 181 #define DA9150_LFOSC_STAT_SHIFT 7 182 #define DA9150_LFOSC_STAT_MASK 182 #define DA9150_LFOSC_STAT_MASK BIT(7) 183 183 184 /* DA9150_STATUS_D = 0x06B */ 184 /* DA9150_STATUS_D = 0x06B */ 185 #define DA9150_GPIOA_STAT_SHIFT 185 #define DA9150_GPIOA_STAT_SHIFT 0 186 #define DA9150_GPIOA_STAT_MASK 186 #define DA9150_GPIOA_STAT_MASK BIT(0) 187 #define DA9150_GPIOB_STAT_SHIFT 187 #define DA9150_GPIOB_STAT_SHIFT 1 188 #define DA9150_GPIOB_STAT_MASK 188 #define DA9150_GPIOB_STAT_MASK BIT(1) 189 #define DA9150_GPIOC_STAT_SHIFT 189 #define DA9150_GPIOC_STAT_SHIFT 2 190 #define DA9150_GPIOC_STAT_MASK 190 #define DA9150_GPIOC_STAT_MASK BIT(2) 191 #define DA9150_GPIOD_STAT_SHIFT 191 #define DA9150_GPIOD_STAT_SHIFT 3 192 #define DA9150_GPIOD_STAT_MASK 192 #define DA9150_GPIOD_STAT_MASK BIT(3) 193 193 194 /* DA9150_STATUS_E = 0x06C */ 194 /* DA9150_STATUS_E = 0x06C */ 195 #define DA9150_DTYPE_SHIFT 195 #define DA9150_DTYPE_SHIFT 0 196 #define DA9150_DTYPE_MASK 196 #define DA9150_DTYPE_MASK (0x1f << 0) 197 #define DA9150_DTYPE_DT_NIL 197 #define DA9150_DTYPE_DT_NIL (0x00 << 0) 198 #define DA9150_DTYPE_DT_USB_OTG 198 #define DA9150_DTYPE_DT_USB_OTG BIT(0) 199 #define DA9150_DTYPE_DT_USB_STD 199 #define DA9150_DTYPE_DT_USB_STD (0x02 << 0) 200 #define DA9150_DTYPE_DT_USB_CHG 200 #define DA9150_DTYPE_DT_USB_CHG (0x03 << 0) 201 #define DA9150_DTYPE_DT_ACA_CHG 201 #define DA9150_DTYPE_DT_ACA_CHG (0x04 << 0) 202 #define DA9150_DTYPE_DT_ACA_OTG 202 #define DA9150_DTYPE_DT_ACA_OTG (0x05 << 0) 203 #define DA9150_DTYPE_DT_ACA_DOC 203 #define DA9150_DTYPE_DT_ACA_DOC (0x06 << 0) 204 #define DA9150_DTYPE_DT_DED_CHG 204 #define DA9150_DTYPE_DT_DED_CHG (0x07 << 0) 205 #define DA9150_DTYPE_DT_CR5_CHG 205 #define DA9150_DTYPE_DT_CR5_CHG (0x08 << 0) 206 #define DA9150_DTYPE_DT_CR4_CHG 206 #define DA9150_DTYPE_DT_CR4_CHG (0x0c << 0) 207 #define DA9150_DTYPE_DT_PT_CHG 207 #define DA9150_DTYPE_DT_PT_CHG (0x11 << 0) 208 #define DA9150_DTYPE_DT_NN_ACC 208 #define DA9150_DTYPE_DT_NN_ACC (0x16 << 0) 209 #define DA9150_DTYPE_DT_NN_CHG 209 #define DA9150_DTYPE_DT_NN_CHG (0x17 << 0) 210 210 211 /* DA9150_STATUS_F = 0x06D */ 211 /* DA9150_STATUS_F = 0x06D */ 212 #define DA9150_SESS_VLD_SHIFT 212 #define DA9150_SESS_VLD_SHIFT 0 213 #define DA9150_SESS_VLD_MASK 213 #define DA9150_SESS_VLD_MASK BIT(0) 214 #define DA9150_ID_ERR_SHIFT 214 #define DA9150_ID_ERR_SHIFT 1 215 #define DA9150_ID_ERR_MASK 215 #define DA9150_ID_ERR_MASK BIT(1) 216 #define DA9150_PT_CHG_SHIFT 216 #define DA9150_PT_CHG_SHIFT 2 217 #define DA9150_PT_CHG_MASK 217 #define DA9150_PT_CHG_MASK BIT(2) 218 218 219 /* DA9150_STATUS_G = 0x06E */ 219 /* DA9150_STATUS_G = 0x06E */ 220 #define DA9150_RID_SHIFT 220 #define DA9150_RID_SHIFT 0 221 #define DA9150_RID_MASK 221 #define DA9150_RID_MASK (0xff << 0) 222 222 223 /* DA9150_STATUS_H = 0x06F */ 223 /* DA9150_STATUS_H = 0x06F */ 224 #define DA9150_VBUS_STAT_SHIFT 224 #define DA9150_VBUS_STAT_SHIFT 0 225 #define DA9150_VBUS_STAT_MASK 225 #define DA9150_VBUS_STAT_MASK (0x07 << 0) 226 #define DA9150_VBUS_STAT_OFF 226 #define DA9150_VBUS_STAT_OFF (0x00 << 0) 227 #define DA9150_VBUS_STAT_WAIT 227 #define DA9150_VBUS_STAT_WAIT BIT(0) 228 #define DA9150_VBUS_STAT_CHG 228 #define DA9150_VBUS_STAT_CHG (0x02 << 0) 229 #define DA9150_VBUS_TRED_SHIFT 229 #define DA9150_VBUS_TRED_SHIFT 3 230 #define DA9150_VBUS_TRED_MASK 230 #define DA9150_VBUS_TRED_MASK BIT(3) 231 #define DA9150_VBUS_DROP_STAT_SHIFT 231 #define DA9150_VBUS_DROP_STAT_SHIFT 4 232 #define DA9150_VBUS_DROP_STAT_MASK 232 #define DA9150_VBUS_DROP_STAT_MASK (0x0f << 4) 233 233 234 /* DA9150_STATUS_I = 0x070 */ 234 /* DA9150_STATUS_I = 0x070 */ 235 #define DA9150_VBUS_ISET_STAT_SHIFT 235 #define DA9150_VBUS_ISET_STAT_SHIFT 0 236 #define DA9150_VBUS_ISET_STAT_MASK 236 #define DA9150_VBUS_ISET_STAT_MASK (0x1f << 0) 237 #define DA9150_VBUS_OT_SHIFT 237 #define DA9150_VBUS_OT_SHIFT 7 238 #define DA9150_VBUS_OT_MASK 238 #define DA9150_VBUS_OT_MASK BIT(7) 239 239 240 /* DA9150_STATUS_J = 0x071 */ 240 /* DA9150_STATUS_J = 0x071 */ 241 #define DA9150_CHG_STAT_SHIFT 241 #define DA9150_CHG_STAT_SHIFT 0 242 #define DA9150_CHG_STAT_MASK 242 #define DA9150_CHG_STAT_MASK (0x0f << 0) 243 #define DA9150_CHG_STAT_OFF 243 #define DA9150_CHG_STAT_OFF (0x00 << 0) 244 #define DA9150_CHG_STAT_SUSP 244 #define DA9150_CHG_STAT_SUSP BIT(0) 245 #define DA9150_CHG_STAT_ACT 245 #define DA9150_CHG_STAT_ACT (0x02 << 0) 246 #define DA9150_CHG_STAT_PRE 246 #define DA9150_CHG_STAT_PRE (0x03 << 0) 247 #define DA9150_CHG_STAT_CC 247 #define DA9150_CHG_STAT_CC (0x04 << 0) 248 #define DA9150_CHG_STAT_CV 248 #define DA9150_CHG_STAT_CV (0x05 << 0) 249 #define DA9150_CHG_STAT_FULL 249 #define DA9150_CHG_STAT_FULL (0x06 << 0) 250 #define DA9150_CHG_STAT_TEMP 250 #define DA9150_CHG_STAT_TEMP (0x07 << 0) 251 #define DA9150_CHG_STAT_TIME 251 #define DA9150_CHG_STAT_TIME (0x08 << 0) 252 #define DA9150_CHG_STAT_BAT 252 #define DA9150_CHG_STAT_BAT (0x09 << 0) 253 #define DA9150_CHG_TEMP_SHIFT 253 #define DA9150_CHG_TEMP_SHIFT 4 254 #define DA9150_CHG_TEMP_MASK 254 #define DA9150_CHG_TEMP_MASK (0x07 << 4) 255 #define DA9150_CHG_TEMP_UNDER 255 #define DA9150_CHG_TEMP_UNDER (0x06 << 4) 256 #define DA9150_CHG_TEMP_OVER 256 #define DA9150_CHG_TEMP_OVER (0x07 << 4) 257 #define DA9150_CHG_IEND_STAT_SHIFT 257 #define DA9150_CHG_IEND_STAT_SHIFT 7 258 #define DA9150_CHG_IEND_STAT_MASK 258 #define DA9150_CHG_IEND_STAT_MASK BIT(7) 259 259 260 /* DA9150_STATUS_K = 0x072 */ 260 /* DA9150_STATUS_K = 0x072 */ 261 #define DA9150_CHG_IAV_H_SHIFT 261 #define DA9150_CHG_IAV_H_SHIFT 0 262 #define DA9150_CHG_IAV_H_MASK 262 #define DA9150_CHG_IAV_H_MASK (0xff << 0) 263 263 264 /* DA9150_STATUS_L = 0x073 */ 264 /* DA9150_STATUS_L = 0x073 */ 265 #define DA9150_CHG_IAV_L_SHIFT 265 #define DA9150_CHG_IAV_L_SHIFT 5 266 #define DA9150_CHG_IAV_L_MASK 266 #define DA9150_CHG_IAV_L_MASK (0x07 << 5) 267 267 268 /* DA9150_STATUS_N = 0x074 */ 268 /* DA9150_STATUS_N = 0x074 */ 269 #define DA9150_CHG_TIME_SHIFT 269 #define DA9150_CHG_TIME_SHIFT 1 270 #define DA9150_CHG_TIME_MASK 270 #define DA9150_CHG_TIME_MASK BIT(1) 271 #define DA9150_CHG_TRED_SHIFT 271 #define DA9150_CHG_TRED_SHIFT 2 272 #define DA9150_CHG_TRED_MASK 272 #define DA9150_CHG_TRED_MASK BIT(2) 273 #define DA9150_CHG_TJUNC_CLASS_SHIFT 273 #define DA9150_CHG_TJUNC_CLASS_SHIFT 3 274 #define DA9150_CHG_TJUNC_CLASS_MASK 274 #define DA9150_CHG_TJUNC_CLASS_MASK (0x07 << 3) 275 #define DA9150_CHG_TJUNC_CLASS_6 275 #define DA9150_CHG_TJUNC_CLASS_6 (0x06 << 3) 276 #define DA9150_EBS_STAT_SHIFT 276 #define DA9150_EBS_STAT_SHIFT 6 277 #define DA9150_EBS_STAT_MASK 277 #define DA9150_EBS_STAT_MASK BIT(6) 278 #define DA9150_CHG_BAT_REMOVED_SHIFT 278 #define DA9150_CHG_BAT_REMOVED_SHIFT 7 279 #define DA9150_CHG_BAT_REMOVED_MASK 279 #define DA9150_CHG_BAT_REMOVED_MASK BIT(7) 280 280 281 /* DA9150_FAULT_LOG_A = 0x076 */ 281 /* DA9150_FAULT_LOG_A = 0x076 */ 282 #define DA9150_TEMP_FAULT_SHIFT 282 #define DA9150_TEMP_FAULT_SHIFT 0 283 #define DA9150_TEMP_FAULT_MASK 283 #define DA9150_TEMP_FAULT_MASK BIT(0) 284 #define DA9150_VSYS_FAULT_SHIFT 284 #define DA9150_VSYS_FAULT_SHIFT 1 285 #define DA9150_VSYS_FAULT_MASK 285 #define DA9150_VSYS_FAULT_MASK BIT(1) 286 #define DA9150_START_FAULT_SHIFT 286 #define DA9150_START_FAULT_SHIFT 2 287 #define DA9150_START_FAULT_MASK 287 #define DA9150_START_FAULT_MASK BIT(2) 288 #define DA9150_EXT_FAULT_SHIFT 288 #define DA9150_EXT_FAULT_SHIFT 3 289 #define DA9150_EXT_FAULT_MASK 289 #define DA9150_EXT_FAULT_MASK BIT(3) 290 #define DA9150_POR_FAULT_SHIFT 290 #define DA9150_POR_FAULT_SHIFT 4 291 #define DA9150_POR_FAULT_MASK 291 #define DA9150_POR_FAULT_MASK BIT(4) 292 292 293 /* DA9150_FAULT_LOG_B = 0x077 */ 293 /* DA9150_FAULT_LOG_B = 0x077 */ 294 #define DA9150_VBUS_FAULT_SHIFT 294 #define DA9150_VBUS_FAULT_SHIFT 0 295 #define DA9150_VBUS_FAULT_MASK 295 #define DA9150_VBUS_FAULT_MASK BIT(0) 296 #define DA9150_OTG_FAULT_SHIFT 296 #define DA9150_OTG_FAULT_SHIFT 1 297 #define DA9150_OTG_FAULT_MASK 297 #define DA9150_OTG_FAULT_MASK BIT(1) 298 298 299 /* DA9150_EVENT_E = 0x078 */ 299 /* DA9150_EVENT_E = 0x078 */ 300 #define DA9150_E_VBUS_SHIFT 300 #define DA9150_E_VBUS_SHIFT 0 301 #define DA9150_E_VBUS_MASK 301 #define DA9150_E_VBUS_MASK BIT(0) 302 #define DA9150_E_CHG_SHIFT 302 #define DA9150_E_CHG_SHIFT 1 303 #define DA9150_E_CHG_MASK 303 #define DA9150_E_CHG_MASK BIT(1) 304 #define DA9150_E_TCLASS_SHIFT 304 #define DA9150_E_TCLASS_SHIFT 2 305 #define DA9150_E_TCLASS_MASK 305 #define DA9150_E_TCLASS_MASK BIT(2) 306 #define DA9150_E_TJUNC_SHIFT 306 #define DA9150_E_TJUNC_SHIFT 3 307 #define DA9150_E_TJUNC_MASK 307 #define DA9150_E_TJUNC_MASK BIT(3) 308 #define DA9150_E_VFAULT_SHIFT 308 #define DA9150_E_VFAULT_SHIFT 4 309 #define DA9150_E_VFAULT_MASK 309 #define DA9150_E_VFAULT_MASK BIT(4) 310 #define DA9150_EVENTS_H_SHIFT 310 #define DA9150_EVENTS_H_SHIFT 5 311 #define DA9150_EVENTS_H_MASK 311 #define DA9150_EVENTS_H_MASK BIT(5) 312 #define DA9150_EVENTS_G_SHIFT 312 #define DA9150_EVENTS_G_SHIFT 6 313 #define DA9150_EVENTS_G_MASK 313 #define DA9150_EVENTS_G_MASK BIT(6) 314 #define DA9150_EVENTS_F_SHIFT 314 #define DA9150_EVENTS_F_SHIFT 7 315 #define DA9150_EVENTS_F_MASK 315 #define DA9150_EVENTS_F_MASK BIT(7) 316 316 317 /* DA9150_EVENT_F = 0x079 */ 317 /* DA9150_EVENT_F = 0x079 */ 318 #define DA9150_E_CONF_SHIFT 318 #define DA9150_E_CONF_SHIFT 0 319 #define DA9150_E_CONF_MASK 319 #define DA9150_E_CONF_MASK BIT(0) 320 #define DA9150_E_DAT_SHIFT 320 #define DA9150_E_DAT_SHIFT 1 321 #define DA9150_E_DAT_MASK 321 #define DA9150_E_DAT_MASK BIT(1) 322 #define DA9150_E_DTYPE_SHIFT 322 #define DA9150_E_DTYPE_SHIFT 3 323 #define DA9150_E_DTYPE_MASK 323 #define DA9150_E_DTYPE_MASK BIT(3) 324 #define DA9150_E_ID_SHIFT 324 #define DA9150_E_ID_SHIFT 4 325 #define DA9150_E_ID_MASK 325 #define DA9150_E_ID_MASK BIT(4) 326 #define DA9150_E_ADP_SHIFT 326 #define DA9150_E_ADP_SHIFT 5 327 #define DA9150_E_ADP_MASK 327 #define DA9150_E_ADP_MASK BIT(5) 328 #define DA9150_E_SESS_END_SHIFT 328 #define DA9150_E_SESS_END_SHIFT 6 329 #define DA9150_E_SESS_END_MASK 329 #define DA9150_E_SESS_END_MASK BIT(6) 330 #define DA9150_E_SESS_VLD_SHIFT 330 #define DA9150_E_SESS_VLD_SHIFT 7 331 #define DA9150_E_SESS_VLD_MASK 331 #define DA9150_E_SESS_VLD_MASK BIT(7) 332 332 333 /* DA9150_EVENT_G = 0x07A */ 333 /* DA9150_EVENT_G = 0x07A */ 334 #define DA9150_E_FG_SHIFT 334 #define DA9150_E_FG_SHIFT 0 335 #define DA9150_E_FG_MASK 335 #define DA9150_E_FG_MASK BIT(0) 336 #define DA9150_E_GP_SHIFT 336 #define DA9150_E_GP_SHIFT 1 337 #define DA9150_E_GP_MASK 337 #define DA9150_E_GP_MASK BIT(1) 338 #define DA9150_E_TBAT_SHIFT 338 #define DA9150_E_TBAT_SHIFT 2 339 #define DA9150_E_TBAT_MASK 339 #define DA9150_E_TBAT_MASK BIT(2) 340 #define DA9150_E_GPIOA_SHIFT 340 #define DA9150_E_GPIOA_SHIFT 3 341 #define DA9150_E_GPIOA_MASK 341 #define DA9150_E_GPIOA_MASK BIT(3) 342 #define DA9150_E_GPIOB_SHIFT 342 #define DA9150_E_GPIOB_SHIFT 4 343 #define DA9150_E_GPIOB_MASK 343 #define DA9150_E_GPIOB_MASK BIT(4) 344 #define DA9150_E_GPIOC_SHIFT 344 #define DA9150_E_GPIOC_SHIFT 5 345 #define DA9150_E_GPIOC_MASK 345 #define DA9150_E_GPIOC_MASK BIT(5) 346 #define DA9150_E_GPIOD_SHIFT 346 #define DA9150_E_GPIOD_SHIFT 6 347 #define DA9150_E_GPIOD_MASK 347 #define DA9150_E_GPIOD_MASK BIT(6) 348 #define DA9150_E_GPADC_SHIFT 348 #define DA9150_E_GPADC_SHIFT 7 349 #define DA9150_E_GPADC_MASK 349 #define DA9150_E_GPADC_MASK BIT(7) 350 350 351 /* DA9150_EVENT_H = 0x07B */ 351 /* DA9150_EVENT_H = 0x07B */ 352 #define DA9150_E_WKUP_SHIFT 352 #define DA9150_E_WKUP_SHIFT 0 353 #define DA9150_E_WKUP_MASK 353 #define DA9150_E_WKUP_MASK BIT(0) 354 354 355 /* DA9150_IRQ_MASK_E = 0x07C */ 355 /* DA9150_IRQ_MASK_E = 0x07C */ 356 #define DA9150_M_VBUS_SHIFT 356 #define DA9150_M_VBUS_SHIFT 0 357 #define DA9150_M_VBUS_MASK 357 #define DA9150_M_VBUS_MASK BIT(0) 358 #define DA9150_M_CHG_SHIFT 358 #define DA9150_M_CHG_SHIFT 1 359 #define DA9150_M_CHG_MASK 359 #define DA9150_M_CHG_MASK BIT(1) 360 #define DA9150_M_TJUNC_SHIFT 360 #define DA9150_M_TJUNC_SHIFT 3 361 #define DA9150_M_TJUNC_MASK 361 #define DA9150_M_TJUNC_MASK BIT(3) 362 #define DA9150_M_VFAULT_SHIFT 362 #define DA9150_M_VFAULT_SHIFT 4 363 #define DA9150_M_VFAULT_MASK 363 #define DA9150_M_VFAULT_MASK BIT(4) 364 364 365 /* DA9150_IRQ_MASK_F = 0x07D */ 365 /* DA9150_IRQ_MASK_F = 0x07D */ 366 #define DA9150_M_CONF_SHIFT 366 #define DA9150_M_CONF_SHIFT 0 367 #define DA9150_M_CONF_MASK 367 #define DA9150_M_CONF_MASK BIT(0) 368 #define DA9150_M_DAT_SHIFT 368 #define DA9150_M_DAT_SHIFT 1 369 #define DA9150_M_DAT_MASK 369 #define DA9150_M_DAT_MASK BIT(1) 370 #define DA9150_M_DTYPE_SHIFT 370 #define DA9150_M_DTYPE_SHIFT 3 371 #define DA9150_M_DTYPE_MASK 371 #define DA9150_M_DTYPE_MASK BIT(3) 372 #define DA9150_M_ID_SHIFT 372 #define DA9150_M_ID_SHIFT 4 373 #define DA9150_M_ID_MASK 373 #define DA9150_M_ID_MASK BIT(4) 374 #define DA9150_M_ADP_SHIFT 374 #define DA9150_M_ADP_SHIFT 5 375 #define DA9150_M_ADP_MASK 375 #define DA9150_M_ADP_MASK BIT(5) 376 #define DA9150_M_SESS_END_SHIFT 376 #define DA9150_M_SESS_END_SHIFT 6 377 #define DA9150_M_SESS_END_MASK 377 #define DA9150_M_SESS_END_MASK BIT(6) 378 #define DA9150_M_SESS_VLD_SHIFT 378 #define DA9150_M_SESS_VLD_SHIFT 7 379 #define DA9150_M_SESS_VLD_MASK 379 #define DA9150_M_SESS_VLD_MASK BIT(7) 380 380 381 /* DA9150_IRQ_MASK_G = 0x07E */ 381 /* DA9150_IRQ_MASK_G = 0x07E */ 382 #define DA9150_M_FG_SHIFT 382 #define DA9150_M_FG_SHIFT 0 383 #define DA9150_M_FG_MASK 383 #define DA9150_M_FG_MASK BIT(0) 384 #define DA9150_M_GP_SHIFT 384 #define DA9150_M_GP_SHIFT 1 385 #define DA9150_M_GP_MASK 385 #define DA9150_M_GP_MASK BIT(1) 386 #define DA9150_M_TBAT_SHIFT 386 #define DA9150_M_TBAT_SHIFT 2 387 #define DA9150_M_TBAT_MASK 387 #define DA9150_M_TBAT_MASK BIT(2) 388 #define DA9150_M_GPIOA_SHIFT 388 #define DA9150_M_GPIOA_SHIFT 3 389 #define DA9150_M_GPIOA_MASK 389 #define DA9150_M_GPIOA_MASK BIT(3) 390 #define DA9150_M_GPIOB_SHIFT 390 #define DA9150_M_GPIOB_SHIFT 4 391 #define DA9150_M_GPIOB_MASK 391 #define DA9150_M_GPIOB_MASK BIT(4) 392 #define DA9150_M_GPIOC_SHIFT 392 #define DA9150_M_GPIOC_SHIFT 5 393 #define DA9150_M_GPIOC_MASK 393 #define DA9150_M_GPIOC_MASK BIT(5) 394 #define DA9150_M_GPIOD_SHIFT 394 #define DA9150_M_GPIOD_SHIFT 6 395 #define DA9150_M_GPIOD_MASK 395 #define DA9150_M_GPIOD_MASK BIT(6) 396 #define DA9150_M_GPADC_SHIFT 396 #define DA9150_M_GPADC_SHIFT 7 397 #define DA9150_M_GPADC_MASK 397 #define DA9150_M_GPADC_MASK BIT(7) 398 398 399 /* DA9150_IRQ_MASK_H = 0x07F */ 399 /* DA9150_IRQ_MASK_H = 0x07F */ 400 #define DA9150_M_WKUP_SHIFT 400 #define DA9150_M_WKUP_SHIFT 0 401 #define DA9150_M_WKUP_MASK 401 #define DA9150_M_WKUP_MASK BIT(0) 402 402 403 /* DA9150_PAGE_CON_1 = 0x080 */ 403 /* DA9150_PAGE_CON_1 = 0x080 */ 404 #define DA9150_PAGE_SHIFT 404 #define DA9150_PAGE_SHIFT 0 405 #define DA9150_PAGE_MASK 405 #define DA9150_PAGE_MASK (0x3f << 0) 406 #define DA9150_WRITE_MODE_SHIFT 406 #define DA9150_WRITE_MODE_SHIFT 6 407 #define DA9150_WRITE_MODE_MASK 407 #define DA9150_WRITE_MODE_MASK BIT(6) 408 #define DA9150_REVERT_SHIFT 408 #define DA9150_REVERT_SHIFT 7 409 #define DA9150_REVERT_MASK 409 #define DA9150_REVERT_MASK BIT(7) 410 410 411 /* DA9150_CONFIG_A = 0x0E0 */ 411 /* DA9150_CONFIG_A = 0x0E0 */ 412 #define DA9150_RESET_DUR_SHIFT 412 #define DA9150_RESET_DUR_SHIFT 0 413 #define DA9150_RESET_DUR_MASK 413 #define DA9150_RESET_DUR_MASK (0x03 << 0) 414 #define DA9150_RESET_EXT_SHIFT 414 #define DA9150_RESET_EXT_SHIFT 2 415 #define DA9150_RESET_EXT_MASK 415 #define DA9150_RESET_EXT_MASK (0x03 << 2) 416 #define DA9150_START_MAX_SHIFT 416 #define DA9150_START_MAX_SHIFT 4 417 #define DA9150_START_MAX_MASK 417 #define DA9150_START_MAX_MASK (0x03 << 4) 418 #define DA9150_PS_WAIT_EN_SHIFT 418 #define DA9150_PS_WAIT_EN_SHIFT 6 419 #define DA9150_PS_WAIT_EN_MASK 419 #define DA9150_PS_WAIT_EN_MASK BIT(6) 420 #define DA9150_PS_DISABLE_DIRECT_SHIFT 420 #define DA9150_PS_DISABLE_DIRECT_SHIFT 7 421 #define DA9150_PS_DISABLE_DIRECT_MASK 421 #define DA9150_PS_DISABLE_DIRECT_MASK BIT(7) 422 422 423 /* DA9150_CONFIG_B = 0x0E1 */ 423 /* DA9150_CONFIG_B = 0x0E1 */ 424 #define DA9150_VFAULT_ADJ_SHIFT 424 #define DA9150_VFAULT_ADJ_SHIFT 0 425 #define DA9150_VFAULT_ADJ_MASK 425 #define DA9150_VFAULT_ADJ_MASK (0x0f << 0) 426 #define DA9150_VFAULT_HYST_SHIFT 426 #define DA9150_VFAULT_HYST_SHIFT 4 427 #define DA9150_VFAULT_HYST_MASK 427 #define DA9150_VFAULT_HYST_MASK (0x07 << 4) 428 #define DA9150_VFAULT_EN_SHIFT 428 #define DA9150_VFAULT_EN_SHIFT 7 429 #define DA9150_VFAULT_EN_MASK 429 #define DA9150_VFAULT_EN_MASK BIT(7) 430 430 431 /* DA9150_CONFIG_C = 0x0E2 */ 431 /* DA9150_CONFIG_C = 0x0E2 */ 432 #define DA9150_VSYS_MIN_SHIFT 432 #define DA9150_VSYS_MIN_SHIFT 3 433 #define DA9150_VSYS_MIN_MASK 433 #define DA9150_VSYS_MIN_MASK (0x1f << 3) 434 434 435 /* DA9150_CONFIG_D = 0x0E3 */ 435 /* DA9150_CONFIG_D = 0x0E3 */ 436 #define DA9150_LFOSC_EXT_SHIFT 436 #define DA9150_LFOSC_EXT_SHIFT 0 437 #define DA9150_LFOSC_EXT_MASK 437 #define DA9150_LFOSC_EXT_MASK BIT(0) 438 #define DA9150_VDD33_DWN_SHIFT 438 #define DA9150_VDD33_DWN_SHIFT 1 439 #define DA9150_VDD33_DWN_MASK 439 #define DA9150_VDD33_DWN_MASK BIT(1) 440 #define DA9150_WKUP_PM_EN_SHIFT 440 #define DA9150_WKUP_PM_EN_SHIFT 2 441 #define DA9150_WKUP_PM_EN_MASK 441 #define DA9150_WKUP_PM_EN_MASK BIT(2) 442 #define DA9150_WKUP_CE_SEL_SHIFT 442 #define DA9150_WKUP_CE_SEL_SHIFT 3 443 #define DA9150_WKUP_CE_SEL_MASK 443 #define DA9150_WKUP_CE_SEL_MASK (0x03 << 3) 444 #define DA9150_WKUP_CLK32K_EN_SHIFT 444 #define DA9150_WKUP_CLK32K_EN_SHIFT 5 445 #define DA9150_WKUP_CLK32K_EN_MASK 445 #define DA9150_WKUP_CLK32K_EN_MASK BIT(5) 446 #define DA9150_DISABLE_DEL_SHIFT 446 #define DA9150_DISABLE_DEL_SHIFT 7 447 #define DA9150_DISABLE_DEL_MASK 447 #define DA9150_DISABLE_DEL_MASK BIT(7) 448 448 449 /* DA9150_CONFIG_E = 0x0E4 */ 449 /* DA9150_CONFIG_E = 0x0E4 */ 450 #define DA9150_PM_SPKSUP_DIS_SHIFT 450 #define DA9150_PM_SPKSUP_DIS_SHIFT 0 451 #define DA9150_PM_SPKSUP_DIS_MASK 451 #define DA9150_PM_SPKSUP_DIS_MASK BIT(0) 452 #define DA9150_PM_MERGE_SHIFT 452 #define DA9150_PM_MERGE_SHIFT 1 453 #define DA9150_PM_MERGE_MASK 453 #define DA9150_PM_MERGE_MASK BIT(1) 454 #define DA9150_PM_SR_OFF_SHIFT 454 #define DA9150_PM_SR_OFF_SHIFT 2 455 #define DA9150_PM_SR_OFF_MASK 455 #define DA9150_PM_SR_OFF_MASK BIT(2) 456 #define DA9150_PM_TIMEOUT_EN_SHIFT 456 #define DA9150_PM_TIMEOUT_EN_SHIFT 3 457 #define DA9150_PM_TIMEOUT_EN_MASK 457 #define DA9150_PM_TIMEOUT_EN_MASK BIT(3) 458 #define DA9150_PM_DLY_SEL_SHIFT 458 #define DA9150_PM_DLY_SEL_SHIFT 4 459 #define DA9150_PM_DLY_SEL_MASK 459 #define DA9150_PM_DLY_SEL_MASK (0x07 << 4) 460 #define DA9150_PM_OUT_DLY_SEL_SHIFT 460 #define DA9150_PM_OUT_DLY_SEL_SHIFT 7 461 #define DA9150_PM_OUT_DLY_SEL_MASK 461 #define DA9150_PM_OUT_DLY_SEL_MASK BIT(7) 462 462 463 /* DA9150_CONTROL_A = 0x0E5 */ 463 /* DA9150_CONTROL_A = 0x0E5 */ 464 #define DA9150_VDD33_SL_SHIFT 464 #define DA9150_VDD33_SL_SHIFT 0 465 #define DA9150_VDD33_SL_MASK 465 #define DA9150_VDD33_SL_MASK BIT(0) 466 #define DA9150_VDD33_LPM_SHIFT 466 #define DA9150_VDD33_LPM_SHIFT 1 467 #define DA9150_VDD33_LPM_MASK 467 #define DA9150_VDD33_LPM_MASK (0x03 << 1) 468 #define DA9150_VDD33_EN_SHIFT 468 #define DA9150_VDD33_EN_SHIFT 3 469 #define DA9150_VDD33_EN_MASK 469 #define DA9150_VDD33_EN_MASK BIT(3) 470 #define DA9150_GPI_LPM_SHIFT 470 #define DA9150_GPI_LPM_SHIFT 6 471 #define DA9150_GPI_LPM_MASK 471 #define DA9150_GPI_LPM_MASK BIT(6) 472 #define DA9150_PM_IF_LPM_SHIFT 472 #define DA9150_PM_IF_LPM_SHIFT 7 473 #define DA9150_PM_IF_LPM_MASK 473 #define DA9150_PM_IF_LPM_MASK BIT(7) 474 474 475 /* DA9150_CONTROL_B = 0x0E6 */ 475 /* DA9150_CONTROL_B = 0x0E6 */ 476 #define DA9150_LPM_SHIFT 476 #define DA9150_LPM_SHIFT 0 477 #define DA9150_LPM_MASK 477 #define DA9150_LPM_MASK BIT(0) 478 #define DA9150_RESET_SHIFT 478 #define DA9150_RESET_SHIFT 1 479 #define DA9150_RESET_MASK 479 #define DA9150_RESET_MASK BIT(1) 480 #define DA9150_RESET_USRCONF_EN_SHIFT 480 #define DA9150_RESET_USRCONF_EN_SHIFT 2 481 #define DA9150_RESET_USRCONF_EN_MASK 481 #define DA9150_RESET_USRCONF_EN_MASK BIT(2) 482 482 483 /* DA9150_CONTROL_C = 0x0E7 */ 483 /* DA9150_CONTROL_C = 0x0E7 */ 484 #define DA9150_DISABLE_SHIFT 484 #define DA9150_DISABLE_SHIFT 0 485 #define DA9150_DISABLE_MASK 485 #define DA9150_DISABLE_MASK BIT(0) 486 486 487 /* DA9150_GPIO_A_B = 0x0E8 */ 487 /* DA9150_GPIO_A_B = 0x0E8 */ 488 #define DA9150_GPIOA_PIN_SHIFT 488 #define DA9150_GPIOA_PIN_SHIFT 0 489 #define DA9150_GPIOA_PIN_MASK 489 #define DA9150_GPIOA_PIN_MASK (0x07 << 0) 490 #define DA9150_GPIOA_PIN_GPI 490 #define DA9150_GPIOA_PIN_GPI (0x00 << 0) 491 #define DA9150_GPIOA_PIN_GPO_OD 491 #define DA9150_GPIOA_PIN_GPO_OD BIT(0) 492 #define DA9150_GPIOA_TYPE_SHIFT 492 #define DA9150_GPIOA_TYPE_SHIFT 3 493 #define DA9150_GPIOA_TYPE_MASK 493 #define DA9150_GPIOA_TYPE_MASK BIT(3) 494 #define DA9150_GPIOB_PIN_SHIFT 494 #define DA9150_GPIOB_PIN_SHIFT 4 495 #define DA9150_GPIOB_PIN_MASK 495 #define DA9150_GPIOB_PIN_MASK (0x07 << 4) 496 #define DA9150_GPIOB_PIN_GPI 496 #define DA9150_GPIOB_PIN_GPI (0x00 << 4) 497 #define DA9150_GPIOB_PIN_GPO_OD 497 #define DA9150_GPIOB_PIN_GPO_OD BIT(4) 498 #define DA9150_GPIOB_TYPE_SHIFT 498 #define DA9150_GPIOB_TYPE_SHIFT 7 499 #define DA9150_GPIOB_TYPE_MASK 499 #define DA9150_GPIOB_TYPE_MASK BIT(7) 500 500 501 /* DA9150_GPIO_C_D = 0x0E9 */ 501 /* DA9150_GPIO_C_D = 0x0E9 */ 502 #define DA9150_GPIOC_PIN_SHIFT 502 #define DA9150_GPIOC_PIN_SHIFT 0 503 #define DA9150_GPIOC_PIN_MASK 503 #define DA9150_GPIOC_PIN_MASK (0x07 << 0) 504 #define DA9150_GPIOC_PIN_GPI 504 #define DA9150_GPIOC_PIN_GPI (0x00 << 0) 505 #define DA9150_GPIOC_PIN_GPO_OD 505 #define DA9150_GPIOC_PIN_GPO_OD BIT(0) 506 #define DA9150_GPIOC_TYPE_SHIFT 506 #define DA9150_GPIOC_TYPE_SHIFT 3 507 #define DA9150_GPIOC_TYPE_MASK 507 #define DA9150_GPIOC_TYPE_MASK BIT(3) 508 #define DA9150_GPIOD_PIN_SHIFT 508 #define DA9150_GPIOD_PIN_SHIFT 4 509 #define DA9150_GPIOD_PIN_MASK 509 #define DA9150_GPIOD_PIN_MASK (0x07 << 4) 510 #define DA9150_GPIOD_PIN_GPI 510 #define DA9150_GPIOD_PIN_GPI (0x00 << 4) 511 #define DA9150_GPIOD_PIN_GPO_OD 511 #define DA9150_GPIOD_PIN_GPO_OD BIT(4) 512 #define DA9150_GPIOD_TYPE_SHIFT 512 #define DA9150_GPIOD_TYPE_SHIFT 7 513 #define DA9150_GPIOD_TYPE_MASK 513 #define DA9150_GPIOD_TYPE_MASK BIT(7) 514 514 515 /* DA9150_GPIO_MODE_CONT = 0x0EA */ 515 /* DA9150_GPIO_MODE_CONT = 0x0EA */ 516 #define DA9150_GPIOA_MODE_SHIFT 516 #define DA9150_GPIOA_MODE_SHIFT 0 517 #define DA9150_GPIOA_MODE_MASK 517 #define DA9150_GPIOA_MODE_MASK BIT(0) 518 #define DA9150_GPIOB_MODE_SHIFT 518 #define DA9150_GPIOB_MODE_SHIFT 1 519 #define DA9150_GPIOB_MODE_MASK 519 #define DA9150_GPIOB_MODE_MASK BIT(1) 520 #define DA9150_GPIOC_MODE_SHIFT 520 #define DA9150_GPIOC_MODE_SHIFT 2 521 #define DA9150_GPIOC_MODE_MASK 521 #define DA9150_GPIOC_MODE_MASK BIT(2) 522 #define DA9150_GPIOD_MODE_SHIFT 522 #define DA9150_GPIOD_MODE_SHIFT 3 523 #define DA9150_GPIOD_MODE_MASK 523 #define DA9150_GPIOD_MODE_MASK BIT(3) 524 #define DA9150_GPIOA_CONT_SHIFT 524 #define DA9150_GPIOA_CONT_SHIFT 4 525 #define DA9150_GPIOA_CONT_MASK 525 #define DA9150_GPIOA_CONT_MASK BIT(4) 526 #define DA9150_GPIOB_CONT_SHIFT 526 #define DA9150_GPIOB_CONT_SHIFT 5 527 #define DA9150_GPIOB_CONT_MASK 527 #define DA9150_GPIOB_CONT_MASK BIT(5) 528 #define DA9150_GPIOC_CONT_SHIFT 528 #define DA9150_GPIOC_CONT_SHIFT 6 529 #define DA9150_GPIOC_CONT_MASK 529 #define DA9150_GPIOC_CONT_MASK BIT(6) 530 #define DA9150_GPIOD_CONT_SHIFT 530 #define DA9150_GPIOD_CONT_SHIFT 7 531 #define DA9150_GPIOD_CONT_MASK 531 #define DA9150_GPIOD_CONT_MASK BIT(7) 532 532 533 /* DA9150_GPIO_CTRL_B = 0x0EB */ 533 /* DA9150_GPIO_CTRL_B = 0x0EB */ 534 #define DA9150_WAKE_PIN_SHIFT 534 #define DA9150_WAKE_PIN_SHIFT 0 535 #define DA9150_WAKE_PIN_MASK 535 #define DA9150_WAKE_PIN_MASK (0x03 << 0) 536 #define DA9150_WAKE_MODE_SHIFT 536 #define DA9150_WAKE_MODE_SHIFT 2 537 #define DA9150_WAKE_MODE_MASK 537 #define DA9150_WAKE_MODE_MASK BIT(2) 538 #define DA9150_WAKE_CONT_SHIFT 538 #define DA9150_WAKE_CONT_SHIFT 3 539 #define DA9150_WAKE_CONT_MASK 539 #define DA9150_WAKE_CONT_MASK BIT(3) 540 #define DA9150_WAKE_DLY_SHIFT 540 #define DA9150_WAKE_DLY_SHIFT 4 541 #define DA9150_WAKE_DLY_MASK 541 #define DA9150_WAKE_DLY_MASK BIT(4) 542 542 543 /* DA9150_GPIO_CTRL_A = 0x0EC */ 543 /* DA9150_GPIO_CTRL_A = 0x0EC */ 544 #define DA9150_GPIOA_ANAEN_SHIFT 544 #define DA9150_GPIOA_ANAEN_SHIFT 0 545 #define DA9150_GPIOA_ANAEN_MASK 545 #define DA9150_GPIOA_ANAEN_MASK BIT(0) 546 #define DA9150_GPIOB_ANAEN_SHIFT 546 #define DA9150_GPIOB_ANAEN_SHIFT 1 547 #define DA9150_GPIOB_ANAEN_MASK 547 #define DA9150_GPIOB_ANAEN_MASK BIT(1) 548 #define DA9150_GPIOC_ANAEN_SHIFT 548 #define DA9150_GPIOC_ANAEN_SHIFT 2 549 #define DA9150_GPIOC_ANAEN_MASK 549 #define DA9150_GPIOC_ANAEN_MASK BIT(2) 550 #define DA9150_GPIOD_ANAEN_SHIFT 550 #define DA9150_GPIOD_ANAEN_SHIFT 3 551 #define DA9150_GPIOD_ANAEN_MASK 551 #define DA9150_GPIOD_ANAEN_MASK BIT(3) 552 #define DA9150_GPIO_ANAEN 552 #define DA9150_GPIO_ANAEN 0x01 553 #define DA9150_GPIO_ANAEN_MASK 553 #define DA9150_GPIO_ANAEN_MASK 0x0F 554 #define DA9150_CHGLED_PIN_SHIFT 554 #define DA9150_CHGLED_PIN_SHIFT 5 555 #define DA9150_CHGLED_PIN_MASK 555 #define DA9150_CHGLED_PIN_MASK (0x07 << 5) 556 556 557 /* DA9150_GPIO_CTRL_C = 0x0ED */ 557 /* DA9150_GPIO_CTRL_C = 0x0ED */ 558 #define DA9150_CHGBL_DUR_SHIFT 558 #define DA9150_CHGBL_DUR_SHIFT 0 559 #define DA9150_CHGBL_DUR_MASK 559 #define DA9150_CHGBL_DUR_MASK (0x03 << 0) 560 #define DA9150_CHGBL_DBL_SHIFT 560 #define DA9150_CHGBL_DBL_SHIFT 2 561 #define DA9150_CHGBL_DBL_MASK 561 #define DA9150_CHGBL_DBL_MASK BIT(2) 562 #define DA9150_CHGBL_FRQ_SHIFT 562 #define DA9150_CHGBL_FRQ_SHIFT 3 563 #define DA9150_CHGBL_FRQ_MASK 563 #define DA9150_CHGBL_FRQ_MASK (0x03 << 3) 564 #define DA9150_CHGBL_FLKR_SHIFT 564 #define DA9150_CHGBL_FLKR_SHIFT 5 565 #define DA9150_CHGBL_FLKR_MASK 565 #define DA9150_CHGBL_FLKR_MASK BIT(5) 566 566 567 /* DA9150_GPIO_CFG_A = 0x0EE */ 567 /* DA9150_GPIO_CFG_A = 0x0EE */ 568 #define DA9150_CE_LPM_DEB_SHIFT 568 #define DA9150_CE_LPM_DEB_SHIFT 0 569 #define DA9150_CE_LPM_DEB_MASK 569 #define DA9150_CE_LPM_DEB_MASK (0x07 << 0) 570 570 571 /* DA9150_GPIO_CFG_B = 0x0EF */ 571 /* DA9150_GPIO_CFG_B = 0x0EF */ 572 #define DA9150_GPIOA_PUPD_SHIFT 572 #define DA9150_GPIOA_PUPD_SHIFT 0 573 #define DA9150_GPIOA_PUPD_MASK 573 #define DA9150_GPIOA_PUPD_MASK BIT(0) 574 #define DA9150_GPIOB_PUPD_SHIFT 574 #define DA9150_GPIOB_PUPD_SHIFT 1 575 #define DA9150_GPIOB_PUPD_MASK 575 #define DA9150_GPIOB_PUPD_MASK BIT(1) 576 #define DA9150_GPIOC_PUPD_SHIFT 576 #define DA9150_GPIOC_PUPD_SHIFT 2 577 #define DA9150_GPIOC_PUPD_MASK 577 #define DA9150_GPIOC_PUPD_MASK BIT(2) 578 #define DA9150_GPIOD_PUPD_SHIFT 578 #define DA9150_GPIOD_PUPD_SHIFT 3 579 #define DA9150_GPIOD_PUPD_MASK 579 #define DA9150_GPIOD_PUPD_MASK BIT(3) 580 #define DA9150_GPIO_PUPD_MASK 580 #define DA9150_GPIO_PUPD_MASK (0xF << 0) 581 #define DA9150_GPI_DEB_SHIFT 581 #define DA9150_GPI_DEB_SHIFT 4 582 #define DA9150_GPI_DEB_MASK 582 #define DA9150_GPI_DEB_MASK (0x07 << 4) 583 #define DA9150_LPM_EN_SHIFT 583 #define DA9150_LPM_EN_SHIFT 7 584 #define DA9150_LPM_EN_MASK 584 #define DA9150_LPM_EN_MASK BIT(7) 585 585 586 /* DA9150_GPIO_CFG_C = 0x0F0 */ 586 /* DA9150_GPIO_CFG_C = 0x0F0 */ 587 #define DA9150_GPI_V_SHIFT 587 #define DA9150_GPI_V_SHIFT 0 588 #define DA9150_GPI_V_MASK 588 #define DA9150_GPI_V_MASK BIT(0) 589 #define DA9150_VDDIO_INT_SHIFT 589 #define DA9150_VDDIO_INT_SHIFT 1 590 #define DA9150_VDDIO_INT_MASK 590 #define DA9150_VDDIO_INT_MASK BIT(1) 591 #define DA9150_FAULT_PIN_SHIFT 591 #define DA9150_FAULT_PIN_SHIFT 3 592 #define DA9150_FAULT_PIN_MASK 592 #define DA9150_FAULT_PIN_MASK (0x07 << 3) 593 #define DA9150_FAULT_TYPE_SHIFT 593 #define DA9150_FAULT_TYPE_SHIFT 6 594 #define DA9150_FAULT_TYPE_MASK 594 #define DA9150_FAULT_TYPE_MASK BIT(6) 595 #define DA9150_NIRQ_PUPD_SHIFT 595 #define DA9150_NIRQ_PUPD_SHIFT 7 596 #define DA9150_NIRQ_PUPD_MASK 596 #define DA9150_NIRQ_PUPD_MASK BIT(7) 597 597 598 /* DA9150_GPADC_MAN = 0x0F2 */ 598 /* DA9150_GPADC_MAN = 0x0F2 */ 599 #define DA9150_GPADC_EN_SHIFT 599 #define DA9150_GPADC_EN_SHIFT 0 600 #define DA9150_GPADC_EN_MASK 600 #define DA9150_GPADC_EN_MASK BIT(0) 601 #define DA9150_GPADC_MUX_SHIFT 601 #define DA9150_GPADC_MUX_SHIFT 1 602 #define DA9150_GPADC_MUX_MASK 602 #define DA9150_GPADC_MUX_MASK (0x1f << 1) 603 603 604 /* DA9150_GPADC_RES_A = 0x0F4 */ 604 /* DA9150_GPADC_RES_A = 0x0F4 */ 605 #define DA9150_GPADC_RES_H_SHIFT 605 #define DA9150_GPADC_RES_H_SHIFT 0 606 #define DA9150_GPADC_RES_H_MASK 606 #define DA9150_GPADC_RES_H_MASK (0xff << 0) 607 607 608 /* DA9150_GPADC_RES_B = 0x0F5 */ 608 /* DA9150_GPADC_RES_B = 0x0F5 */ 609 #define DA9150_GPADC_RUN_SHIFT 609 #define DA9150_GPADC_RUN_SHIFT 0 610 #define DA9150_GPADC_RUN_MASK 610 #define DA9150_GPADC_RUN_MASK BIT(0) 611 #define DA9150_GPADC_RES_L_SHIFT 611 #define DA9150_GPADC_RES_L_SHIFT 6 612 #define DA9150_GPADC_RES_L_MASK 612 #define DA9150_GPADC_RES_L_MASK (0x03 << 6) 613 #define DA9150_GPADC_RES_L_BITS 613 #define DA9150_GPADC_RES_L_BITS 2 614 614 615 /* DA9150_PAGE_CON_2 = 0x100 */ 615 /* DA9150_PAGE_CON_2 = 0x100 */ 616 #define DA9150_PAGE_SHIFT 616 #define DA9150_PAGE_SHIFT 0 617 #define DA9150_PAGE_MASK 617 #define DA9150_PAGE_MASK (0x3f << 0) 618 #define DA9150_WRITE_MODE_SHIFT 618 #define DA9150_WRITE_MODE_SHIFT 6 619 #define DA9150_WRITE_MODE_MASK 619 #define DA9150_WRITE_MODE_MASK BIT(6) 620 #define DA9150_REVERT_SHIFT 620 #define DA9150_REVERT_SHIFT 7 621 #define DA9150_REVERT_MASK 621 #define DA9150_REVERT_MASK BIT(7) 622 622 623 /* DA9150_OTP_CONT_SHARED = 0x101 */ 623 /* DA9150_OTP_CONT_SHARED = 0x101 */ 624 #define DA9150_PC_DONE_SHIFT 624 #define DA9150_PC_DONE_SHIFT 3 625 #define DA9150_PC_DONE_MASK 625 #define DA9150_PC_DONE_MASK BIT(3) 626 626 627 /* DA9150_INTERFACE_SHARED = 0x105 */ 627 /* DA9150_INTERFACE_SHARED = 0x105 */ 628 #define DA9150_IF_BASE_ADDR_SHIFT 628 #define DA9150_IF_BASE_ADDR_SHIFT 4 629 #define DA9150_IF_BASE_ADDR_MASK 629 #define DA9150_IF_BASE_ADDR_MASK (0x0f << 4) 630 630 631 /* DA9150_CONFIG_A_SHARED = 0x106 */ 631 /* DA9150_CONFIG_A_SHARED = 0x106 */ 632 #define DA9150_NIRQ_VDD_SHIFT 632 #define DA9150_NIRQ_VDD_SHIFT 1 633 #define DA9150_NIRQ_VDD_MASK 633 #define DA9150_NIRQ_VDD_MASK BIT(1) 634 #define DA9150_NIRQ_PIN_SHIFT 634 #define DA9150_NIRQ_PIN_SHIFT 2 635 #define DA9150_NIRQ_PIN_MASK 635 #define DA9150_NIRQ_PIN_MASK BIT(2) 636 #define DA9150_NIRQ_TYPE_SHIFT 636 #define DA9150_NIRQ_TYPE_SHIFT 3 637 #define DA9150_NIRQ_TYPE_MASK 637 #define DA9150_NIRQ_TYPE_MASK BIT(3) 638 #define DA9150_PM_IF_V_SHIFT 638 #define DA9150_PM_IF_V_SHIFT 4 639 #define DA9150_PM_IF_V_MASK 639 #define DA9150_PM_IF_V_MASK BIT(4) 640 #define DA9150_PM_IF_FMP_SHIFT 640 #define DA9150_PM_IF_FMP_SHIFT 5 641 #define DA9150_PM_IF_FMP_MASK 641 #define DA9150_PM_IF_FMP_MASK BIT(5) 642 #define DA9150_PM_IF_HSM_SHIFT 642 #define DA9150_PM_IF_HSM_SHIFT 6 643 #define DA9150_PM_IF_HSM_MASK 643 #define DA9150_PM_IF_HSM_MASK BIT(6) 644 644 645 /* DA9150_CONFIG_D_SHARED = 0x109 */ 645 /* DA9150_CONFIG_D_SHARED = 0x109 */ 646 #define DA9150_NIRQ_MODE_SHIFT 646 #define DA9150_NIRQ_MODE_SHIFT 1 647 #define DA9150_NIRQ_MODE_MASK 647 #define DA9150_NIRQ_MODE_MASK BIT(1) 648 648 649 /* DA9150_ADETVB_CFG_C = 0x150 */ 649 /* DA9150_ADETVB_CFG_C = 0x150 */ 650 #define DA9150_TADP_RISE_SHIFT 650 #define DA9150_TADP_RISE_SHIFT 0 651 #define DA9150_TADP_RISE_MASK 651 #define DA9150_TADP_RISE_MASK (0xff << 0) 652 652 653 /* DA9150_ADETD_STAT = 0x151 */ 653 /* DA9150_ADETD_STAT = 0x151 */ 654 #define DA9150_DCD_STAT_SHIFT 654 #define DA9150_DCD_STAT_SHIFT 0 655 #define DA9150_DCD_STAT_MASK 655 #define DA9150_DCD_STAT_MASK BIT(0) 656 #define DA9150_PCD_STAT_SHIFT 656 #define DA9150_PCD_STAT_SHIFT 1 657 #define DA9150_PCD_STAT_MASK 657 #define DA9150_PCD_STAT_MASK (0x03 << 1) 658 #define DA9150_SCD_STAT_SHIFT 658 #define DA9150_SCD_STAT_SHIFT 3 659 #define DA9150_SCD_STAT_MASK 659 #define DA9150_SCD_STAT_MASK (0x03 << 3) 660 #define DA9150_DP_STAT_SHIFT 660 #define DA9150_DP_STAT_SHIFT 5 661 #define DA9150_DP_STAT_MASK 661 #define DA9150_DP_STAT_MASK BIT(5) 662 #define DA9150_DM_STAT_SHIFT 662 #define DA9150_DM_STAT_SHIFT 6 663 #define DA9150_DM_STAT_MASK 663 #define DA9150_DM_STAT_MASK BIT(6) 664 664 665 /* DA9150_ADET_CMPSTAT = 0x152 */ 665 /* DA9150_ADET_CMPSTAT = 0x152 */ 666 #define DA9150_DP_COMP_SHIFT 666 #define DA9150_DP_COMP_SHIFT 1 667 #define DA9150_DP_COMP_MASK 667 #define DA9150_DP_COMP_MASK BIT(1) 668 #define DA9150_DM_COMP_SHIFT 668 #define DA9150_DM_COMP_SHIFT 2 669 #define DA9150_DM_COMP_MASK 669 #define DA9150_DM_COMP_MASK BIT(2) 670 #define DA9150_ADP_SNS_COMP_SHIFT 670 #define DA9150_ADP_SNS_COMP_SHIFT 3 671 #define DA9150_ADP_SNS_COMP_MASK 671 #define DA9150_ADP_SNS_COMP_MASK BIT(3) 672 #define DA9150_ADP_PRB_COMP_SHIFT 672 #define DA9150_ADP_PRB_COMP_SHIFT 4 673 #define DA9150_ADP_PRB_COMP_MASK 673 #define DA9150_ADP_PRB_COMP_MASK BIT(4) 674 #define DA9150_ID_COMP_SHIFT 674 #define DA9150_ID_COMP_SHIFT 5 675 #define DA9150_ID_COMP_MASK 675 #define DA9150_ID_COMP_MASK BIT(5) 676 676 677 /* DA9150_ADET_CTRL_A = 0x153 */ 677 /* DA9150_ADET_CTRL_A = 0x153 */ 678 #define DA9150_AID_DAT_SHIFT 678 #define DA9150_AID_DAT_SHIFT 0 679 #define DA9150_AID_DAT_MASK 679 #define DA9150_AID_DAT_MASK BIT(0) 680 #define DA9150_AID_ID_SHIFT 680 #define DA9150_AID_ID_SHIFT 1 681 #define DA9150_AID_ID_MASK 681 #define DA9150_AID_ID_MASK BIT(1) 682 #define DA9150_AID_TRIG_SHIFT 682 #define DA9150_AID_TRIG_SHIFT 2 683 #define DA9150_AID_TRIG_MASK 683 #define DA9150_AID_TRIG_MASK BIT(2) 684 684 685 /* DA9150_ADETVB_CFG_B = 0x154 */ 685 /* DA9150_ADETVB_CFG_B = 0x154 */ 686 #define DA9150_VB_MODE_SHIFT 686 #define DA9150_VB_MODE_SHIFT 0 687 #define DA9150_VB_MODE_MASK 687 #define DA9150_VB_MODE_MASK (0x03 << 0) 688 #define DA9150_VB_MODE_VB_SESS 688 #define DA9150_VB_MODE_VB_SESS BIT(0) 689 689 690 #define DA9150_TADP_PRB_SHIFT 690 #define DA9150_TADP_PRB_SHIFT 2 691 #define DA9150_TADP_PRB_MASK 691 #define DA9150_TADP_PRB_MASK BIT(2) 692 #define DA9150_DAT_RPD_EXT_SHIFT 692 #define DA9150_DAT_RPD_EXT_SHIFT 5 693 #define DA9150_DAT_RPD_EXT_MASK 693 #define DA9150_DAT_RPD_EXT_MASK BIT(5) 694 #define DA9150_CONF_RPD_SHIFT 694 #define DA9150_CONF_RPD_SHIFT 6 695 #define DA9150_CONF_RPD_MASK 695 #define DA9150_CONF_RPD_MASK BIT(6) 696 #define DA9150_CONF_SRP_SHIFT 696 #define DA9150_CONF_SRP_SHIFT 7 697 #define DA9150_CONF_SRP_MASK 697 #define DA9150_CONF_SRP_MASK BIT(7) 698 698 699 /* DA9150_ADETVB_CFG_A = 0x155 */ 699 /* DA9150_ADETVB_CFG_A = 0x155 */ 700 #define DA9150_AID_MODE_SHIFT 700 #define DA9150_AID_MODE_SHIFT 0 701 #define DA9150_AID_MODE_MASK 701 #define DA9150_AID_MODE_MASK (0x03 << 0) 702 #define DA9150_AID_EXT_POL_SHIFT 702 #define DA9150_AID_EXT_POL_SHIFT 2 703 #define DA9150_AID_EXT_POL_MASK 703 #define DA9150_AID_EXT_POL_MASK BIT(2) 704 704 705 /* DA9150_ADETAC_CFG_A = 0x156 */ 705 /* DA9150_ADETAC_CFG_A = 0x156 */ 706 #define DA9150_ISET_CDP_SHIFT 706 #define DA9150_ISET_CDP_SHIFT 0 707 #define DA9150_ISET_CDP_MASK 707 #define DA9150_ISET_CDP_MASK (0x1f << 0) 708 #define DA9150_CONF_DBP_SHIFT 708 #define DA9150_CONF_DBP_SHIFT 5 709 #define DA9150_CONF_DBP_MASK 709 #define DA9150_CONF_DBP_MASK BIT(5) 710 710 711 /* DA9150_ADDETAC_CFG_B = 0x157 */ 711 /* DA9150_ADDETAC_CFG_B = 0x157 */ 712 #define DA9150_ISET_DCHG_SHIFT 712 #define DA9150_ISET_DCHG_SHIFT 0 713 #define DA9150_ISET_DCHG_MASK 713 #define DA9150_ISET_DCHG_MASK (0x1f << 0) 714 #define DA9150_CONF_GPIOA_SHIFT 714 #define DA9150_CONF_GPIOA_SHIFT 5 715 #define DA9150_CONF_GPIOA_MASK 715 #define DA9150_CONF_GPIOA_MASK BIT(5) 716 #define DA9150_CONF_GPIOB_SHIFT 716 #define DA9150_CONF_GPIOB_SHIFT 6 717 #define DA9150_CONF_GPIOB_MASK 717 #define DA9150_CONF_GPIOB_MASK BIT(6) 718 #define DA9150_AID_VB_SHIFT 718 #define DA9150_AID_VB_SHIFT 7 719 #define DA9150_AID_VB_MASK 719 #define DA9150_AID_VB_MASK BIT(7) 720 720 721 /* DA9150_ADETAC_CFG_C = 0x158 */ 721 /* DA9150_ADETAC_CFG_C = 0x158 */ 722 #define DA9150_ISET_DEF_SHIFT 722 #define DA9150_ISET_DEF_SHIFT 0 723 #define DA9150_ISET_DEF_MASK 723 #define DA9150_ISET_DEF_MASK (0x1f << 0) 724 #define DA9150_CONF_MODE_SHIFT 724 #define DA9150_CONF_MODE_SHIFT 5 725 #define DA9150_CONF_MODE_MASK 725 #define DA9150_CONF_MODE_MASK (0x03 << 5) 726 #define DA9150_AID_CR_DIS_SHIFT 726 #define DA9150_AID_CR_DIS_SHIFT 7 727 #define DA9150_AID_CR_DIS_MASK 727 #define DA9150_AID_CR_DIS_MASK BIT(7) 728 728 729 /* DA9150_ADETAC_CFG_D = 0x159 */ 729 /* DA9150_ADETAC_CFG_D = 0x159 */ 730 #define DA9150_ISET_UNIT_SHIFT 730 #define DA9150_ISET_UNIT_SHIFT 0 731 #define DA9150_ISET_UNIT_MASK 731 #define DA9150_ISET_UNIT_MASK (0x1f << 0) 732 #define DA9150_AID_UNCLAMP_SHIFT 732 #define DA9150_AID_UNCLAMP_SHIFT 5 733 #define DA9150_AID_UNCLAMP_MASK 733 #define DA9150_AID_UNCLAMP_MASK BIT(5) 734 734 735 /* DA9150_ADETVB_CFG_D = 0x15A */ 735 /* DA9150_ADETVB_CFG_D = 0x15A */ 736 #define DA9150_ID_MODE_SHIFT 736 #define DA9150_ID_MODE_SHIFT 0 737 #define DA9150_ID_MODE_MASK 737 #define DA9150_ID_MODE_MASK (0x03 << 0) 738 #define DA9150_DAT_MODE_SHIFT 738 #define DA9150_DAT_MODE_SHIFT 2 739 #define DA9150_DAT_MODE_MASK 739 #define DA9150_DAT_MODE_MASK (0x0f << 2) 740 #define DA9150_DAT_SWP_SHIFT 740 #define DA9150_DAT_SWP_SHIFT 6 741 #define DA9150_DAT_SWP_MASK 741 #define DA9150_DAT_SWP_MASK BIT(6) 742 #define DA9150_DAT_CLAMP_EXT_SHIFT 742 #define DA9150_DAT_CLAMP_EXT_SHIFT 7 743 #define DA9150_DAT_CLAMP_EXT_MASK 743 #define DA9150_DAT_CLAMP_EXT_MASK BIT(7) 744 744 745 /* DA9150_ADETID_CFG_A = 0x15B */ 745 /* DA9150_ADETID_CFG_A = 0x15B */ 746 #define DA9150_TID_POLL_SHIFT 746 #define DA9150_TID_POLL_SHIFT 0 747 #define DA9150_TID_POLL_MASK 747 #define DA9150_TID_POLL_MASK (0x07 << 0) 748 #define DA9150_RID_CONV_SHIFT 748 #define DA9150_RID_CONV_SHIFT 3 749 #define DA9150_RID_CONV_MASK 749 #define DA9150_RID_CONV_MASK BIT(3) 750 750 751 /* DA9150_ADET_RID_PT_CHG_H = 0x15C */ 751 /* DA9150_ADET_RID_PT_CHG_H = 0x15C */ 752 #define DA9150_RID_PT_CHG_H_SHIFT 752 #define DA9150_RID_PT_CHG_H_SHIFT 0 753 #define DA9150_RID_PT_CHG_H_MASK 753 #define DA9150_RID_PT_CHG_H_MASK (0xff << 0) 754 754 755 /* DA9150_ADET_RID_PT_CHG_L = 0x15D */ 755 /* DA9150_ADET_RID_PT_CHG_L = 0x15D */ 756 #define DA9150_RID_PT_CHG_L_SHIFT 756 #define DA9150_RID_PT_CHG_L_SHIFT 6 757 #define DA9150_RID_PT_CHG_L_MASK 757 #define DA9150_RID_PT_CHG_L_MASK (0x03 << 6) 758 758 759 /* DA9150_PPR_TCTR_B = 0x160 */ 759 /* DA9150_PPR_TCTR_B = 0x160 */ 760 #define DA9150_CHG_TCTR_VAL_SHIFT 760 #define DA9150_CHG_TCTR_VAL_SHIFT 0 761 #define DA9150_CHG_TCTR_VAL_MASK 761 #define DA9150_CHG_TCTR_VAL_MASK (0xff << 0) 762 762 763 /* DA9150_PPR_BKCTRL_A = 0x163 */ 763 /* DA9150_PPR_BKCTRL_A = 0x163 */ 764 #define DA9150_VBUS_MODE_SHIFT 764 #define DA9150_VBUS_MODE_SHIFT 0 765 #define DA9150_VBUS_MODE_MASK 765 #define DA9150_VBUS_MODE_MASK (0x03 << 0) 766 #define DA9150_VBUS_MODE_CHG 766 #define DA9150_VBUS_MODE_CHG BIT(0) 767 #define DA9150_VBUS_MODE_OTG 767 #define DA9150_VBUS_MODE_OTG (0x02 << 0) 768 #define DA9150_VBUS_LPM_SHIFT 768 #define DA9150_VBUS_LPM_SHIFT 2 769 #define DA9150_VBUS_LPM_MASK 769 #define DA9150_VBUS_LPM_MASK (0x03 << 2) 770 #define DA9150_VBUS_SUSP_SHIFT 770 #define DA9150_VBUS_SUSP_SHIFT 4 771 #define DA9150_VBUS_SUSP_MASK 771 #define DA9150_VBUS_SUSP_MASK BIT(4) 772 #define DA9150_VBUS_PWM_SHIFT 772 #define DA9150_VBUS_PWM_SHIFT 5 773 #define DA9150_VBUS_PWM_MASK 773 #define DA9150_VBUS_PWM_MASK BIT(5) 774 #define DA9150_VBUS_ISO_SHIFT 774 #define DA9150_VBUS_ISO_SHIFT 6 775 #define DA9150_VBUS_ISO_MASK 775 #define DA9150_VBUS_ISO_MASK BIT(6) 776 #define DA9150_VBUS_LDO_SHIFT 776 #define DA9150_VBUS_LDO_SHIFT 7 777 #define DA9150_VBUS_LDO_MASK 777 #define DA9150_VBUS_LDO_MASK BIT(7) 778 778 779 /* DA9150_PPR_BKCFG_A = 0x164 */ 779 /* DA9150_PPR_BKCFG_A = 0x164 */ 780 #define DA9150_VBUS_ISET_SHIFT 780 #define DA9150_VBUS_ISET_SHIFT 0 781 #define DA9150_VBUS_ISET_MASK 781 #define DA9150_VBUS_ISET_MASK (0x1f << 0) 782 #define DA9150_VBUS_IMAX_SHIFT 782 #define DA9150_VBUS_IMAX_SHIFT 5 783 #define DA9150_VBUS_IMAX_MASK 783 #define DA9150_VBUS_IMAX_MASK BIT(5) 784 #define DA9150_VBUS_IOTG_SHIFT 784 #define DA9150_VBUS_IOTG_SHIFT 6 785 #define DA9150_VBUS_IOTG_MASK 785 #define DA9150_VBUS_IOTG_MASK (0x03 << 6) 786 786 787 /* DA9150_PPR_BKCFG_B = 0x165 */ 787 /* DA9150_PPR_BKCFG_B = 0x165 */ 788 #define DA9150_VBUS_DROP_SHIFT 788 #define DA9150_VBUS_DROP_SHIFT 0 789 #define DA9150_VBUS_DROP_MASK 789 #define DA9150_VBUS_DROP_MASK (0x0f << 0) 790 #define DA9150_VBUS_FAULT_DIS_SHIFT 790 #define DA9150_VBUS_FAULT_DIS_SHIFT 6 791 #define DA9150_VBUS_FAULT_DIS_MASK 791 #define DA9150_VBUS_FAULT_DIS_MASK BIT(6) 792 #define DA9150_OTG_FAULT_DIS_SHIFT 792 #define DA9150_OTG_FAULT_DIS_SHIFT 7 793 #define DA9150_OTG_FAULT_DIS_MASK 793 #define DA9150_OTG_FAULT_DIS_MASK BIT(7) 794 794 795 /* DA9150_PPR_CHGCTRL_A = 0x166 */ 795 /* DA9150_PPR_CHGCTRL_A = 0x166 */ 796 #define DA9150_CHG_EN_SHIFT 796 #define DA9150_CHG_EN_SHIFT 0 797 #define DA9150_CHG_EN_MASK 797 #define DA9150_CHG_EN_MASK BIT(0) 798 798 799 /* DA9150_PPR_CHGCTRL_B = 0x167 */ 799 /* DA9150_PPR_CHGCTRL_B = 0x167 */ 800 #define DA9150_CHG_VBAT_SHIFT 800 #define DA9150_CHG_VBAT_SHIFT 0 801 #define DA9150_CHG_VBAT_MASK 801 #define DA9150_CHG_VBAT_MASK (0x1f << 0) 802 #define DA9150_CHG_VDROP_SHIFT 802 #define DA9150_CHG_VDROP_SHIFT 6 803 #define DA9150_CHG_VDROP_MASK 803 #define DA9150_CHG_VDROP_MASK (0x03 << 6) 804 804 805 /* DA9150_PPR_CHGCTRL_C = 0x168 */ 805 /* DA9150_PPR_CHGCTRL_C = 0x168 */ 806 #define DA9150_CHG_VFAULT_SHIFT 806 #define DA9150_CHG_VFAULT_SHIFT 0 807 #define DA9150_CHG_VFAULT_MASK 807 #define DA9150_CHG_VFAULT_MASK (0x0f << 0) 808 #define DA9150_CHG_IPRE_SHIFT 808 #define DA9150_CHG_IPRE_SHIFT 4 809 #define DA9150_CHG_IPRE_MASK 809 #define DA9150_CHG_IPRE_MASK (0x03 << 4) 810 810 811 /* DA9150_PPR_TCTR_A = 0x169 */ 811 /* DA9150_PPR_TCTR_A = 0x169 */ 812 #define DA9150_CHG_TCTR_SHIFT 812 #define DA9150_CHG_TCTR_SHIFT 0 813 #define DA9150_CHG_TCTR_MASK 813 #define DA9150_CHG_TCTR_MASK (0x07 << 0) 814 #define DA9150_CHG_TCTR_MODE_SHIFT 814 #define DA9150_CHG_TCTR_MODE_SHIFT 4 815 #define DA9150_CHG_TCTR_MODE_MASK 815 #define DA9150_CHG_TCTR_MODE_MASK BIT(4) 816 816 817 /* DA9150_PPR_CHGCTRL_D = 0x16A */ 817 /* DA9150_PPR_CHGCTRL_D = 0x16A */ 818 #define DA9150_CHG_IBAT_SHIFT 818 #define DA9150_CHG_IBAT_SHIFT 0 819 #define DA9150_CHG_IBAT_MASK 819 #define DA9150_CHG_IBAT_MASK (0xff << 0) 820 820 821 /* DA9150_PPR_CHGCTRL_E = 0x16B */ 821 /* DA9150_PPR_CHGCTRL_E = 0x16B */ 822 #define DA9150_CHG_IEND_SHIFT 822 #define DA9150_CHG_IEND_SHIFT 0 823 #define DA9150_CHG_IEND_MASK 823 #define DA9150_CHG_IEND_MASK (0xff << 0) 824 824 825 /* DA9150_PPR_CHGCTRL_F = 0x16C */ 825 /* DA9150_PPR_CHGCTRL_F = 0x16C */ 826 #define DA9150_CHG_VCOLD_SHIFT 826 #define DA9150_CHG_VCOLD_SHIFT 0 827 #define DA9150_CHG_VCOLD_MASK 827 #define DA9150_CHG_VCOLD_MASK (0x1f << 0) 828 #define DA9150_TBAT_TQA_EN_SHIFT 828 #define DA9150_TBAT_TQA_EN_SHIFT 6 829 #define DA9150_TBAT_TQA_EN_MASK 829 #define DA9150_TBAT_TQA_EN_MASK BIT(6) 830 #define DA9150_TBAT_TDP_EN_SHIFT 830 #define DA9150_TBAT_TDP_EN_SHIFT 7 831 #define DA9150_TBAT_TDP_EN_MASK 831 #define DA9150_TBAT_TDP_EN_MASK BIT(7) 832 832 833 /* DA9150_PPR_CHGCTRL_G = 0x16D */ 833 /* DA9150_PPR_CHGCTRL_G = 0x16D */ 834 #define DA9150_CHG_VWARM_SHIFT 834 #define DA9150_CHG_VWARM_SHIFT 0 835 #define DA9150_CHG_VWARM_MASK 835 #define DA9150_CHG_VWARM_MASK (0x1f << 0) 836 836 837 /* DA9150_PPR_CHGCTRL_H = 0x16E */ 837 /* DA9150_PPR_CHGCTRL_H = 0x16E */ 838 #define DA9150_CHG_VHOT_SHIFT 838 #define DA9150_CHG_VHOT_SHIFT 0 839 #define DA9150_CHG_VHOT_MASK 839 #define DA9150_CHG_VHOT_MASK (0x1f << 0) 840 840 841 /* DA9150_PPR_CHGCTRL_I = 0x16F */ 841 /* DA9150_PPR_CHGCTRL_I = 0x16F */ 842 #define DA9150_CHG_ICOLD_SHIFT 842 #define DA9150_CHG_ICOLD_SHIFT 0 843 #define DA9150_CHG_ICOLD_MASK 843 #define DA9150_CHG_ICOLD_MASK (0xff << 0) 844 844 845 /* DA9150_PPR_CHGCTRL_J = 0x170 */ 845 /* DA9150_PPR_CHGCTRL_J = 0x170 */ 846 #define DA9150_CHG_IWARM_SHIFT 846 #define DA9150_CHG_IWARM_SHIFT 0 847 #define DA9150_CHG_IWARM_MASK 847 #define DA9150_CHG_IWARM_MASK (0xff << 0) 848 848 849 /* DA9150_PPR_CHGCTRL_K = 0x171 */ 849 /* DA9150_PPR_CHGCTRL_K = 0x171 */ 850 #define DA9150_CHG_IHOT_SHIFT 850 #define DA9150_CHG_IHOT_SHIFT 0 851 #define DA9150_CHG_IHOT_MASK 851 #define DA9150_CHG_IHOT_MASK (0xff << 0) 852 852 853 /* DA9150_PPR_CHGCTRL_L = 0x172 */ 853 /* DA9150_PPR_CHGCTRL_L = 0x172 */ 854 #define DA9150_CHG_IBAT_TRED_SHIFT 854 #define DA9150_CHG_IBAT_TRED_SHIFT 0 855 #define DA9150_CHG_IBAT_TRED_MASK 855 #define DA9150_CHG_IBAT_TRED_MASK (0xff << 0) 856 856 857 /* DA9150_PPR_CHGCTRL_M = 0x173 */ 857 /* DA9150_PPR_CHGCTRL_M = 0x173 */ 858 #define DA9150_CHG_VFLOAT_SHIFT 858 #define DA9150_CHG_VFLOAT_SHIFT 0 859 #define DA9150_CHG_VFLOAT_MASK 859 #define DA9150_CHG_VFLOAT_MASK (0x0f << 0) 860 #define DA9150_CHG_LPM_SHIFT 860 #define DA9150_CHG_LPM_SHIFT 5 861 #define DA9150_CHG_LPM_MASK 861 #define DA9150_CHG_LPM_MASK BIT(5) 862 #define DA9150_CHG_NBLO_SHIFT 862 #define DA9150_CHG_NBLO_SHIFT 6 863 #define DA9150_CHG_NBLO_MASK 863 #define DA9150_CHG_NBLO_MASK BIT(6) 864 #define DA9150_EBS_EN_SHIFT 864 #define DA9150_EBS_EN_SHIFT 7 865 #define DA9150_EBS_EN_MASK 865 #define DA9150_EBS_EN_MASK BIT(7) 866 866 867 /* DA9150_PPR_THYST_A = 0x174 */ 867 /* DA9150_PPR_THYST_A = 0x174 */ 868 #define DA9150_TBAT_T1_SHIFT 868 #define DA9150_TBAT_T1_SHIFT 0 869 #define DA9150_TBAT_T1_MASK 869 #define DA9150_TBAT_T1_MASK (0xff << 0) 870 870 871 /* DA9150_PPR_THYST_B = 0x175 */ 871 /* DA9150_PPR_THYST_B = 0x175 */ 872 #define DA9150_TBAT_T2_SHIFT 872 #define DA9150_TBAT_T2_SHIFT 0 873 #define DA9150_TBAT_T2_MASK 873 #define DA9150_TBAT_T2_MASK (0xff << 0) 874 874 875 /* DA9150_PPR_THYST_C = 0x176 */ 875 /* DA9150_PPR_THYST_C = 0x176 */ 876 #define DA9150_TBAT_T3_SHIFT 876 #define DA9150_TBAT_T3_SHIFT 0 877 #define DA9150_TBAT_T3_MASK 877 #define DA9150_TBAT_T3_MASK (0xff << 0) 878 878 879 /* DA9150_PPR_THYST_D = 0x177 */ 879 /* DA9150_PPR_THYST_D = 0x177 */ 880 #define DA9150_TBAT_T4_SHIFT 880 #define DA9150_TBAT_T4_SHIFT 0 881 #define DA9150_TBAT_T4_MASK 881 #define DA9150_TBAT_T4_MASK (0xff << 0) 882 882 883 /* DA9150_PPR_THYST_E = 0x178 */ 883 /* DA9150_PPR_THYST_E = 0x178 */ 884 #define DA9150_TBAT_T5_SHIFT 884 #define DA9150_TBAT_T5_SHIFT 0 885 #define DA9150_TBAT_T5_MASK 885 #define DA9150_TBAT_T5_MASK (0xff << 0) 886 886 887 /* DA9150_PPR_THYST_F = 0x179 */ 887 /* DA9150_PPR_THYST_F = 0x179 */ 888 #define DA9150_TBAT_H1_SHIFT 888 #define DA9150_TBAT_H1_SHIFT 0 889 #define DA9150_TBAT_H1_MASK 889 #define DA9150_TBAT_H1_MASK (0xff << 0) 890 890 891 /* DA9150_PPR_THYST_G = 0x17A */ 891 /* DA9150_PPR_THYST_G = 0x17A */ 892 #define DA9150_TBAT_H5_SHIFT 892 #define DA9150_TBAT_H5_SHIFT 0 893 #define DA9150_TBAT_H5_MASK 893 #define DA9150_TBAT_H5_MASK (0xff << 0) 894 894 895 /* DA9150_PAGE_CON_3 = 0x180 */ 895 /* DA9150_PAGE_CON_3 = 0x180 */ 896 #define DA9150_PAGE_SHIFT 896 #define DA9150_PAGE_SHIFT 0 897 #define DA9150_PAGE_MASK 897 #define DA9150_PAGE_MASK (0x3f << 0) 898 #define DA9150_WRITE_MODE_SHIFT 898 #define DA9150_WRITE_MODE_SHIFT 6 899 #define DA9150_WRITE_MODE_MASK 899 #define DA9150_WRITE_MODE_MASK BIT(6) 900 #define DA9150_REVERT_SHIFT 900 #define DA9150_REVERT_SHIFT 7 901 #define DA9150_REVERT_MASK 901 #define DA9150_REVERT_MASK BIT(7) 902 902 903 /* DA9150_PAGE_CON_4 = 0x200 */ 903 /* DA9150_PAGE_CON_4 = 0x200 */ 904 #define DA9150_PAGE_SHIFT 904 #define DA9150_PAGE_SHIFT 0 905 #define DA9150_PAGE_MASK 905 #define DA9150_PAGE_MASK (0x3f << 0) 906 #define DA9150_WRITE_MODE_SHIFT 906 #define DA9150_WRITE_MODE_SHIFT 6 907 #define DA9150_WRITE_MODE_MASK 907 #define DA9150_WRITE_MODE_MASK BIT(6) 908 #define DA9150_REVERT_SHIFT 908 #define DA9150_REVERT_SHIFT 7 909 #define DA9150_REVERT_MASK 909 #define DA9150_REVERT_MASK BIT(7) 910 910 911 /* DA9150_PAGE_CON_5 = 0x280 */ 911 /* DA9150_PAGE_CON_5 = 0x280 */ 912 #define DA9150_PAGE_SHIFT 912 #define DA9150_PAGE_SHIFT 0 913 #define DA9150_PAGE_MASK 913 #define DA9150_PAGE_MASK (0x3f << 0) 914 #define DA9150_WRITE_MODE_SHIFT 914 #define DA9150_WRITE_MODE_SHIFT 6 915 #define DA9150_WRITE_MODE_MASK 915 #define DA9150_WRITE_MODE_MASK BIT(6) 916 #define DA9150_REVERT_SHIFT 916 #define DA9150_REVERT_SHIFT 7 917 #define DA9150_REVERT_MASK 917 #define DA9150_REVERT_MASK BIT(7) 918 918 919 /* DA9150_PAGE_CON_6 = 0x300 */ 919 /* DA9150_PAGE_CON_6 = 0x300 */ 920 #define DA9150_PAGE_SHIFT 920 #define DA9150_PAGE_SHIFT 0 921 #define DA9150_PAGE_MASK 921 #define DA9150_PAGE_MASK (0x3f << 0) 922 #define DA9150_WRITE_MODE_SHIFT 922 #define DA9150_WRITE_MODE_SHIFT 6 923 #define DA9150_WRITE_MODE_MASK 923 #define DA9150_WRITE_MODE_MASK BIT(6) 924 #define DA9150_REVERT_SHIFT 924 #define DA9150_REVERT_SHIFT 7 925 #define DA9150_REVERT_MASK 925 #define DA9150_REVERT_MASK BIT(7) 926 926 927 /* DA9150_COREBTLD_STAT_A = 0x302 */ 927 /* DA9150_COREBTLD_STAT_A = 0x302 */ 928 #define DA9150_BOOTLD_STAT_SHIFT 928 #define DA9150_BOOTLD_STAT_SHIFT 0 929 #define DA9150_BOOTLD_STAT_MASK 929 #define DA9150_BOOTLD_STAT_MASK (0x03 << 0) 930 #define DA9150_CORE_LOCKUP_SHIFT 930 #define DA9150_CORE_LOCKUP_SHIFT 2 931 #define DA9150_CORE_LOCKUP_MASK 931 #define DA9150_CORE_LOCKUP_MASK BIT(2) 932 932 933 /* DA9150_COREBTLD_CTRL_A = 0x303 */ 933 /* DA9150_COREBTLD_CTRL_A = 0x303 */ 934 #define DA9150_CORE_RESET_SHIFT 934 #define DA9150_CORE_RESET_SHIFT 0 935 #define DA9150_CORE_RESET_MASK 935 #define DA9150_CORE_RESET_MASK BIT(0) 936 #define DA9150_CORE_STOP_SHIFT 936 #define DA9150_CORE_STOP_SHIFT 1 937 #define DA9150_CORE_STOP_MASK 937 #define DA9150_CORE_STOP_MASK BIT(1) 938 938 939 /* DA9150_CORE_CONFIG_A = 0x304 */ 939 /* DA9150_CORE_CONFIG_A = 0x304 */ 940 #define DA9150_CORE_MEMMUX_SHIFT 940 #define DA9150_CORE_MEMMUX_SHIFT 0 941 #define DA9150_CORE_MEMMUX_MASK 941 #define DA9150_CORE_MEMMUX_MASK (0x03 << 0) 942 #define DA9150_WDT_AUTO_START_SHIFT 942 #define DA9150_WDT_AUTO_START_SHIFT 2 943 #define DA9150_WDT_AUTO_START_MASK 943 #define DA9150_WDT_AUTO_START_MASK BIT(2) 944 #define DA9150_WDT_AUTO_LOCK_SHIFT 944 #define DA9150_WDT_AUTO_LOCK_SHIFT 3 945 #define DA9150_WDT_AUTO_LOCK_MASK 945 #define DA9150_WDT_AUTO_LOCK_MASK BIT(3) 946 #define DA9150_WDT_HLT_NO_CLK_SHIFT 946 #define DA9150_WDT_HLT_NO_CLK_SHIFT 4 947 #define DA9150_WDT_HLT_NO_CLK_MASK 947 #define DA9150_WDT_HLT_NO_CLK_MASK BIT(4) 948 948 949 /* DA9150_CORE_CONFIG_C = 0x305 */ 949 /* DA9150_CORE_CONFIG_C = 0x305 */ 950 #define DA9150_CORE_SW_SIZE_SHIFT 950 #define DA9150_CORE_SW_SIZE_SHIFT 0 951 #define DA9150_CORE_SW_SIZE_MASK 951 #define DA9150_CORE_SW_SIZE_MASK (0xff << 0) 952 952 953 /* DA9150_CORE_CONFIG_B = 0x306 */ 953 /* DA9150_CORE_CONFIG_B = 0x306 */ 954 #define DA9150_BOOTLD_EN_SHIFT 954 #define DA9150_BOOTLD_EN_SHIFT 0 955 #define DA9150_BOOTLD_EN_MASK 955 #define DA9150_BOOTLD_EN_MASK BIT(0) 956 #define DA9150_CORE_EN_SHIFT 956 #define DA9150_CORE_EN_SHIFT 2 957 #define DA9150_CORE_EN_MASK 957 #define DA9150_CORE_EN_MASK BIT(2) 958 #define DA9150_CORE_SW_SRC_SHIFT 958 #define DA9150_CORE_SW_SRC_SHIFT 3 959 #define DA9150_CORE_SW_SRC_MASK 959 #define DA9150_CORE_SW_SRC_MASK (0x07 << 3) 960 #define DA9150_DEEP_SLEEP_EN_SHIFT 960 #define DA9150_DEEP_SLEEP_EN_SHIFT 7 961 #define DA9150_DEEP_SLEEP_EN_MASK 961 #define DA9150_DEEP_SLEEP_EN_MASK BIT(7) 962 962 963 /* DA9150_CORE_CFG_DATA_A = 0x307 */ 963 /* DA9150_CORE_CFG_DATA_A = 0x307 */ 964 #define DA9150_CORE_CFG_DT_A_SHIFT 964 #define DA9150_CORE_CFG_DT_A_SHIFT 0 965 #define DA9150_CORE_CFG_DT_A_MASK 965 #define DA9150_CORE_CFG_DT_A_MASK (0xff << 0) 966 966 967 /* DA9150_CORE_CFG_DATA_B = 0x308 */ 967 /* DA9150_CORE_CFG_DATA_B = 0x308 */ 968 #define DA9150_CORE_CFG_DT_B_SHIFT 968 #define DA9150_CORE_CFG_DT_B_SHIFT 0 969 #define DA9150_CORE_CFG_DT_B_MASK 969 #define DA9150_CORE_CFG_DT_B_MASK (0xff << 0) 970 970 971 /* DA9150_CORE_CMD_A = 0x309 */ 971 /* DA9150_CORE_CMD_A = 0x309 */ 972 #define DA9150_CORE_CMD_SHIFT 972 #define DA9150_CORE_CMD_SHIFT 0 973 #define DA9150_CORE_CMD_MASK 973 #define DA9150_CORE_CMD_MASK (0xff << 0) 974 974 975 /* DA9150_CORE_DATA_A = 0x30A */ 975 /* DA9150_CORE_DATA_A = 0x30A */ 976 #define DA9150_CORE_DATA_0_SHIFT 976 #define DA9150_CORE_DATA_0_SHIFT 0 977 #define DA9150_CORE_DATA_0_MASK 977 #define DA9150_CORE_DATA_0_MASK (0xff << 0) 978 978 979 /* DA9150_CORE_DATA_B = 0x30B */ 979 /* DA9150_CORE_DATA_B = 0x30B */ 980 #define DA9150_CORE_DATA_1_SHIFT 980 #define DA9150_CORE_DATA_1_SHIFT 0 981 #define DA9150_CORE_DATA_1_MASK 981 #define DA9150_CORE_DATA_1_MASK (0xff << 0) 982 982 983 /* DA9150_CORE_DATA_C = 0x30C */ 983 /* DA9150_CORE_DATA_C = 0x30C */ 984 #define DA9150_CORE_DATA_2_SHIFT 984 #define DA9150_CORE_DATA_2_SHIFT 0 985 #define DA9150_CORE_DATA_2_MASK 985 #define DA9150_CORE_DATA_2_MASK (0xff << 0) 986 986 987 /* DA9150_CORE_DATA_D = 0x30D */ 987 /* DA9150_CORE_DATA_D = 0x30D */ 988 #define DA9150_CORE_DATA_3_SHIFT 988 #define DA9150_CORE_DATA_3_SHIFT 0 989 #define DA9150_CORE_DATA_3_MASK 989 #define DA9150_CORE_DATA_3_MASK (0xff << 0) 990 990 991 /* DA9150_CORE2WIRE_STAT_A = 0x310 */ 991 /* DA9150_CORE2WIRE_STAT_A = 0x310 */ 992 #define DA9150_FW_FWDL_ERR_SHIFT 992 #define DA9150_FW_FWDL_ERR_SHIFT 7 993 #define DA9150_FW_FWDL_ERR_MASK 993 #define DA9150_FW_FWDL_ERR_MASK BIT(7) 994 994 995 /* DA9150_CORE2WIRE_CTRL_A = 0x311 */ 995 /* DA9150_CORE2WIRE_CTRL_A = 0x311 */ 996 #define DA9150_FW_FWDL_EN_SHIFT 996 #define DA9150_FW_FWDL_EN_SHIFT 0 997 #define DA9150_FW_FWDL_EN_MASK 997 #define DA9150_FW_FWDL_EN_MASK BIT(0) 998 #define DA9150_FG_QIF_EN_SHIFT 998 #define DA9150_FG_QIF_EN_SHIFT 1 999 #define DA9150_FG_QIF_EN_MASK 999 #define DA9150_FG_QIF_EN_MASK BIT(1) 1000 #define DA9150_CORE_BASE_ADDR_SHIFT 1000 #define DA9150_CORE_BASE_ADDR_SHIFT 4 1001 #define DA9150_CORE_BASE_ADDR_MASK 1001 #define DA9150_CORE_BASE_ADDR_MASK (0x0f << 4) 1002 1002 1003 /* DA9150_FW_CTRL_A = 0x312 */ 1003 /* DA9150_FW_CTRL_A = 0x312 */ 1004 #define DA9150_FW_SEAL_SHIFT 1004 #define DA9150_FW_SEAL_SHIFT 0 1005 #define DA9150_FW_SEAL_MASK 1005 #define DA9150_FW_SEAL_MASK (0xff << 0) 1006 1006 1007 /* DA9150_FW_CTRL_C = 0x313 */ 1007 /* DA9150_FW_CTRL_C = 0x313 */ 1008 #define DA9150_FW_FWDL_CRC_SHIFT 1008 #define DA9150_FW_FWDL_CRC_SHIFT 0 1009 #define DA9150_FW_FWDL_CRC_MASK 1009 #define DA9150_FW_FWDL_CRC_MASK (0xff << 0) 1010 1010 1011 /* DA9150_FW_CTRL_D = 0x314 */ 1011 /* DA9150_FW_CTRL_D = 0x314 */ 1012 #define DA9150_FW_FWDL_BASE_SHIFT 1012 #define DA9150_FW_FWDL_BASE_SHIFT 0 1013 #define DA9150_FW_FWDL_BASE_MASK 1013 #define DA9150_FW_FWDL_BASE_MASK (0x0f << 0) 1014 1014 1015 /* DA9150_FG_CTRL_A = 0x315 */ 1015 /* DA9150_FG_CTRL_A = 0x315 */ 1016 #define DA9150_FG_QIF_CODE_SHIFT 1016 #define DA9150_FG_QIF_CODE_SHIFT 0 1017 #define DA9150_FG_QIF_CODE_MASK 1017 #define DA9150_FG_QIF_CODE_MASK (0xff << 0) 1018 1018 1019 /* DA9150_FG_CTRL_B = 0x316 */ 1019 /* DA9150_FG_CTRL_B = 0x316 */ 1020 #define DA9150_FG_QIF_VALUE_SHIFT 1020 #define DA9150_FG_QIF_VALUE_SHIFT 0 1021 #define DA9150_FG_QIF_VALUE_MASK 1021 #define DA9150_FG_QIF_VALUE_MASK (0xff << 0) 1022 1022 1023 /* DA9150_FW_CTRL_E = 0x317 */ 1023 /* DA9150_FW_CTRL_E = 0x317 */ 1024 #define DA9150_FW_FWDL_SEG_SHIFT 1024 #define DA9150_FW_FWDL_SEG_SHIFT 0 1025 #define DA9150_FW_FWDL_SEG_MASK 1025 #define DA9150_FW_FWDL_SEG_MASK (0xff << 0) 1026 1026 1027 /* DA9150_FW_CTRL_B = 0x318 */ 1027 /* DA9150_FW_CTRL_B = 0x318 */ 1028 #define DA9150_FW_FWDL_VALUE_SHIFT 1028 #define DA9150_FW_FWDL_VALUE_SHIFT 0 1029 #define DA9150_FW_FWDL_VALUE_MASK 1029 #define DA9150_FW_FWDL_VALUE_MASK (0xff << 0) 1030 1030 1031 /* DA9150_GPADC_CMAN = 0x320 */ 1031 /* DA9150_GPADC_CMAN = 0x320 */ 1032 #define DA9150_GPADC_CEN_SHIFT 1032 #define DA9150_GPADC_CEN_SHIFT 0 1033 #define DA9150_GPADC_CEN_MASK 1033 #define DA9150_GPADC_CEN_MASK BIT(0) 1034 #define DA9150_GPADC_CMUX_SHIFT 1034 #define DA9150_GPADC_CMUX_SHIFT 1 1035 #define DA9150_GPADC_CMUX_MASK 1035 #define DA9150_GPADC_CMUX_MASK (0x1f << 1) 1036 1036 1037 /* DA9150_GPADC_CRES_A = 0x322 */ 1037 /* DA9150_GPADC_CRES_A = 0x322 */ 1038 #define DA9150_GPADC_CRES_H_SHIFT 1038 #define DA9150_GPADC_CRES_H_SHIFT 0 1039 #define DA9150_GPADC_CRES_H_MASK 1039 #define DA9150_GPADC_CRES_H_MASK (0xff << 0) 1040 1040 1041 /* DA9150_GPADC_CRES_B = 0x323 */ 1041 /* DA9150_GPADC_CRES_B = 0x323 */ 1042 #define DA9150_GPADC_CRUN_SHIFT 1042 #define DA9150_GPADC_CRUN_SHIFT 0 1043 #define DA9150_GPADC_CRUN_MASK 1043 #define DA9150_GPADC_CRUN_MASK BIT(0) 1044 #define DA9150_GPADC_CRES_L_SHIFT 1044 #define DA9150_GPADC_CRES_L_SHIFT 6 1045 #define DA9150_GPADC_CRES_L_MASK 1045 #define DA9150_GPADC_CRES_L_MASK (0x03 << 6) 1046 1046 1047 /* DA9150_CC_CFG_A = 0x328 */ 1047 /* DA9150_CC_CFG_A = 0x328 */ 1048 #define DA9150_CC_EN_SHIFT 1048 #define DA9150_CC_EN_SHIFT 0 1049 #define DA9150_CC_EN_MASK 1049 #define DA9150_CC_EN_MASK BIT(0) 1050 #define DA9150_CC_TIMEBASE_SHIFT 1050 #define DA9150_CC_TIMEBASE_SHIFT 1 1051 #define DA9150_CC_TIMEBASE_MASK 1051 #define DA9150_CC_TIMEBASE_MASK (0x03 << 1) 1052 #define DA9150_CC_CFG_SHIFT 1052 #define DA9150_CC_CFG_SHIFT 5 1053 #define DA9150_CC_CFG_MASK 1053 #define DA9150_CC_CFG_MASK (0x03 << 5) 1054 #define DA9150_CC_ENDLESS_MODE_SHIFT 1054 #define DA9150_CC_ENDLESS_MODE_SHIFT 7 1055 #define DA9150_CC_ENDLESS_MODE_MASK 1055 #define DA9150_CC_ENDLESS_MODE_MASK BIT(7) 1056 1056 1057 /* DA9150_CC_CFG_B = 0x329 */ 1057 /* DA9150_CC_CFG_B = 0x329 */ 1058 #define DA9150_CC_OPT_SHIFT 1058 #define DA9150_CC_OPT_SHIFT 0 1059 #define DA9150_CC_OPT_MASK 1059 #define DA9150_CC_OPT_MASK (0x03 << 0) 1060 #define DA9150_CC_PREAMP_SHIFT 1060 #define DA9150_CC_PREAMP_SHIFT 2 1061 #define DA9150_CC_PREAMP_MASK 1061 #define DA9150_CC_PREAMP_MASK (0x03 << 2) 1062 1062 1063 /* DA9150_CC_ICHG_RES_A = 0x32A */ 1063 /* DA9150_CC_ICHG_RES_A = 0x32A */ 1064 #define DA9150_CC_ICHG_RES_H_SHIFT 1064 #define DA9150_CC_ICHG_RES_H_SHIFT 0 1065 #define DA9150_CC_ICHG_RES_H_MASK 1065 #define DA9150_CC_ICHG_RES_H_MASK (0xff << 0) 1066 1066 1067 /* DA9150_CC_ICHG_RES_B = 0x32B */ 1067 /* DA9150_CC_ICHG_RES_B = 0x32B */ 1068 #define DA9150_CC_ICHG_RES_L_SHIFT 1068 #define DA9150_CC_ICHG_RES_L_SHIFT 3 1069 #define DA9150_CC_ICHG_RES_L_MASK 1069 #define DA9150_CC_ICHG_RES_L_MASK (0x1f << 3) 1070 1070 1071 /* DA9150_CC_IAVG_RES_A = 0x32C */ 1071 /* DA9150_CC_IAVG_RES_A = 0x32C */ 1072 #define DA9150_CC_IAVG_RES_H_SHIFT 1072 #define DA9150_CC_IAVG_RES_H_SHIFT 0 1073 #define DA9150_CC_IAVG_RES_H_MASK 1073 #define DA9150_CC_IAVG_RES_H_MASK (0xff << 0) 1074 1074 1075 /* DA9150_CC_IAVG_RES_B = 0x32D */ 1075 /* DA9150_CC_IAVG_RES_B = 0x32D */ 1076 #define DA9150_CC_IAVG_RES_L_SHIFT 1076 #define DA9150_CC_IAVG_RES_L_SHIFT 0 1077 #define DA9150_CC_IAVG_RES_L_MASK 1077 #define DA9150_CC_IAVG_RES_L_MASK (0xff << 0) 1078 1078 1079 /* DA9150_TAUX_CTRL_A = 0x330 */ 1079 /* DA9150_TAUX_CTRL_A = 0x330 */ 1080 #define DA9150_TAUX_EN_SHIFT 1080 #define DA9150_TAUX_EN_SHIFT 0 1081 #define DA9150_TAUX_EN_MASK 1081 #define DA9150_TAUX_EN_MASK BIT(0) 1082 #define DA9150_TAUX_MOD_SHIFT 1082 #define DA9150_TAUX_MOD_SHIFT 1 1083 #define DA9150_TAUX_MOD_MASK 1083 #define DA9150_TAUX_MOD_MASK BIT(1) 1084 #define DA9150_TAUX_UPDATE_SHIFT 1084 #define DA9150_TAUX_UPDATE_SHIFT 2 1085 #define DA9150_TAUX_UPDATE_MASK 1085 #define DA9150_TAUX_UPDATE_MASK BIT(2) 1086 1086 1087 /* DA9150_TAUX_RELOAD_H = 0x332 */ 1087 /* DA9150_TAUX_RELOAD_H = 0x332 */ 1088 #define DA9150_TAUX_RLD_H_SHIFT 1088 #define DA9150_TAUX_RLD_H_SHIFT 0 1089 #define DA9150_TAUX_RLD_H_MASK 1089 #define DA9150_TAUX_RLD_H_MASK (0xff << 0) 1090 1090 1091 /* DA9150_TAUX_RELOAD_L = 0x333 */ 1091 /* DA9150_TAUX_RELOAD_L = 0x333 */ 1092 #define DA9150_TAUX_RLD_L_SHIFT 1092 #define DA9150_TAUX_RLD_L_SHIFT 3 1093 #define DA9150_TAUX_RLD_L_MASK 1093 #define DA9150_TAUX_RLD_L_MASK (0x1f << 3) 1094 1094 1095 /* DA9150_TAUX_VALUE_H = 0x334 */ 1095 /* DA9150_TAUX_VALUE_H = 0x334 */ 1096 #define DA9150_TAUX_VAL_H_SHIFT 1096 #define DA9150_TAUX_VAL_H_SHIFT 0 1097 #define DA9150_TAUX_VAL_H_MASK 1097 #define DA9150_TAUX_VAL_H_MASK (0xff << 0) 1098 1098 1099 /* DA9150_TAUX_VALUE_L = 0x335 */ 1099 /* DA9150_TAUX_VALUE_L = 0x335 */ 1100 #define DA9150_TAUX_VAL_L_SHIFT 1100 #define DA9150_TAUX_VAL_L_SHIFT 3 1101 #define DA9150_TAUX_VAL_L_MASK 1101 #define DA9150_TAUX_VAL_L_MASK (0x1f << 3) 1102 1102 1103 /* DA9150_AUX_DATA_0 = 0x338 */ 1103 /* DA9150_AUX_DATA_0 = 0x338 */ 1104 #define DA9150_AUX_DAT_0_SHIFT 1104 #define DA9150_AUX_DAT_0_SHIFT 0 1105 #define DA9150_AUX_DAT_0_MASK 1105 #define DA9150_AUX_DAT_0_MASK (0xff << 0) 1106 1106 1107 /* DA9150_AUX_DATA_1 = 0x339 */ 1107 /* DA9150_AUX_DATA_1 = 0x339 */ 1108 #define DA9150_AUX_DAT_1_SHIFT 1108 #define DA9150_AUX_DAT_1_SHIFT 0 1109 #define DA9150_AUX_DAT_1_MASK 1109 #define DA9150_AUX_DAT_1_MASK (0xff << 0) 1110 1110 1111 /* DA9150_AUX_DATA_2 = 0x33A */ 1111 /* DA9150_AUX_DATA_2 = 0x33A */ 1112 #define DA9150_AUX_DAT_2_SHIFT 1112 #define DA9150_AUX_DAT_2_SHIFT 0 1113 #define DA9150_AUX_DAT_2_MASK 1113 #define DA9150_AUX_DAT_2_MASK (0xff << 0) 1114 1114 1115 /* DA9150_AUX_DATA_3 = 0x33B */ 1115 /* DA9150_AUX_DATA_3 = 0x33B */ 1116 #define DA9150_AUX_DAT_3_SHIFT 1116 #define DA9150_AUX_DAT_3_SHIFT 0 1117 #define DA9150_AUX_DAT_3_MASK 1117 #define DA9150_AUX_DAT_3_MASK (0xff << 0) 1118 1118 1119 /* DA9150_BIF_CTRL = 0x340 */ 1119 /* DA9150_BIF_CTRL = 0x340 */ 1120 #define DA9150_BIF_ISRC_EN_SHIFT 1120 #define DA9150_BIF_ISRC_EN_SHIFT 0 1121 #define DA9150_BIF_ISRC_EN_MASK 1121 #define DA9150_BIF_ISRC_EN_MASK BIT(0) 1122 1122 1123 /* DA9150_TBAT_CTRL_A = 0x342 */ 1123 /* DA9150_TBAT_CTRL_A = 0x342 */ 1124 #define DA9150_TBAT_EN_SHIFT 1124 #define DA9150_TBAT_EN_SHIFT 0 1125 #define DA9150_TBAT_EN_MASK 1125 #define DA9150_TBAT_EN_MASK BIT(0) 1126 #define DA9150_TBAT_SW1_SHIFT 1126 #define DA9150_TBAT_SW1_SHIFT 1 1127 #define DA9150_TBAT_SW1_MASK 1127 #define DA9150_TBAT_SW1_MASK BIT(1) 1128 #define DA9150_TBAT_SW2_SHIFT 1128 #define DA9150_TBAT_SW2_SHIFT 2 1129 #define DA9150_TBAT_SW2_MASK 1129 #define DA9150_TBAT_SW2_MASK BIT(2) 1130 1130 1131 /* DA9150_TBAT_CTRL_B = 0x343 */ 1131 /* DA9150_TBAT_CTRL_B = 0x343 */ 1132 #define DA9150_TBAT_SW_FRC_SHIFT 1132 #define DA9150_TBAT_SW_FRC_SHIFT 0 1133 #define DA9150_TBAT_SW_FRC_MASK 1133 #define DA9150_TBAT_SW_FRC_MASK BIT(0) 1134 #define DA9150_TBAT_STAT_SW1_SHIFT 1134 #define DA9150_TBAT_STAT_SW1_SHIFT 1 1135 #define DA9150_TBAT_STAT_SW1_MASK 1135 #define DA9150_TBAT_STAT_SW1_MASK BIT(1) 1136 #define DA9150_TBAT_STAT_SW2_SHIFT 1136 #define DA9150_TBAT_STAT_SW2_SHIFT 2 1137 #define DA9150_TBAT_STAT_SW2_MASK 1137 #define DA9150_TBAT_STAT_SW2_MASK BIT(2) 1138 #define DA9150_TBAT_HIGH_CURR_SHIFT 1138 #define DA9150_TBAT_HIGH_CURR_SHIFT 3 1139 #define DA9150_TBAT_HIGH_CURR_MASK 1139 #define DA9150_TBAT_HIGH_CURR_MASK BIT(3) 1140 1140 1141 /* DA9150_TBAT_RES_A = 0x344 */ 1141 /* DA9150_TBAT_RES_A = 0x344 */ 1142 #define DA9150_TBAT_RES_H_SHIFT 1142 #define DA9150_TBAT_RES_H_SHIFT 0 1143 #define DA9150_TBAT_RES_H_MASK 1143 #define DA9150_TBAT_RES_H_MASK (0xff << 0) 1144 1144 1145 /* DA9150_TBAT_RES_B = 0x345 */ 1145 /* DA9150_TBAT_RES_B = 0x345 */ 1146 #define DA9150_TBAT_RES_DIS_SHIFT 1146 #define DA9150_TBAT_RES_DIS_SHIFT 0 1147 #define DA9150_TBAT_RES_DIS_MASK 1147 #define DA9150_TBAT_RES_DIS_MASK BIT(0) 1148 #define DA9150_TBAT_RES_L_SHIFT 1148 #define DA9150_TBAT_RES_L_SHIFT 6 1149 #define DA9150_TBAT_RES_L_MASK 1149 #define DA9150_TBAT_RES_L_MASK (0x03 << 6) 1150 1150 1151 #endif /* __DA9150_REGISTERS_H */ 1151 #endif /* __DA9150_REGISTERS_H */ 1152 1152
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