1 /* SPDX-License-Identifier: GPL-2.0 1 /* SPDX-License-Identifier: GPL-2.0
2 * 2 *
3 * Copyright (C) 2020 Gateworks Corporation 3 * Copyright (C) 2020 Gateworks Corporation
4 */ 4 */
5 #ifndef __LINUX_MFD_GSC_H_ 5 #ifndef __LINUX_MFD_GSC_H_
6 #define __LINUX_MFD_GSC_H_ 6 #define __LINUX_MFD_GSC_H_
7 7
8 #include <linux/regmap.h> 8 #include <linux/regmap.h>
9 9
10 /* Device Addresses */ 10 /* Device Addresses */
11 #define GSC_MISC 0x20 11 #define GSC_MISC 0x20
12 #define GSC_UPDATE 0x21 12 #define GSC_UPDATE 0x21
13 #define GSC_GPIO 0x23 13 #define GSC_GPIO 0x23
14 #define GSC_HWMON 0x29 14 #define GSC_HWMON 0x29
15 #define GSC_EEPROM0 0x50 15 #define GSC_EEPROM0 0x50
16 #define GSC_EEPROM1 0x51 16 #define GSC_EEPROM1 0x51
17 #define GSC_EEPROM2 0x52 17 #define GSC_EEPROM2 0x52
18 #define GSC_EEPROM3 0x53 18 #define GSC_EEPROM3 0x53
19 #define GSC_RTC 0x68 19 #define GSC_RTC 0x68
20 20
21 /* Register offsets */ 21 /* Register offsets */
22 enum { 22 enum {
23 GSC_CTRL_0 = 0x00, 23 GSC_CTRL_0 = 0x00,
24 GSC_CTRL_1 = 0x01, 24 GSC_CTRL_1 = 0x01,
25 GSC_TIME = 0x02, 25 GSC_TIME = 0x02,
26 GSC_TIME_ADD = 0x06, 26 GSC_TIME_ADD = 0x06,
27 GSC_IRQ_STATUS = 0x0A, 27 GSC_IRQ_STATUS = 0x0A,
28 GSC_IRQ_ENABLE = 0x0B, 28 GSC_IRQ_ENABLE = 0x0B,
29 GSC_FW_CRC = 0x0C, 29 GSC_FW_CRC = 0x0C,
30 GSC_FW_VER = 0x0E, 30 GSC_FW_VER = 0x0E,
31 GSC_WP = 0x0F, 31 GSC_WP = 0x0F,
32 }; 32 };
33 33
34 /* Bit definitions */ 34 /* Bit definitions */
35 #define GSC_CTRL_0_PB_HARD_RESET 0 35 #define GSC_CTRL_0_PB_HARD_RESET 0
36 #define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1 36 #define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1
37 #define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2 37 #define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2
38 #define GSC_CTRL_0_PB_BOOT_ALTERNATE 3 38 #define GSC_CTRL_0_PB_BOOT_ALTERNATE 3
39 #define GSC_CTRL_0_PERFORM_CRC 4 39 #define GSC_CTRL_0_PERFORM_CRC 4
40 #define GSC_CTRL_0_TAMPER_DETECT 5 40 #define GSC_CTRL_0_TAMPER_DETECT 5
41 #define GSC_CTRL_0_SWITCH_HOLD 6 41 #define GSC_CTRL_0_SWITCH_HOLD 6
42 42
43 #define GSC_CTRL_1_SLEEP_ENABLE 0 43 #define GSC_CTRL_1_SLEEP_ENABLE 0
44 #define GSC_CTRL_1_SLEEP_ACTIVATE 1 44 #define GSC_CTRL_1_SLEEP_ACTIVATE 1
45 #define GSC_CTRL_1_SLEEP_ADD 2 45 #define GSC_CTRL_1_SLEEP_ADD 2
46 #define GSC_CTRL_1_SLEEP_NOWAKEPB 3 46 #define GSC_CTRL_1_SLEEP_NOWAKEPB 3
47 #define GSC_CTRL_1_WDT_TIME 4 47 #define GSC_CTRL_1_WDT_TIME 4
48 #define GSC_CTRL_1_WDT_ENABLE 5 48 #define GSC_CTRL_1_WDT_ENABLE 5
49 #define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6 49 #define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6
50 #define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7 50 #define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7
51 51
52 #define GSC_IRQ_PB 0 52 #define GSC_IRQ_PB 0
53 #define GSC_IRQ_KEY_ERASED 1 53 #define GSC_IRQ_KEY_ERASED 1
54 #define GSC_IRQ_EEPROM_WP 2 54 #define GSC_IRQ_EEPROM_WP 2
55 #define GSC_IRQ_RESV 3 55 #define GSC_IRQ_RESV 3
56 #define GSC_IRQ_GPIO 4 56 #define GSC_IRQ_GPIO 4
57 #define GSC_IRQ_TAMPER 5 57 #define GSC_IRQ_TAMPER 5
58 #define GSC_IRQ_WDT_TIMEOUT 6 58 #define GSC_IRQ_WDT_TIMEOUT 6
59 #define GSC_IRQ_SWITCH_HOLD 7 59 #define GSC_IRQ_SWITCH_HOLD 7
60 60
61 int gsc_read(void *context, unsigned int reg, 61 int gsc_read(void *context, unsigned int reg, unsigned int *val);
62 int gsc_write(void *context, unsigned int reg, 62 int gsc_write(void *context, unsigned int reg, unsigned int val);
63 63
64 struct gsc_dev { 64 struct gsc_dev {
65 struct device *dev; 65 struct device *dev;
66 66
67 struct i2c_client *i2c; /* 0x2 67 struct i2c_client *i2c; /* 0x20: interrupt controller, WDT */
68 struct i2c_client *i2c_hwmon; /* 0x2 68 struct i2c_client *i2c_hwmon; /* 0x29: hwmon, fan controller */
69 69
70 struct regmap *regmap; 70 struct regmap *regmap;
71 71
72 unsigned int fwver; 72 unsigned int fwver;
73 unsigned short fwcrc; 73 unsigned short fwcrc;
74 }; 74 };
75 75
76 #endif /* __LINUX_MFD_GSC_H_ */ 76 #endif /* __LINUX_MFD_GSC_H_ */
77 77
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