1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * Functions to access LP87565 power managemen
4 *
5 * Copyright (C) 2017 Texas Instruments Incorp
6 */
7
8 #ifndef __LINUX_MFD_LP87565_H
9 #define __LINUX_MFD_LP87565_H
10
11 #include <linux/i2c.h>
12 #include <linux/regulator/driver.h>
13 #include <linux/regulator/machine.h>
14
15 enum lp87565_device_type {
16 LP87565_DEVICE_TYPE_UNKNOWN = 0,
17 LP87565_DEVICE_TYPE_LP87524_Q1,
18 LP87565_DEVICE_TYPE_LP87561_Q1,
19 LP87565_DEVICE_TYPE_LP87565_Q1,
20 };
21
22 /* All register addresses */
23 #define LP87565_REG_DEV_REV 0X00
24 #define LP87565_REG_OTP_REV 0X01
25 #define LP87565_REG_BUCK0_CTRL_1
26 #define LP87565_REG_BUCK0_CTRL_2
27
28 #define LP87565_REG_BUCK1_CTRL_1
29 #define LP87565_REG_BUCK1_CTRL_2
30
31 #define LP87565_REG_BUCK2_CTRL_1
32 #define LP87565_REG_BUCK2_CTRL_2
33
34 #define LP87565_REG_BUCK3_CTRL_1
35 #define LP87565_REG_BUCK3_CTRL_2
36
37 #define LP87565_REG_BUCK0_VOUT
38 #define LP87565_REG_BUCK0_FLOOR_VOUT
39
40 #define LP87565_REG_BUCK1_VOUT
41 #define LP87565_REG_BUCK1_FLOOR_VOUT
42
43 #define LP87565_REG_BUCK2_VOUT
44 #define LP87565_REG_BUCK2_FLOOR_VOUT
45
46 #define LP87565_REG_BUCK3_VOUT
47 #define LP87565_REG_BUCK3_FLOOR_VOUT
48
49 #define LP87565_REG_BUCK0_DELAY
50 #define LP87565_REG_BUCK1_DELAY
51
52 #define LP87565_REG_BUCK2_DELAY
53 #define LP87565_REG_BUCK3_DELAY
54
55 #define LP87565_REG_GPO2_DELAY
56 #define LP87565_REG_GPO3_DELAY
57 #define LP87565_REG_RESET
58 #define LP87565_REG_CONFIG
59
60 #define LP87565_REG_INT_TOP_1
61 #define LP87565_REG_INT_TOP_2
62
63 #define LP87565_REG_INT_BUCK_0_1
64 #define LP87565_REG_INT_BUCK_2_3
65 #define LP87565_REG_TOP_STAT
66 #define LP87565_REG_BUCK_0_1_STAT
67 #define LP87565_REG_BUCK_2_3_STAT
68
69 #define LP87565_REG_TOP_MASK_1
70 #define LP87565_REG_TOP_MASK_2
71
72 #define LP87565_REG_BUCK_0_1_MASK
73 #define LP87565_REG_BUCK_2_3_MASK
74 #define LP87565_REG_SEL_I_LOAD
75
76 #define LP87565_REG_I_LOAD_2
77 #define LP87565_REG_I_LOAD_1
78
79 #define LP87565_REG_PGOOD_CTRL1
80 #define LP87565_REG_PGOOD_CTRL2
81 #define LP87565_REG_PGOOD_FLT
82 #define LP87565_REG_PLL_CTRL
83 #define LP87565_REG_PIN_FUNCTION
84 #define LP87565_REG_GPIO_CONFIG
85 #define LP87565_REG_GPIO_IN
86 #define LP87565_REG_GPIO_OUT
87
88 #define LP87565_REG_MAX LP8756
89
90 /* Register field definitions */
91 #define LP87565_DEV_REV_DEV_ID
92 #define LP87565_DEV_REV_ALL_LAYER
93 #define LP87565_DEV_REV_METAL_LAYER
94
95 #define LP87565_OTP_REV_OTP_ID
96
97 #define LP87565_BUCK_CTRL_1_EN
98 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL
99 #define LP87565_BUCK_CTRL_1_PIN_SELECT_EN
100
101 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN
102 #define LP87565_BUCK_CTRL_1_RDIS_EN
103 #define LP87565_BUCK_CTRL_1_FPWM
104 /* Bit0 is reserved for BUCK1 and BUCK3 and va
105 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2
106
107 #define LP87565_BUCK_CTRL_2_ILIM
108 #define LP87565_BUCK_CTRL_2_SLEW_RATE
109
110 #define LP87565_BUCK_VSET
111 #define LP87565_BUCK_FLOOR_VSET
112
113 #define LP87565_BUCK_SHUTDOWN_DELAY
114 #define LP87565_BUCK_STARTUP_DELAY
115
116 #define LP87565_GPIO_SHUTDOWN_DELAY
117 #define LP87565_GPIO_STARTUP_DELAY
118
119 #define LP87565_RESET_SW_RESET
120
121 #define LP87565_CONFIG_DOUBLE_DELAY
122 #define LP87565_CONFIG_CLKIN_PD
123 #define LP87565_CONFIG_EN4_PD
124 #define LP87565_CONFIG_EN3_PD
125 #define LP87565_CONFIG_TDIE_WARN_LEVEL
126 #define LP87565_CONFIG_EN2_PD
127 #define LP87565_CONFIG_EN1_PD
128
129 #define LP87565_INT_GPIO
130 #define LP87565_INT_BUCK23
131 #define LP87565_INT_BUCK01
132 #define LP87565_NO_SYNC_CLK
133 #define LP87565_TDIE_SD
134 #define LP87565_TDIE_WARN
135 #define LP87565_INT_OVP
136 #define LP87565_I_LOAD_READY
137
138 #define LP87565_INT_TOP2_RESET_REG
139
140 #define LP87565_BUCK1_PG_INT
141 #define LP87565_BUCK1_SC_INT
142 #define LP87565_BUCK1_ILIM_INT
143 #define LP87565_BUCK0_PG_INT
144 #define LP87565_BUCK0_SC_INT
145 #define LP87565_BUCK0_ILIM_INT
146
147 #define LP87565_BUCK3_PG_INT
148 #define LP87565_BUCK3_SC_INT
149 #define LP87565_BUCK3_ILIM_INT
150 #define LP87565_BUCK2_PG_INT
151 #define LP87565_BUCK2_SC_INT
152 #define LP87565_BUCK2_ILIM_INT
153
154 #define LP87565_SYNC_CLK_STAT
155 #define LP87565_TDIE_SD_STAT
156 #define LP87565_TDIE_WARN_STAT
157 #define LP87565_OVP_STAT
158
159 #define LP87565_BUCK1_STAT
160 #define LP87565_BUCK1_PG_STAT
161 #define LP87565_BUCK1_ILIM_STAT
162 #define LP87565_BUCK0_STAT
163 #define LP87565_BUCK0_PG_STAT
164 #define LP87565_BUCK0_ILIM_STAT
165
166 #define LP87565_BUCK3_STAT
167 #define LP87565_BUCK3_PG_STAT
168 #define LP87565_BUCK3_ILIM_STAT
169 #define LP87565_BUCK2_STAT
170 #define LP87565_BUCK2_PG_STAT
171 #define LP87565_BUCK2_ILIM_STAT
172
173 #define LPL87565_GPIO_MASK
174 #define LPL87565_SYNC_CLK_MASK
175 #define LPL87565_TDIE_WARN_MASK
176 #define LPL87565_I_LOAD_READY_MASK
177
178 #define LPL87565_RESET_REG_MASK
179
180 #define LPL87565_BUCK1_PG_MASK
181 #define LPL87565_BUCK1_ILIM_MASK
182 #define LPL87565_BUCK0_PG_MASK
183 #define LPL87565_BUCK0_ILIM_MASK
184
185 #define LPL87565_BUCK3_PG_MASK
186 #define LPL87565_BUCK3_ILIM_MASK
187 #define LPL87565_BUCK2_PG_MASK
188 #define LPL87565_BUCK2_ILIM_MASK
189
190 #define LP87565_LOAD_CURRENT_BUCK_SELECT
191
192 #define LP87565_I_LOAD2_BUCK_LOAD_CURRENT
193 #define LP87565_I_LOAD1_BUCK_LOAD_CURRENT
194
195 #define LP87565_PG3_SEL
196 #define LP87565_PG2_SEL
197 #define LP87565_PG1_SEL
198 #define LP87565_PG0_SEL
199
200 #define LP87565_HALF_DAY
201 #define LP87565_EN_PG0_NINT
202 #define LP87565_PGOOD_SET_DELAY
203 #define LP87565_EN_PGFLT_STAT
204 #define LP87565_PGOOD_WINDOW
205 #define LP87565_PGOOD_OD
206 #define LP87565_PGOOD_POL
207
208 #define LP87565_PG3_FLT
209 #define LP87565_PG2_FLT
210 #define LP87565_PG1_FLT
211 #define LP87565_PG0_FLT
212
213 #define LP87565_PLL_MODE
214 #define LP87565_EXT_CLK_FREQ
215
216 #define LP87565_EN_SPREAD_SPEC
217 #define LP87565_EN_PIN_CTRL_GPIO3
218 #define LP87565_EN_PIN_SELECT_GPIO3
219 #define LP87565_EN_PIN_CTRL_GPIO2
220 #define LP87565_EN_PIN_SELECT_GPIO2
221 #define LP87565_GPIO3_SEL
222 #define LP87565_GPIO2_SEL
223 #define LP87565_GPIO1_SEL
224
225 #define LP87565_GPIO3_OD
226 #define LP87565_GPIO2_OD
227 #define LP87565_GPIO1_OD
228 #define LP87565_GPIO3_DIR
229 #define LP87565_GPIO2_DIR
230 #define LP87565_GPIO1_DIR
231
232 #define LP87565_GPIO3_IN
233 #define LP87565_GPIO2_IN
234 #define LP87565_GPIO1_IN
235
236 #define LP87565_GPIO3_OUT
237 #define LP87565_GPIO2_OUT
238 #define LP87565_GPIO1_OUT
239
240 /**
241 * struct LP87565 - state holder for the LP875
242 * @dev: struct device pointer for MFD device
243 * @rev: revision of the LP87565
244 * @dev_type: The device type for example lp87
245 * @lock: lock guarding the data structure
246 * @regmap: register map of the LP87565 PMIC
247 *
248 * Device data may be used to access the LP875
249 */
250 struct lp87565 {
251 struct device *dev;
252 u8 rev;
253 u8 dev_type;
254 struct regmap *regmap;
255 struct gpio_desc *reset_gpio;
256 };
257 #endif /* __LINUX_MFD_LP87565_H */
258
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