1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * Defining registers address and its bit defi
4 *
5 * Copyright (C) 2016 NVIDIA CORPORATION. All
6 */
7
8 #ifndef _MFD_MAX77620_H_
9 #define _MFD_MAX77620_H_
10
11 #include <linux/types.h>
12
13 /* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Regist
14 #define MAX77620_REG_CNFGGLBL1
15 #define MAX77620_REG_CNFGGLBL2
16 #define MAX77620_REG_CNFGGLBL3
17 #define MAX77620_REG_CNFG1_32K
18 #define MAX77620_REG_CNFGBBC
19 #define MAX77620_REG_IRQTOP
20 #define MAX77620_REG_INTLBT
21 #define MAX77620_REG_IRQSD
22 #define MAX77620_REG_IRQ_LVL2_L0_7
23 #define MAX77620_REG_IRQ_LVL2_L8
24 #define MAX77620_REG_IRQ_LVL2_GPIO
25 #define MAX77620_REG_ONOFFIRQ
26 #define MAX77620_REG_NVERC
27 #define MAX77620_REG_IRQTOPM
28 #define MAX77620_REG_INTENLBT
29 #define MAX77620_REG_IRQMASKSD
30 #define MAX77620_REG_IRQ_MSK_L0_7
31 #define MAX77620_REG_IRQ_MSK_L8
32 #define MAX77620_REG_ONOFFIRQM
33 #define MAX77620_REG_STATLBT
34 #define MAX77620_REG_STATSD
35 #define MAX77620_REG_ONOFFSTAT
36
37 /* SD and LDO Registers */
38 #define MAX77620_REG_SD0
39 #define MAX77620_REG_SD1
40 #define MAX77620_REG_SD2
41 #define MAX77620_REG_SD3
42 #define MAX77620_REG_SD4
43 #define MAX77620_REG_DVSSD0
44 #define MAX77620_REG_DVSSD1
45 #define MAX77620_REG_SD0_CFG
46 #define MAX77620_REG_SD1_CFG
47 #define MAX77620_REG_SD2_CFG
48 #define MAX77620_REG_SD3_CFG
49 #define MAX77620_REG_SD4_CFG
50 #define MAX77620_REG_SD_CFG2
51 #define MAX77620_REG_LDO0_CFG
52 #define MAX77620_REG_LDO0_CFG2
53 #define MAX77620_REG_LDO1_CFG
54 #define MAX77620_REG_LDO1_CFG2
55 #define MAX77620_REG_LDO2_CFG
56 #define MAX77620_REG_LDO2_CFG2
57 #define MAX77620_REG_LDO3_CFG
58 #define MAX77620_REG_LDO3_CFG2
59 #define MAX77620_REG_LDO4_CFG
60 #define MAX77620_REG_LDO4_CFG2
61 #define MAX77620_REG_LDO5_CFG
62 #define MAX77620_REG_LDO5_CFG2
63 #define MAX77620_REG_LDO6_CFG
64 #define MAX77620_REG_LDO6_CFG2
65 #define MAX77620_REG_LDO7_CFG
66 #define MAX77620_REG_LDO7_CFG2
67 #define MAX77620_REG_LDO8_CFG
68 #define MAX77620_REG_LDO8_CFG2
69 #define MAX77620_REG_LDO_CFG3
70
71 #define MAX77620_LDO_SLEW_RATE_MASK
72
73 /* LDO Configuration 3 */
74 #define MAX77620_TRACK4_MASK
75 #define MAX77620_TRACK4_SHIFT
76
77 /* Voltage */
78 #define MAX77620_SDX_VOLT_MASK
79 #define MAX77620_SD0_VOLT_MASK
80 #define MAX77620_SD1_VOLT_MASK
81 #define MAX77620_LDO_VOLT_MASK
82
83 #define MAX77620_REG_GPIO0
84 #define MAX77620_REG_GPIO1
85 #define MAX77620_REG_GPIO2
86 #define MAX77620_REG_GPIO3
87 #define MAX77620_REG_GPIO4
88 #define MAX77620_REG_GPIO5
89 #define MAX77620_REG_GPIO6
90 #define MAX77620_REG_GPIO7
91 #define MAX77620_REG_PUE_GPIO
92 #define MAX77620_REG_PDE_GPIO
93 #define MAX77620_REG_AME_GPIO
94 #define MAX77620_REG_ONOFFCNFG1
95 #define MAX77620_REG_ONOFFCNFG2
96
97 /* FPS Registers */
98 #define MAX77620_REG_FPS_CFG0
99 #define MAX77620_REG_FPS_CFG1
100 #define MAX77620_REG_FPS_CFG2
101 #define MAX77620_REG_FPS_LDO0
102 #define MAX77620_REG_FPS_LDO1
103 #define MAX77620_REG_FPS_LDO2
104 #define MAX77620_REG_FPS_LDO3
105 #define MAX77620_REG_FPS_LDO4
106 #define MAX77620_REG_FPS_LDO5
107 #define MAX77620_REG_FPS_LDO6
108 #define MAX77620_REG_FPS_LDO7
109 #define MAX77620_REG_FPS_LDO8
110 #define MAX77620_REG_FPS_SD0
111 #define MAX77620_REG_FPS_SD1
112 #define MAX77620_REG_FPS_SD2
113 #define MAX77620_REG_FPS_SD3
114 #define MAX77620_REG_FPS_SD4
115 #define MAX77620_REG_FPS_NONE
116
117 #define MAX77620_FPS_SRC_MASK
118 #define MAX77620_FPS_SRC_SHIFT
119 #define MAX77620_FPS_PU_PERIOD_MASK
120 #define MAX77620_FPS_PU_PERIOD_SHIFT
121 #define MAX77620_FPS_PD_PERIOD_MASK
122 #define MAX77620_FPS_PD_PERIOD_SHIFT
123 #define MAX77620_FPS_TIME_PERIOD_MASK
124 #define MAX77620_FPS_TIME_PERIOD_SHIFT
125 #define MAX77620_FPS_EN_SRC_MASK
126 #define MAX77620_FPS_EN_SRC_SHIFT
127 #define MAX77620_FPS_ENFPS_SW_MASK
128 #define MAX77620_FPS_ENFPS_SW
129
130 /* Minimum and maximum FPS period time (in mic
131 * different for MAX77620 and Max20024.
132 */
133 #define MAX77620_FPS_PERIOD_MIN_US
134 #define MAX20024_FPS_PERIOD_MIN_US
135
136 #define MAX20024_FPS_PERIOD_MAX_US
137 #define MAX77620_FPS_PERIOD_MAX_US
138
139 #define MAX77620_REG_FPS_GPIO1
140 #define MAX77620_REG_FPS_GPIO2
141 #define MAX77620_REG_FPS_GPIO3
142 #define MAX77620_REG_FPS_RSO
143 #define MAX77620_REG_CID0
144 #define MAX77620_REG_CID1
145 #define MAX77620_REG_CID2
146 #define MAX77620_REG_CID3
147 #define MAX77620_REG_CID4
148 #define MAX77620_REG_CID5
149
150 #define MAX77620_REG_DVSSD4
151 #define MAX20024_REG_MAX_ADD
152
153 #define MAX77620_CID_DIDM_MASK
154 #define MAX77620_CID_DIDM_SHIFT
155
156 /* CNCG2SD */
157 #define MAX77620_SD_CNF2_ROVS_EN_SD1
158 #define MAX77620_SD_CNF2_ROVS_EN_SD0
159
160 /* Device Identification Metal */
161 #define MAX77620_CID5_DIDM(n)
162 /* Device Indentification OTP */
163 #define MAX77620_CID5_DIDO(n)
164
165 /* SD CNFG1 */
166 #define MAX77620_SD_SR_MASK
167 #define MAX77620_SD_SR_SHIFT
168 #define MAX77620_SD_POWER_MODE_MASK
169 #define MAX77620_SD_POWER_MODE_SHIFT
170 #define MAX77620_SD_CFG1_ADE_MASK
171 #define MAX77620_SD_CFG1_ADE_DISABLE
172 #define MAX77620_SD_CFG1_ADE_ENABLE
173 #define MAX77620_SD_FPWM_MASK
174 #define MAX77620_SD_FPWM_SHIFT
175 #define MAX77620_SD_FSRADE_MASK
176 #define MAX77620_SD_FSRADE_SHIFT
177 #define MAX77620_SD_CFG1_FPWM_SD_MASK
178 #define MAX77620_SD_CFG1_FPWM_SD_SKIP
179 #define MAX77620_SD_CFG1_FPWM_SD_FPWM
180 #define MAX20024_SD_CFG1_MPOK_MASK
181 #define MAX77620_SD_CFG1_FSRADE_SD_MASK
182 #define MAX77620_SD_CFG1_FSRADE_SD_DISABLE
183 #define MAX77620_SD_CFG1_FSRADE_SD_ENABLE
184
185 /* LDO_CNFG2 */
186 #define MAX77620_LDO_POWER_MODE_MASK
187 #define MAX77620_LDO_POWER_MODE_SHIFT
188 #define MAX20024_LDO_CFG2_MPOK_MASK
189 #define MAX77620_LDO_CFG2_ADE_MASK
190 #define MAX77620_LDO_CFG2_ADE_DISABLE
191 #define MAX77620_LDO_CFG2_ADE_ENABLE
192 #define MAX77620_LDO_CFG2_SS_MASK
193 #define MAX77620_LDO_CFG2_SS_FAST
194 #define MAX77620_LDO_CFG2_SS_SLOW
195
196 #define MAX77620_IRQ_TOP_GLBL_MASK
197 #define MAX77620_IRQ_TOP_SD_MASK
198 #define MAX77620_IRQ_TOP_LDO_MASK
199 #define MAX77620_IRQ_TOP_GPIO_MASK
200 #define MAX77620_IRQ_TOP_RTC_MASK
201 #define MAX77620_IRQ_TOP_32K_MASK
202 #define MAX77620_IRQ_TOP_ONOFF_MASK
203
204 #define MAX77620_IRQ_LBM_MASK
205 #define MAX77620_IRQ_TJALRM1_MASK
206 #define MAX77620_IRQ_TJALRM2_MASK
207
208 #define MAX77620_PWR_I2C_ADDR
209 #define MAX77620_RTC_I2C_ADDR
210
211 #define MAX77620_CNFG_GPIO_DRV_MASK
212 #define MAX77620_CNFG_GPIO_DRV_PUSHPULL
213 #define MAX77620_CNFG_GPIO_DRV_OPENDRAIN
214 #define MAX77620_CNFG_GPIO_DIR_MASK
215 #define MAX77620_CNFG_GPIO_DIR_INPUT
216 #define MAX77620_CNFG_GPIO_DIR_OUTPUT
217 #define MAX77620_CNFG_GPIO_INPUT_VAL_MASK
218 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK
219 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH
220 #define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW
221 #define MAX77620_CNFG_GPIO_INT_MASK
222 #define MAX77620_CNFG_GPIO_INT_FALLING
223 #define MAX77620_CNFG_GPIO_INT_RISING
224 #define MAX77620_CNFG_GPIO_DBNC_MASK
225 #define MAX77620_CNFG_GPIO_DBNC_None
226 #define MAX77620_CNFG_GPIO_DBNC_8ms
227 #define MAX77620_CNFG_GPIO_DBNC_16ms
228 #define MAX77620_CNFG_GPIO_DBNC_32ms
229
230 #define MAX77620_IRQ_LVL2_GPIO_EDGE0
231 #define MAX77620_IRQ_LVL2_GPIO_EDGE1
232 #define MAX77620_IRQ_LVL2_GPIO_EDGE2
233 #define MAX77620_IRQ_LVL2_GPIO_EDGE3
234 #define MAX77620_IRQ_LVL2_GPIO_EDGE4
235 #define MAX77620_IRQ_LVL2_GPIO_EDGE5
236 #define MAX77620_IRQ_LVL2_GPIO_EDGE6
237 #define MAX77620_IRQ_LVL2_GPIO_EDGE7
238
239 #define MAX77620_CNFG1_32K_OUT0_EN
240
241 #define MAX77620_ONOFFCNFG1_SFT_RST
242 #define MAX77620_ONOFFCNFG1_MRT_MASK
243 #define MAX77620_ONOFFCNFG1_MRT_SHIFT
244 #define MAX77620_ONOFFCNFG1_SLPEN
245 #define MAX77620_ONOFFCNFG1_PWR_OFF
246 #define MAX20024_ONOFFCNFG1_CLRSE
247
248 #define MAX77620_ONOFFCNFG2_SFT_RST_WK
249 #define MAX77620_ONOFFCNFG2_WD_RST_WK
250 #define MAX77620_ONOFFCNFG2_SLP_LPM_MSK
251 #define MAX77620_ONOFFCNFG2_WK_ALARM1
252 #define MAX77620_ONOFFCNFG2_WK_EN0
253
254 #define MAX77620_GLBLM_MASK
255
256 #define MAX77620_WDTC_MASK
257 #define MAX77620_WDTOFFC
258 #define MAX77620_WDTSLPC
259 #define MAX77620_WDTEN
260
261 #define MAX77620_TWD_MASK
262 #define MAX77620_TWD_2s
263 #define MAX77620_TWD_16s
264 #define MAX77620_TWD_64s
265 #define MAX77620_TWD_128s
266
267 #define MAX77620_CNFGGLBL1_LBDAC_EN
268 #define MAX77620_CNFGGLBL1_MPPLD
269 #define MAX77620_CNFGGLBL1_LBHYST
270 #define MAX77620_CNFGGLBL1_LBDAC
271 #define MAX77620_CNFGGLBL1_LBRSTEN
272
273 /* CNFG BBC registers */
274 #define MAX77620_CNFGBBC_ENABLE
275 #define MAX77620_CNFGBBC_CURRENT_MASK
276 #define MAX77620_CNFGBBC_CURRENT_SHIFT
277 #define MAX77620_CNFGBBC_VOLTAGE_MASK
278 #define MAX77620_CNFGBBC_VOLTAGE_SHIFT
279 #define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE
280 #define MAX77620_CNFGBBC_RESISTOR_MASK
281 #define MAX77620_CNFGBBC_RESISTOR_SHIFT
282
283 #define MAX77620_FPS_COUNT
284
285 /* Interrupts */
286 enum {
287 MAX77620_IRQ_TOP_GLBL, /* Low
288 MAX77620_IRQ_TOP_SD, /* SD
289 MAX77620_IRQ_TOP_LDO, /* LDO
290 MAX77620_IRQ_TOP_GPIO, /* TOP
291 MAX77620_IRQ_TOP_RTC, /* RTC
292 MAX77620_IRQ_TOP_32K, /* 32k
293 MAX77620_IRQ_TOP_ONOFF, /* ON/
294 MAX77620_IRQ_LBT_MBATLOW, /* The
295 MAX77620_IRQ_LBT_TJALRM1, /* The
296 MAX77620_IRQ_LBT_TJALRM2, /* The
297 };
298
299 /* GPIOs */
300 enum {
301 MAX77620_GPIO0,
302 MAX77620_GPIO1,
303 MAX77620_GPIO2,
304 MAX77620_GPIO3,
305 MAX77620_GPIO4,
306 MAX77620_GPIO5,
307 MAX77620_GPIO6,
308 MAX77620_GPIO7,
309 MAX77620_GPIO_NR,
310 };
311
312 /* FPS Source */
313 enum max77620_fps_src {
314 MAX77620_FPS_SRC_0,
315 MAX77620_FPS_SRC_1,
316 MAX77620_FPS_SRC_2,
317 MAX77620_FPS_SRC_NONE,
318 MAX77620_FPS_SRC_DEF,
319 };
320
321 enum max77620_chip_id {
322 MAX77620,
323 MAX20024,
324 MAX77663,
325 };
326
327 struct max77620_chip {
328 struct device *dev;
329 struct regmap *rmap;
330
331 int chip_irq;
332
333 /* chip id */
334 enum max77620_chip_id chip_id;
335
336 bool sleep_enable;
337 bool enable_global_lpm;
338 int shutdown_fps_period[MAX77620_FPS_C
339 int suspend_fps_period[MAX77620_FPS_CO
340
341 struct regmap_irq_chip_data *top_irq_d
342 struct regmap_irq_chip_data *gpio_irq_
343 };
344
345 #endif /* _MFD_MAX77620_H_ */
346
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