1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 2 /* 3 * Copyright (c) 2022 AngeloGioacchino Del Reg 4 */ 5 6 #ifndef __MFD_MT6332_REGISTERS_H__ 7 #define __MFD_MT6332_REGISTERS_H__ 8 9 /* PMIC Registers */ 10 #define MT6332_HWCID 0x8000 11 #define MT6332_SWCID 0x8002 12 #define MT6332_TOP_CON 0x8004 13 #define MT6332_DDR_VREF_AP_CON 0x8006 14 #define MT6332_DDR_VREF_DQ_CON 0x8008 15 #define MT6332_DDR_VREF_CA_CON 0x800A 16 #define MT6332_TEST_OUT 0x800C 17 #define MT6332_TEST_CON0 0x800E 18 #define MT6332_TEST_CON1 0x8010 19 #define MT6332_TESTMODE_SW 0x8012 20 #define MT6332_TESTMODE_ANA 0x8014 21 #define MT6332_TDSEL_CON 0x8016 22 #define MT6332_RDSEL_CON 0x8018 23 #define MT6332_SMT_CON0 0x801A 24 #define MT6332_SMT_CON1 0x801C 25 #define MT6332_DRV_CON0 0x801E 26 #define MT6332_DRV_CON1 0x8020 27 #define MT6332_DRV_CON2 0x8022 28 #define MT6332_EN_STATUS0 0x8024 29 #define MT6332_OCSTATUS0 0x8026 30 #define MT6332_TOP_STATUS 0x8028 31 #define MT6332_TOP_STATUS_SET 0x802A 32 #define MT6332_TOP_STATUS_CLR 0x802C 33 #define MT6332_FLASH_CON0 0x802E 34 #define MT6332_FLASH_CON1 0x8030 35 #define MT6332_FLASH_CON2 0x8032 36 #define MT6332_CORE_CON0 0x8034 37 #define MT6332_CORE_CON1 0x8036 38 #define MT6332_CORE_CON2 0x8038 39 #define MT6332_CORE_CON3 0x803A 40 #define MT6332_CORE_CON4 0x803C 41 #define MT6332_CORE_CON5 0x803E 42 #define MT6332_CORE_CON6 0x8040 43 #define MT6332_CORE_CON7 0x8042 44 #define MT6332_CORE_CON8 0x8044 45 #define MT6332_CORE_CON9 0x8046 46 #define MT6332_CORE_CON10 0x8048 47 #define MT6332_CORE_CON11 0x804A 48 #define MT6332_CORE_CON12 0x804C 49 #define MT6332_CORE_CON13 0x804E 50 #define MT6332_CORE_CON14 0x8050 51 #define MT6332_CORE_CON15 0x8052 52 #define MT6332_STA_CON0 0x8054 53 #define MT6332_STA_CON1 0x8056 54 #define MT6332_STA_CON2 0x8058 55 #define MT6332_STA_CON3 0x805A 56 #define MT6332_STA_CON4 0x805C 57 #define MT6332_STA_CON5 0x805E 58 #define MT6332_STA_CON6 0x8060 59 #define MT6332_STA_CON7 0x8062 60 #define MT6332_CHR_CON0 0x8064 61 #define MT6332_CHR_CON1 0x8066 62 #define MT6332_CHR_CON2 0x8068 63 #define MT6332_CHR_CON3 0x806A 64 #define MT6332_CHR_CON4 0x806C 65 #define MT6332_CHR_CON5 0x806E 66 #define MT6332_CHR_CON6 0x8070 67 #define MT6332_CHR_CON7 0x8072 68 #define MT6332_CHR_CON8 0x8074 69 #define MT6332_CHR_CON9 0x8076 70 #define MT6332_CHR_CON10 0x8078 71 #define MT6332_CHR_CON11 0x807A 72 #define MT6332_CHR_CON12 0x807C 73 #define MT6332_CHR_CON13 0x807E 74 #define MT6332_CHR_CON14 0x8080 75 #define MT6332_CHR_CON15 0x8082 76 #define MT6332_BOOST_CON0 0x8084 77 #define MT6332_BOOST_CON1 0x8086 78 #define MT6332_BOOST_CON2 0x8088 79 #define MT6332_BOOST_CON3 0x808A 80 #define MT6332_BOOST_CON4 0x808C 81 #define MT6332_BOOST_CON5 0x808E 82 #define MT6332_BOOST_CON6 0x8090 83 #define MT6332_BOOST_CON7 0x8092 84 #define MT6332_TOP_CKPDN_CON0 0x8094 85 #define MT6332_TOP_CKPDN_CON0_SET 0x8096 86 #define MT6332_TOP_CKPDN_CON0_CLR 0x8098 87 #define MT6332_TOP_CKPDN_CON1 0x809A 88 #define MT6332_TOP_CKPDN_CON1_SET 0x809C 89 #define MT6332_TOP_CKPDN_CON1_CLR 0x809E 90 #define MT6332_TOP_CKPDN_CON2 0x80A0 91 #define MT6332_TOP_CKPDN_CON2_SET 0x80A2 92 #define MT6332_TOP_CKPDN_CON2_CLR 0x80A4 93 #define MT6332_TOP_CKSEL_CON0 0x80A6 94 #define MT6332_TOP_CKSEL_CON0_SET 0x80A8 95 #define MT6332_TOP_CKSEL_CON0_CLR 0x80AA 96 #define MT6332_TOP_CKSEL_CON1 0x80AC 97 #define MT6332_TOP_CKSEL_CON1_SET 0x80AE 98 #define MT6332_TOP_CKSEL_CON1_CLR 0x80B0 99 #define MT6332_TOP_CKHWEN_CON 0x80B2 100 #define MT6332_TOP_CKHWEN_CON_SET 0x80B4 101 #define MT6332_TOP_CKHWEN_CON_CLR 0x80B6 102 #define MT6332_TOP_CKTST_CON0 0x80B8 103 #define MT6332_TOP_CKTST_CON1 0x80BA 104 #define MT6332_TOP_RST_CON 0x80BC 105 #define MT6332_TOP_RST_CON_SET 0x80BE 106 #define MT6332_TOP_RST_CON_CLR 0x80C0 107 #define MT6332_TOP_RST_MISC 0x80C2 108 #define MT6332_TOP_RST_MISC_SET 0x80C4 109 #define MT6332_TOP_RST_MISC_CLR 0x80C6 110 #define MT6332_INT_CON0 0x80C8 111 #define MT6332_INT_CON0_SET 0x80CA 112 #define MT6332_INT_CON0_CLR 0x80CC 113 #define MT6332_INT_CON1 0x80CE 114 #define MT6332_INT_CON1_SET 0x80D0 115 #define MT6332_INT_CON1_CLR 0x80D2 116 #define MT6332_INT_CON2 0x80D4 117 #define MT6332_INT_CON2_SET 0x80D6 118 #define MT6332_INT_CON2_CLR 0x80D8 119 #define MT6332_INT_CON3 0x80DA 120 #define MT6332_INT_CON3_SET 0x80DC 121 #define MT6332_INT_CON3_CLR 0x80DE 122 #define MT6332_CHRWDT_CON0 0x80E0 123 #define MT6332_CHRWDT_STATUS0 0x80E2 124 #define MT6332_INT_STATUS0 0x80E4 125 #define MT6332_INT_STATUS1 0x80E6 126 #define MT6332_INT_STATUS2 0x80E8 127 #define MT6332_INT_STATUS3 0x80EA 128 #define MT6332_OC_GEAR_0 0x80EC 129 #define MT6332_OC_GEAR_1 0x80EE 130 #define MT6332_OC_GEAR_2 0x80F0 131 #define MT6332_INT_MISC_CON 0x80F2 132 #define MT6332_RG_SPI_CON 0x80F4 133 #define MT6332_DEW_DIO_EN 0x80F6 134 #define MT6332_DEW_READ_TEST 0x80F8 135 #define MT6332_DEW_WRITE_TEST 0x80FA 136 #define MT6332_DEW_CRC_SWRST 0x80FC 137 #define MT6332_DEW_CRC_EN 0x80FE 138 #define MT6332_DEW_CRC_VAL 0x8100 139 #define MT6332_DEW_DBG_MON_SEL 0x8102 140 #define MT6332_DEW_CIPHER_KEY_SEL 0x8104 141 #define MT6332_DEW_CIPHER_IV_SEL 0x8106 142 #define MT6332_DEW_CIPHER_EN 0x8108 143 #define MT6332_DEW_CIPHER_RDY 0x810A 144 #define MT6332_DEW_CIPHER_MODE 0x810C 145 #define MT6332_DEW_CIPHER_SWRST 0x810E 146 #define MT6332_DEW_RDDMY_NO 0x8110 147 #define MT6332_INT_STA 0x8112 148 #define MT6332_BIF_CON0 0x8114 149 #define MT6332_BIF_CON1 0x8116 150 #define MT6332_BIF_CON2 0x8118 151 #define MT6332_BIF_CON3 0x811A 152 #define MT6332_BIF_CON4 0x811C 153 #define MT6332_BIF_CON5 0x811E 154 #define MT6332_BIF_CON6 0x8120 155 #define MT6332_BIF_CON7 0x8122 156 #define MT6332_BIF_CON8 0x8124 157 #define MT6332_BIF_CON9 0x8126 158 #define MT6332_BIF_CON10 0x8128 159 #define MT6332_BIF_CON11 0x812A 160 #define MT6332_BIF_CON12 0x812C 161 #define MT6332_BIF_CON13 0x812E 162 #define MT6332_BIF_CON14 0x8130 163 #define MT6332_BIF_CON15 0x8132 164 #define MT6332_BIF_CON16 0x8134 165 #define MT6332_BIF_CON17 0x8136 166 #define MT6332_BIF_CON18 0x8138 167 #define MT6332_BIF_CON19 0x813A 168 #define MT6332_BIF_CON20 0x813C 169 #define MT6332_BIF_CON21 0x813E 170 #define MT6332_BIF_CON22 0x8140 171 #define MT6332_BIF_CON23 0x8142 172 #define MT6332_BIF_CON24 0x8144 173 #define MT6332_BIF_CON25 0x8146 174 #define MT6332_BIF_CON26 0x8148 175 #define MT6332_BIF_CON27 0x814A 176 #define MT6332_BIF_CON28 0x814C 177 #define MT6332_BIF_CON29 0x814E 178 #define MT6332_BIF_CON30 0x8150 179 #define MT6332_BIF_CON31 0x8152 180 #define MT6332_BIF_CON32 0x8154 181 #define MT6332_BIF_CON33 0x8156 182 #define MT6332_BIF_CON34 0x8158 183 #define MT6332_BIF_CON35 0x815A 184 #define MT6332_BIF_CON36 0x815C 185 #define MT6332_BATON_CON0 0x815E 186 #define MT6332_BIF_CON37 0x8160 187 #define MT6332_BIF_CON38 0x8162 188 #define MT6332_CHR_CON16 0x8164 189 #define MT6332_CHR_CON17 0x8166 190 #define MT6332_CHR_CON18 0x8168 191 #define MT6332_CHR_CON19 0x816A 192 #define MT6332_CHR_CON20 0x816C 193 #define MT6332_CHR_CON21 0x816E 194 #define MT6332_CHR_CON22 0x8170 195 #define MT6332_CHR_CON23 0x8172 196 #define MT6332_CHR_CON24 0x8174 197 #define MT6332_CHR_CON25 0x8176 198 #define MT6332_STA_CON8 0x8178 199 #define MT6332_BUCK_ALL_CON0 0x8400 200 #define MT6332_BUCK_ALL_CON1 0x8402 201 #define MT6332_BUCK_ALL_CON2 0x8404 202 #define MT6332_BUCK_ALL_CON3 0x8406 203 #define MT6332_BUCK_ALL_CON4 0x8408 204 #define MT6332_BUCK_ALL_CON5 0x840A 205 #define MT6332_BUCK_ALL_CON6 0x840C 206 #define MT6332_BUCK_ALL_CON7 0x840E 207 #define MT6332_BUCK_ALL_CON8 0x8410 208 #define MT6332_BUCK_ALL_CON9 0x8412 209 #define MT6332_BUCK_ALL_CON10 0x8414 210 #define MT6332_BUCK_ALL_CON11 0x8416 211 #define MT6332_BUCK_ALL_CON12 0x8418 212 #define MT6332_BUCK_ALL_CON13 0x841A 213 #define MT6332_BUCK_ALL_CON14 0x841C 214 #define MT6332_BUCK_ALL_CON15 0x841E 215 #define MT6332_BUCK_ALL_CON16 0x8420 216 #define MT6332_BUCK_ALL_CON17 0x8422 217 #define MT6332_BUCK_ALL_CON18 0x8424 218 #define MT6332_BUCK_ALL_CON19 0x8426 219 #define MT6332_BUCK_ALL_CON20 0x8428 220 #define MT6332_BUCK_ALL_CON21 0x842A 221 #define MT6332_BUCK_ALL_CON22 0x842C 222 #define MT6332_BUCK_ALL_CON23 0x842E 223 #define MT6332_BUCK_ALL_CON24 0x8430 224 #define MT6332_BUCK_ALL_CON25 0x8432 225 #define MT6332_BUCK_ALL_CON26 0x8434 226 #define MT6332_BUCK_ALL_CON27 0x8436 227 #define MT6332_VDRAM_CON0 0x8438 228 #define MT6332_VDRAM_CON1 0x843A 229 #define MT6332_VDRAM_CON2 0x843C 230 #define MT6332_VDRAM_CON3 0x843E 231 #define MT6332_VDRAM_CON4 0x8440 232 #define MT6332_VDRAM_CON5 0x8442 233 #define MT6332_VDRAM_CON6 0x8444 234 #define MT6332_VDRAM_CON7 0x8446 235 #define MT6332_VDRAM_CON8 0x8448 236 #define MT6332_VDRAM_CON9 0x844A 237 #define MT6332_VDRAM_CON10 0x844C 238 #define MT6332_VDRAM_CON11 0x844E 239 #define MT6332_VDRAM_CON12 0x8450 240 #define MT6332_VDRAM_CON13 0x8452 241 #define MT6332_VDRAM_CON14 0x8454 242 #define MT6332_VDRAM_CON15 0x8456 243 #define MT6332_VDRAM_CON16 0x8458 244 #define MT6332_VDRAM_CON17 0x845A 245 #define MT6332_VDRAM_CON18 0x845C 246 #define MT6332_VDRAM_CON19 0x845E 247 #define MT6332_VDRAM_CON20 0x8460 248 #define MT6332_VDRAM_CON21 0x8462 249 #define MT6332_VDVFS2_CON0 0x8464 250 #define MT6332_VDVFS2_CON1 0x8466 251 #define MT6332_VDVFS2_CON2 0x8468 252 #define MT6332_VDVFS2_CON3 0x846A 253 #define MT6332_VDVFS2_CON4 0x846C 254 #define MT6332_VDVFS2_CON5 0x846E 255 #define MT6332_VDVFS2_CON6 0x8470 256 #define MT6332_VDVFS2_CON7 0x8472 257 #define MT6332_VDVFS2_CON8 0x8474 258 #define MT6332_VDVFS2_CON9 0x8476 259 #define MT6332_VDVFS2_CON10 0x8478 260 #define MT6332_VDVFS2_CON11 0x847A 261 #define MT6332_VDVFS2_CON12 0x847C 262 #define MT6332_VDVFS2_CON13 0x847E 263 #define MT6332_VDVFS2_CON14 0x8480 264 #define MT6332_VDVFS2_CON15 0x8482 265 #define MT6332_VDVFS2_CON16 0x8484 266 #define MT6332_VDVFS2_CON17 0x8486 267 #define MT6332_VDVFS2_CON18 0x8488 268 #define MT6332_VDVFS2_CON19 0x848A 269 #define MT6332_VDVFS2_CON20 0x848C 270 #define MT6332_VDVFS2_CON21 0x848E 271 #define MT6332_VDVFS2_CON22 0x8490 272 #define MT6332_VDVFS2_CON23 0x8492 273 #define MT6332_VDVFS2_CON24 0x8494 274 #define MT6332_VDVFS2_CON25 0x8496 275 #define MT6332_VDVFS2_CON26 0x8498 276 #define MT6332_VDVFS2_CON27 0x849A 277 #define MT6332_VRF1_CON0 0x849C 278 #define MT6332_VRF1_CON1 0x849E 279 #define MT6332_VRF1_CON2 0x84A0 280 #define MT6332_VRF1_CON3 0x84A2 281 #define MT6332_VRF1_CON4 0x84A4 282 #define MT6332_VRF1_CON5 0x84A6 283 #define MT6332_VRF1_CON6 0x84A8 284 #define MT6332_VRF1_CON7 0x84AA 285 #define MT6332_VRF1_CON8 0x84AC 286 #define MT6332_VRF1_CON9 0x84AE 287 #define MT6332_VRF1_CON10 0x84B0 288 #define MT6332_VRF1_CON11 0x84B2 289 #define MT6332_VRF1_CON12 0x84B4 290 #define MT6332_VRF1_CON13 0x84B6 291 #define MT6332_VRF1_CON14 0x84B8 292 #define MT6332_VRF1_CON15 0x84BA 293 #define MT6332_VRF1_CON16 0x84BC 294 #define MT6332_VRF1_CON17 0x84BE 295 #define MT6332_VRF1_CON18 0x84C0 296 #define MT6332_VRF1_CON19 0x84C2 297 #define MT6332_VRF1_CON20 0x84C4 298 #define MT6332_VRF1_CON21 0x84C6 299 #define MT6332_VRF2_CON0 0x84C8 300 #define MT6332_VRF2_CON1 0x84CA 301 #define MT6332_VRF2_CON2 0x84CC 302 #define MT6332_VRF2_CON3 0x84CE 303 #define MT6332_VRF2_CON4 0x84D0 304 #define MT6332_VRF2_CON5 0x84D2 305 #define MT6332_VRF2_CON6 0x84D4 306 #define MT6332_VRF2_CON7 0x84D6 307 #define MT6332_VRF2_CON8 0x84D8 308 #define MT6332_VRF2_CON9 0x84DA 309 #define MT6332_VRF2_CON10 0x84DC 310 #define MT6332_VRF2_CON11 0x84DE 311 #define MT6332_VRF2_CON12 0x84E0 312 #define MT6332_VRF2_CON13 0x84E2 313 #define MT6332_VRF2_CON14 0x84E4 314 #define MT6332_VRF2_CON15 0x84E6 315 #define MT6332_VRF2_CON16 0x84E8 316 #define MT6332_VRF2_CON17 0x84EA 317 #define MT6332_VRF2_CON18 0x84EC 318 #define MT6332_VRF2_CON19 0x84EE 319 #define MT6332_VRF2_CON20 0x84F0 320 #define MT6332_VRF2_CON21 0x84F2 321 #define MT6332_VPA_CON0 0x84F4 322 #define MT6332_VPA_CON1 0x84F6 323 #define MT6332_VPA_CON2 0x84F8 324 #define MT6332_VPA_CON3 0x84FC 325 #define MT6332_VPA_CON4 0x84FE 326 #define MT6332_VPA_CON5 0x8500 327 #define MT6332_VPA_CON6 0x8502 328 #define MT6332_VPA_CON7 0x8504 329 #define MT6332_VPA_CON8 0x8506 330 #define MT6332_VPA_CON9 0x8508 331 #define MT6332_VPA_CON10 0x850A 332 #define MT6332_VPA_CON11 0x850C 333 #define MT6332_VPA_CON12 0x850E 334 #define MT6332_VPA_CON13 0x8510 335 #define MT6332_VPA_CON14 0x8512 336 #define MT6332_VPA_CON15 0x8514 337 #define MT6332_VPA_CON16 0x8516 338 #define MT6332_VPA_CON17 0x8518 339 #define MT6332_VPA_CON18 0x851A 340 #define MT6332_VPA_CON19 0x851C 341 #define MT6332_VPA_CON20 0x851E 342 #define MT6332_VPA_CON21 0x8520 343 #define MT6332_VPA_CON22 0x8522 344 #define MT6332_VPA_CON23 0x8524 345 #define MT6332_VPA_CON24 0x8526 346 #define MT6332_VPA_CON25 0x8528 347 #define MT6332_VSBST_CON0 0x852A 348 #define MT6332_VSBST_CON1 0x852C 349 #define MT6332_VSBST_CON2 0x852E 350 #define MT6332_VSBST_CON3 0x8530 351 #define MT6332_VSBST_CON4 0x8532 352 #define MT6332_VSBST_CON5 0x8534 353 #define MT6332_VSBST_CON6 0x8536 354 #define MT6332_VSBST_CON7 0x8538 355 #define MT6332_VSBST_CON8 0x853A 356 #define MT6332_VSBST_CON9 0x853C 357 #define MT6332_VSBST_CON10 0x853E 358 #define MT6332_VSBST_CON11 0x8540 359 #define MT6332_VSBST_CON12 0x8542 360 #define MT6332_VSBST_CON13 0x8544 361 #define MT6332_VSBST_CON14 0x8546 362 #define MT6332_VSBST_CON15 0x8548 363 #define MT6332_VSBST_CON16 0x854A 364 #define MT6332_VSBST_CON17 0x854C 365 #define MT6332_VSBST_CON18 0x854E 366 #define MT6332_VSBST_CON19 0x8550 367 #define MT6332_VSBST_CON20 0x8552 368 #define MT6332_VSBST_CON21 0x8554 369 #define MT6332_BUCK_K_CON0 0x8556 370 #define MT6332_BUCK_K_CON1 0x8558 371 #define MT6332_BUCK_K_CON2 0x855A 372 #define MT6332_BUCK_K_CON3 0x855C 373 #define MT6332_BUCK_K_CON4 0x855E 374 #define MT6332_BUCK_K_CON5 0x8560 375 #define MT6332_AUXADC_ADC0 0x8800 376 #define MT6332_AUXADC_ADC1 0x8802 377 #define MT6332_AUXADC_ADC2 0x8804 378 #define MT6332_AUXADC_ADC3 0x8806 379 #define MT6332_AUXADC_ADC4 0x8808 380 #define MT6332_AUXADC_ADC5 0x880A 381 #define MT6332_AUXADC_ADC6 0x880C 382 #define MT6332_AUXADC_ADC7 0x880E 383 #define MT6332_AUXADC_ADC8 0x8810 384 #define MT6332_AUXADC_ADC9 0x8812 385 #define MT6332_AUXADC_ADC10 0x8814 386 #define MT6332_AUXADC_ADC11 0x8816 387 #define MT6332_AUXADC_ADC12 0x8818 388 #define MT6332_AUXADC_ADC13 0x881A 389 #define MT6332_AUXADC_ADC14 0x881C 390 #define MT6332_AUXADC_ADC15 0x881E 391 #define MT6332_AUXADC_ADC16 0x8820 392 #define MT6332_AUXADC_ADC17 0x8822 393 #define MT6332_AUXADC_ADC18 0x8824 394 #define MT6332_AUXADC_ADC19 0x8826 395 #define MT6332_AUXADC_ADC20 0x8828 396 #define MT6332_AUXADC_ADC21 0x882A 397 #define MT6332_AUXADC_ADC22 0x882C 398 #define MT6332_AUXADC_ADC23 0x882E 399 #define MT6332_AUXADC_ADC24 0x8830 400 #define MT6332_AUXADC_ADC25 0x8832 401 #define MT6332_AUXADC_ADC26 0x8834 402 #define MT6332_AUXADC_ADC27 0x8836 403 #define MT6332_AUXADC_ADC28 0x8838 404 #define MT6332_AUXADC_ADC29 0x883A 405 #define MT6332_AUXADC_ADC30 0x883C 406 #define MT6332_AUXADC_ADC31 0x883E 407 #define MT6332_AUXADC_ADC32 0x8840 408 #define MT6332_AUXADC_ADC33 0x8842 409 #define MT6332_AUXADC_ADC34 0x8844 410 #define MT6332_AUXADC_ADC35 0x8846 411 #define MT6332_AUXADC_ADC36 0x8848 412 #define MT6332_AUXADC_ADC37 0x884A 413 #define MT6332_AUXADC_ADC38 0x884C 414 #define MT6332_AUXADC_ADC39 0x884E 415 #define MT6332_AUXADC_ADC40 0x8850 416 #define MT6332_AUXADC_ADC41 0x8852 417 #define MT6332_AUXADC_ADC42 0x8854 418 #define MT6332_AUXADC_ADC43 0x8856 419 #define MT6332_AUXADC_STA0 0x8858 420 #define MT6332_AUXADC_STA1 0x885A 421 #define MT6332_AUXADC_RQST0 0x885C 422 #define MT6332_AUXADC_RQST0_SET 0x885E 423 #define MT6332_AUXADC_RQST0_CLR 0x8860 424 #define MT6332_AUXADC_RQST1 0x8862 425 #define MT6332_AUXADC_RQST1_SET 0x8864 426 #define MT6332_AUXADC_RQST1_CLR 0x8866 427 #define MT6332_AUXADC_CON0 0x8868 428 #define MT6332_AUXADC_CON1 0x886A 429 #define MT6332_AUXADC_CON2 0x886C 430 #define MT6332_AUXADC_CON3 0x886E 431 #define MT6332_AUXADC_CON4 0x8870 432 #define MT6332_AUXADC_CON5 0x8872 433 #define MT6332_AUXADC_CON6 0x8874 434 #define MT6332_AUXADC_CON7 0x8876 435 #define MT6332_AUXADC_CON8 0x8878 436 #define MT6332_AUXADC_CON9 0x887A 437 #define MT6332_AUXADC_CON10 0x887C 438 #define MT6332_AUXADC_CON11 0x887E 439 #define MT6332_AUXADC_CON12 0x8880 440 #define MT6332_AUXADC_CON13 0x8882 441 #define MT6332_AUXADC_CON14 0x8884 442 #define MT6332_AUXADC_CON15 0x8886 443 #define MT6332_AUXADC_CON16 0x8888 444 #define MT6332_AUXADC_CON17 0x888A 445 #define MT6332_AUXADC_CON18 0x888C 446 #define MT6332_AUXADC_CON19 0x888E 447 #define MT6332_AUXADC_CON20 0x8890 448 #define MT6332_AUXADC_CON21 0x8892 449 #define MT6332_AUXADC_CON22 0x8894 450 #define MT6332_AUXADC_CON23 0x8896 451 #define MT6332_AUXADC_CON24 0x8898 452 #define MT6332_AUXADC_CON25 0x889A 453 #define MT6332_AUXADC_CON26 0x889C 454 #define MT6332_AUXADC_CON27 0x889E 455 #define MT6332_AUXADC_CON28 0x88A0 456 #define MT6332_AUXADC_CON29 0x88A2 457 #define MT6332_AUXADC_CON30 0x88A4 458 #define MT6332_AUXADC_CON31 0x88A6 459 #define MT6332_AUXADC_CON32 0x88A8 460 #define MT6332_AUXADC_CON33 0x88AA 461 #define MT6332_AUXADC_CON34 0x88AC 462 #define MT6332_AUXADC_CON35 0x88AE 463 #define MT6332_AUXADC_CON36 0x88B0 464 #define MT6332_AUXADC_CON37 0x88B2 465 #define MT6332_AUXADC_CON38 0x88B4 466 #define MT6332_AUXADC_CON39 0x88B6 467 #define MT6332_AUXADC_CON40 0x88B8 468 #define MT6332_AUXADC_CON41 0x88BA 469 #define MT6332_AUXADC_CON42 0x88BC 470 #define MT6332_AUXADC_CON43 0x88BE 471 #define MT6332_AUXADC_CON44 0x88C0 472 #define MT6332_AUXADC_CON45 0x88C2 473 #define MT6332_AUXADC_CON46 0x88C4 474 #define MT6332_AUXADC_CON47 0x88C6 475 #define MT6332_STRUP_CONA0 0x8C00 476 #define MT6332_STRUP_CONA1 0x8C02 477 #define MT6332_STRUP_CONA2 0x8C04 478 #define MT6332_STRUP_CON0 0x8C06 479 #define MT6332_STRUP_CON2 0x8C08 480 #define MT6332_STRUP_CON3 0x8C0A 481 #define MT6332_STRUP_CON4 0x8C0C 482 #define MT6332_STRUP_CON5 0x8C0E 483 #define MT6332_STRUP_CON6 0x8C10 484 #define MT6332_STRUP_CON7 0x8C12 485 #define MT6332_STRUP_CON8 0x8C14 486 #define MT6332_STRUP_CON9 0x8C16 487 #define MT6332_STRUP_CON10 0x8C18 488 #define MT6332_STRUP_CON11 0x8C1A 489 #define MT6332_STRUP_CON12 0x8C1C 490 #define MT6332_STRUP_CON13 0x8C1E 491 #define MT6332_STRUP_CON14 0x8C20 492 #define MT6332_STRUP_CON15 0x8C22 493 #define MT6332_STRUP_CON16 0x8C24 494 #define MT6332_STRUP_CON17 0x8C26 495 #define MT6332_FGADC_CON0 0x8C28 496 #define MT6332_FGADC_CON1 0x8C2A 497 #define MT6332_FGADC_CON2 0x8C2C 498 #define MT6332_FGADC_CON3 0x8C2E 499 #define MT6332_FGADC_CON4 0x8C30 500 #define MT6332_FGADC_CON5 0x8C32 501 #define MT6332_FGADC_CON6 0x8C34 502 #define MT6332_FGADC_CON7 0x8C36 503 #define MT6332_FGADC_CON8 0x8C38 504 #define MT6332_FGADC_CON9 0x8C3A 505 #define MT6332_FGADC_CON10 0x8C3C 506 #define MT6332_FGADC_CON11 0x8C3E 507 #define MT6332_FGADC_CON12 0x8C40 508 #define MT6332_FGADC_CON13 0x8C42 509 #define MT6332_FGADC_CON14 0x8C44 510 #define MT6332_FGADC_CON15 0x8C46 511 #define MT6332_FGADC_CON16 0x8C48 512 #define MT6332_FGADC_CON17 0x8C4A 513 #define MT6332_FGADC_CON18 0x8C4C 514 #define MT6332_FGADC_CON19 0x8C4E 515 #define MT6332_FGADC_CON20 0x8C50 516 #define MT6332_FGADC_CON21 0x8C52 517 #define MT6332_FGADC_CON22 0x8C54 518 #define MT6332_OTP_CON0 0x8C56 519 #define MT6332_OTP_CON1 0x8C58 520 #define MT6332_OTP_CON2 0x8C5A 521 #define MT6332_OTP_CON3 0x8C5C 522 #define MT6332_OTP_CON4 0x8C5E 523 #define MT6332_OTP_CON5 0x8C60 524 #define MT6332_OTP_CON6 0x8C62 525 #define MT6332_OTP_CON7 0x8C64 526 #define MT6332_OTP_CON8 0x8C66 527 #define MT6332_OTP_CON9 0x8C68 528 #define MT6332_OTP_CON10 0x8C6A 529 #define MT6332_OTP_CON11 0x8C6C 530 #define MT6332_OTP_CON12 0x8C6E 531 #define MT6332_OTP_CON13 0x8C70 532 #define MT6332_OTP_CON14 0x8C72 533 #define MT6332_OTP_DOUT_0_15 0x8C74 534 #define MT6332_OTP_DOUT_16_31 0x8C76 535 #define MT6332_OTP_DOUT_32_47 0x8C78 536 #define MT6332_OTP_DOUT_48_63 0x8C7A 537 #define MT6332_OTP_DOUT_64_79 0x8C7C 538 #define MT6332_OTP_DOUT_80_95 0x8C7E 539 #define MT6332_OTP_DOUT_96_111 0x8C80 540 #define MT6332_OTP_DOUT_112_127 0x8C82 541 #define MT6332_OTP_DOUT_128_143 0x8C84 542 #define MT6332_OTP_DOUT_144_159 0x8C86 543 #define MT6332_OTP_DOUT_160_175 0x8C88 544 #define MT6332_OTP_DOUT_176_191 0x8C8A 545 #define MT6332_OTP_DOUT_192_207 0x8C8C 546 #define MT6332_OTP_DOUT_208_223 0x8C8E 547 #define MT6332_OTP_DOUT_224_239 0x8C90 548 #define MT6332_OTP_DOUT_240_255 0x8C92 549 #define MT6332_OTP_VAL_0_15 0x8C94 550 #define MT6332_OTP_VAL_16_31 0x8C96 551 #define MT6332_OTP_VAL_32_47 0x8C98 552 #define MT6332_OTP_VAL_48_63 0x8C9A 553 #define MT6332_OTP_VAL_64_79 0x8C9C 554 #define MT6332_OTP_VAL_80_95 0x8C9E 555 #define MT6332_OTP_VAL_96_111 0x8CA0 556 #define MT6332_OTP_VAL_112_127 0x8CA2 557 #define MT6332_OTP_VAL_128_143 0x8CA4 558 #define MT6332_OTP_VAL_144_159 0x8CA6 559 #define MT6332_OTP_VAL_160_175 0x8CA8 560 #define MT6332_OTP_VAL_176_191 0x8CAA 561 #define MT6332_OTP_VAL_192_207 0x8CAC 562 #define MT6332_OTP_VAL_208_223 0x8CAE 563 #define MT6332_OTP_VAL_224_239 0x8CB0 564 #define MT6332_OTP_VAL_240_255 0x8CB2 565 #define MT6332_LDO_CON0 0x8CB4 566 #define MT6332_LDO_CON1 0x8CB6 567 #define MT6332_LDO_CON2 0x8CB8 568 #define MT6332_LDO_CON3 0x8CBA 569 #define MT6332_LDO_CON5 0x8CBC 570 #define MT6332_LDO_CON6 0x8CBE 571 #define MT6332_LDO_CON7 0x8CC0 572 #define MT6332_LDO_CON8 0x8CC2 573 #define MT6332_LDO_CON9 0x8CC4 574 #define MT6332_LDO_CON10 0x8CC6 575 #define MT6332_LDO_CON11 0x8CC8 576 #define MT6332_LDO_CON12 0x8CCA 577 #define MT6332_LDO_CON13 0x8CCC 578 #define MT6332_FQMTR_CON0 0x8CCE 579 #define MT6332_FQMTR_CON1 0x8CD0 580 #define MT6332_FQMTR_CON2 0x8CD2 581 #define MT6332_IWLED_CON0 0x8CD4 582 #define MT6332_IWLED_DEG 0x8CD6 583 #define MT6332_IWLED_STATUS 0x8CD8 584 #define MT6332_IWLED_EN_CTRL 0x8CDA 585 #define MT6332_IWLED_CON1 0x8CDC 586 #define MT6332_IWLED_CON2 0x8CDE 587 #define MT6332_IWLED_TRIM0 0x8CE0 588 #define MT6332_IWLED_TRIM1 0x8CE2 589 #define MT6332_IWLED_CON3 0x8CE4 590 #define MT6332_IWLED_CON4 0x8CE6 591 #define MT6332_IWLED_CON5 0x8CE8 592 #define MT6332_IWLED_CON6 0x8CEA 593 #define MT6332_IWLED_CON7 0x8CEC 594 #define MT6332_IWLED_CON8 0x8CEE 595 #define MT6332_IWLED_CON9 0x8CF0 596 #define MT6332_SPK_CON0 0x8CF2 597 #define MT6332_SPK_CON1 0x8CF4 598 #define MT6332_SPK_CON2 0x8CF6 599 #define MT6332_SPK_CON3 0x8CF8 600 #define MT6332_SPK_CON4 0x8CFA 601 #define MT6332_SPK_CON5 0x8CFC 602 #define MT6332_SPK_CON6 0x8CFE 603 #define MT6332_SPK_CON7 0x8D00 604 #define MT6332_SPK_CON8 0x8D02 605 #define MT6332_SPK_CON9 0x8D04 606 #define MT6332_SPK_CON10 0x8D06 607 #define MT6332_SPK_CON11 0x8D08 608 #define MT6332_SPK_CON12 0x8D0A 609 #define MT6332_SPK_CON13 0x8D0C 610 #define MT6332_SPK_CON14 0x8D0E 611 #define MT6332_SPK_CON15 0x8D10 612 #define MT6332_SPK_CON16 0x8D12 613 #define MT6332_TESTI_CON0 0x8D14 614 #define MT6332_TESTI_CON1 0x8D16 615 #define MT6332_TESTI_CON2 0x8D18 616 #define MT6332_TESTI_CON3 0x8D1A 617 #define MT6332_TESTI_CON4 0x8D1C 618 #define MT6332_TESTI_CON5 0x8D1E 619 #define MT6332_TESTI_CON6 0x8D20 620 #define MT6332_TESTI_MUX_CON0 0x8D22 621 #define MT6332_TESTI_MUX_CON1 0x8D24 622 #define MT6332_TESTI_MUX_CON2 0x8D26 623 #define MT6332_TESTI_MUX_CON3 0x8D28 624 #define MT6332_TESTI_MUX_CON4 0x8D2A 625 #define MT6332_TESTI_MUX_CON5 0x8D2C 626 #define MT6332_TESTI_MUX_CON6 0x8D2E 627 #define MT6332_TESTO_CON0 0x8D30 628 #define MT6332_TESTO_CON1 0x8D32 629 #define MT6332_TEST_OMUX_CON0 0x8D34 630 #define MT6332_TEST_OMUX_CON1 0x8D36 631 #define MT6332_DEBUG_CON0 0x8D38 632 #define MT6332_DEBUG_CON1 0x8D3A 633 #define MT6332_DEBUG_CON2 0x8D3C 634 #define MT6332_FGADC_CON23 0x8D3E 635 #define MT6332_FGADC_CON24 0x8D40 636 #define MT6332_FGADC_CON25 0x8D42 637 #define MT6332_TOP_RST_STATUS 0x8D44 638 #define MT6332_TOP_RST_STATUS_SET 0x8D46 639 #define MT6332_TOP_RST_STATUS_CLR 0x8D48 640 #define MT6332_VDVFS2_CON28 0x8D4A 641 642 #endif /* __MFD_MT6332_REGISTERS_H__ */ 643
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