1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* 2 /*
3 * TI Palmas 3 * TI Palmas
4 * 4 *
5 * Copyright 2011-2013 Texas Instruments Inc. 5 * Copyright 2011-2013 Texas Instruments Inc.
6 * 6 *
7 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * Author: Ian Lartey <ian@slimlogic.co.uk> 8 * Author: Ian Lartey <ian@slimlogic.co.uk>
9 */ 9 */
10 10
11 #ifndef __LINUX_MFD_PALMAS_H 11 #ifndef __LINUX_MFD_PALMAS_H
12 #define __LINUX_MFD_PALMAS_H 12 #define __LINUX_MFD_PALMAS_H
13 13
14 #include <linux/usb/otg.h> 14 #include <linux/usb/otg.h>
15 #include <linux/leds.h> 15 #include <linux/leds.h>
16 #include <linux/regmap.h> 16 #include <linux/regmap.h>
17 #include <linux/regulator/driver.h> 17 #include <linux/regulator/driver.h>
18 #include <linux/extcon-provider.h> 18 #include <linux/extcon-provider.h>
>> 19 #include <linux/of_gpio.h>
19 #include <linux/usb/phy_companion.h> 20 #include <linux/usb/phy_companion.h>
20 21
21 #define PALMAS_NUM_CLIENTS 3 22 #define PALMAS_NUM_CLIENTS 3
22 23
23 /* The ID_REVISION NUMBERS */ 24 /* The ID_REVISION NUMBERS */
24 #define PALMAS_CHIP_OLD_ID 0x0000 25 #define PALMAS_CHIP_OLD_ID 0x0000
25 #define PALMAS_CHIP_ID 0xC035 26 #define PALMAS_CHIP_ID 0xC035
26 #define PALMAS_CHIP_CHARGER_ID 0xC036 27 #define PALMAS_CHIP_CHARGER_ID 0xC036
27 28
28 #define TPS65917_RESERVED -1 29 #define TPS65917_RESERVED -1
29 30
30 #define is_palmas(a) (((a) == PALMAS_CHIP_O 31 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
31 ((a) == PALMAS_CHIP_ID 32 ((a) == PALMAS_CHIP_ID))
32 #define is_palmas_charger(a) ((a) == PALMAS_CH 33 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
33 34
34 /** 35 /**
35 * Palmas PMIC feature types 36 * Palmas PMIC feature types
36 * 37 *
37 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used whe 38 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
38 * regulator. 39 * regulator.
39 * 40 *
40 * PALMAS_PMIC_HAS(b, f) - macro to check if a 41 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
41 * specific feature (above) or not. Retur 42 * specific feature (above) or not. Return non-zero, if yes.
42 */ 43 */
43 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST 44 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
44 #define PALMAS_PMIC_HAS(b, f) 45 #define PALMAS_PMIC_HAS(b, f) \
45 ((b)->features & PALMA 46 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
46 47
47 struct palmas_pmic; 48 struct palmas_pmic;
48 struct palmas_gpadc; 49 struct palmas_gpadc;
49 struct palmas_resource; 50 struct palmas_resource;
50 struct palmas_usb; 51 struct palmas_usb;
51 struct palmas_pmic_driver_data; 52 struct palmas_pmic_driver_data;
52 struct palmas_pmic_platform_data; 53 struct palmas_pmic_platform_data;
53 54
54 enum palmas_usb_state { 55 enum palmas_usb_state {
55 PALMAS_USB_STATE_DISCONNECT, 56 PALMAS_USB_STATE_DISCONNECT,
56 PALMAS_USB_STATE_VBUS, 57 PALMAS_USB_STATE_VBUS,
57 PALMAS_USB_STATE_ID, 58 PALMAS_USB_STATE_ID,
58 }; 59 };
59 60
60 struct palmas { 61 struct palmas {
61 struct device *dev; 62 struct device *dev;
62 63
63 struct i2c_client *i2c_clients[PALMAS_ 64 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
64 struct regmap *regmap[PALMAS_NUM_CLIEN 65 struct regmap *regmap[PALMAS_NUM_CLIENTS];
65 66
66 /* Stored chip id */ 67 /* Stored chip id */
67 int id; 68 int id;
68 69
69 unsigned int features; 70 unsigned int features;
70 /* IRQ Data */ 71 /* IRQ Data */
71 int irq; 72 int irq;
72 u32 irq_mask; 73 u32 irq_mask;
73 struct mutex irq_lock; 74 struct mutex irq_lock;
74 struct regmap_irq_chip_data *irq_data; 75 struct regmap_irq_chip_data *irq_data;
75 76
76 struct palmas_pmic_driver_data *pmic_d 77 struct palmas_pmic_driver_data *pmic_ddata;
77 78
78 /* Child Devices */ 79 /* Child Devices */
79 struct palmas_pmic *pmic; 80 struct palmas_pmic *pmic;
80 struct palmas_gpadc *gpadc; 81 struct palmas_gpadc *gpadc;
81 struct palmas_resource *resource; 82 struct palmas_resource *resource;
82 struct palmas_usb *usb; 83 struct palmas_usb *usb;
83 84
84 /* GPIO MUXing */ 85 /* GPIO MUXing */
85 u8 gpio_muxed; 86 u8 gpio_muxed;
86 u8 led_muxed; 87 u8 led_muxed;
87 u8 pwm_muxed; 88 u8 pwm_muxed;
88 }; 89 };
89 90
90 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENA 91 #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
91 PALMAS_EXT_CONTROL_ENA 92 PALMAS_EXT_CONTROL_ENABLE2 | \
92 PALMAS_EXT_CONTROL_NSL 93 PALMAS_EXT_CONTROL_NSLEEP)
93 94
94 struct palmas_sleep_requestor_info { 95 struct palmas_sleep_requestor_info {
95 int id; 96 int id;
96 int reg_offset; 97 int reg_offset;
97 int bit_pos; 98 int bit_pos;
98 }; 99 };
99 100
100 struct palmas_regs_info { 101 struct palmas_regs_info {
101 char *name; 102 char *name;
102 char *sname; 103 char *sname;
103 u8 vsel_addr; 104 u8 vsel_addr;
104 u8 ctrl_addr; 105 u8 ctrl_addr;
105 u8 tstep_addr; 106 u8 tstep_addr;
106 int sleep_id; 107 int sleep_id;
107 }; 108 };
108 109
109 struct palmas_pmic_driver_data { 110 struct palmas_pmic_driver_data {
110 int smps_start; 111 int smps_start;
111 int smps_end; 112 int smps_end;
112 int ldo_begin; 113 int ldo_begin;
113 int ldo_end; 114 int ldo_end;
114 int max_reg; 115 int max_reg;
115 bool has_regen3; 116 bool has_regen3;
116 struct palmas_regs_info *palmas_regs_i 117 struct palmas_regs_info *palmas_regs_info;
117 struct of_regulator_match *palmas_matc 118 struct of_regulator_match *palmas_matches;
118 struct palmas_sleep_requestor_info *sl 119 struct palmas_sleep_requestor_info *sleep_req_info;
119 int (*smps_register)(struct palmas_pmi 120 int (*smps_register)(struct palmas_pmic *pmic,
120 struct palmas_pmi 121 struct palmas_pmic_driver_data *ddata,
121 struct palmas_pmi 122 struct palmas_pmic_platform_data *pdata,
122 const char *pdev_ 123 const char *pdev_name,
123 struct regulator_ 124 struct regulator_config config);
124 int (*ldo_register)(struct palmas_pmic 125 int (*ldo_register)(struct palmas_pmic *pmic,
125 struct palmas_pmic 126 struct palmas_pmic_driver_data *ddata,
126 struct palmas_pmic 127 struct palmas_pmic_platform_data *pdata,
127 const char *pdev_n 128 const char *pdev_name,
128 struct regulator_c 129 struct regulator_config config);
129 }; 130 };
130 131
>> 132 struct palmas_adc_wakeup_property {
>> 133 int adc_channel_number;
>> 134 int adc_high_threshold;
>> 135 int adc_low_threshold;
>> 136 };
>> 137
131 struct palmas_gpadc_platform_data { 138 struct palmas_gpadc_platform_data {
132 /* Channel 3 current source is only en 139 /* Channel 3 current source is only enabled during conversion */
133 int ch3_current; /* 0: off; 1: 140 int ch3_current; /* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */
134 141
135 /* Channel 0 current source can be use 142 /* Channel 0 current source can be used for battery detection.
136 * If used for battery detection this 143 * If used for battery detection this will cause a permanent current
137 * consumption depending on current le 144 * consumption depending on current level set here.
138 */ 145 */
139 int ch0_current; /* 0: off; 1: 146 int ch0_current; /* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
140 bool extended_delay; /* use extende 147 bool extended_delay; /* use extended delay for conversion */
141 148
142 /* default BAT_REMOVAL_DAT setting on 149 /* default BAT_REMOVAL_DAT setting on device probe */
143 int bat_removal; 150 int bat_removal;
144 151
145 /* Sets the START_POLARITY bit in the 152 /* Sets the START_POLARITY bit in the RT_CTRL register */
146 int start_polarity; 153 int start_polarity;
147 154
148 int auto_conversion_period_ms; 155 int auto_conversion_period_ms;
>> 156 struct palmas_adc_wakeup_property *adc_wakeup1_data;
>> 157 struct palmas_adc_wakeup_property *adc_wakeup2_data;
149 }; 158 };
150 159
151 struct palmas_reg_init { 160 struct palmas_reg_init {
152 /* warm_rest controls the voltage leve 161 /* warm_rest controls the voltage levels after a warm reset
153 * 162 *
154 * 0: reload default values from OTP o 163 * 0: reload default values from OTP on warm reset
155 * 1: maintain voltage from VSEL on wa 164 * 1: maintain voltage from VSEL on warm reset
156 */ 165 */
157 int warm_reset; 166 int warm_reset;
158 167
159 /* roof_floor controls whether the reg 168 /* roof_floor controls whether the regulator uses the i2c style
160 * of DVS or uses the method where a G 169 * of DVS or uses the method where a GPIO or other control method is
161 * attached to the NSLEEP/ENABLE1/ENAB 170 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
162 * 171 *
163 * For SMPS 172 * For SMPS
164 * 173 *
165 * 0: i2c selection of voltage 174 * 0: i2c selection of voltage
166 * 1: pin selection of voltage. 175 * 1: pin selection of voltage.
167 * 176 *
168 * For LDO unused 177 * For LDO unused
169 */ 178 */
170 int roof_floor; 179 int roof_floor;
171 180
172 /* sleep_mode is the mode loaded to MO 181 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
173 * the data sheet. 182 * the data sheet.
174 * 183 *
175 * For SMPS 184 * For SMPS
176 * 185 *
177 * 0: Off 186 * 0: Off
178 * 1: AUTO 187 * 1: AUTO
179 * 2: ECO 188 * 2: ECO
180 * 3: Forced PWM 189 * 3: Forced PWM
181 * 190 *
182 * For LDO 191 * For LDO
183 * 192 *
184 * 0: Off 193 * 0: Off
185 * 1: On 194 * 1: On
186 */ 195 */
187 int mode_sleep; 196 int mode_sleep;
188 197
189 /* voltage_sel is the bitfield loaded 198 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
190 * register. Set this is the default v 199 * register. Set this is the default voltage set in OTP needs
191 * to be overridden. 200 * to be overridden.
192 */ 201 */
193 u8 vsel; 202 u8 vsel;
194 203
195 }; 204 };
196 205
197 enum palmas_regulators { 206 enum palmas_regulators {
198 /* SMPS regulators */ 207 /* SMPS regulators */
199 PALMAS_REG_SMPS12, 208 PALMAS_REG_SMPS12,
200 PALMAS_REG_SMPS123, 209 PALMAS_REG_SMPS123,
201 PALMAS_REG_SMPS3, 210 PALMAS_REG_SMPS3,
202 PALMAS_REG_SMPS45, 211 PALMAS_REG_SMPS45,
203 PALMAS_REG_SMPS457, 212 PALMAS_REG_SMPS457,
204 PALMAS_REG_SMPS6, 213 PALMAS_REG_SMPS6,
205 PALMAS_REG_SMPS7, 214 PALMAS_REG_SMPS7,
206 PALMAS_REG_SMPS8, 215 PALMAS_REG_SMPS8,
207 PALMAS_REG_SMPS9, 216 PALMAS_REG_SMPS9,
208 PALMAS_REG_SMPS10_OUT2, 217 PALMAS_REG_SMPS10_OUT2,
209 PALMAS_REG_SMPS10_OUT1, 218 PALMAS_REG_SMPS10_OUT1,
210 /* LDO regulators */ 219 /* LDO regulators */
211 PALMAS_REG_LDO1, 220 PALMAS_REG_LDO1,
212 PALMAS_REG_LDO2, 221 PALMAS_REG_LDO2,
213 PALMAS_REG_LDO3, 222 PALMAS_REG_LDO3,
214 PALMAS_REG_LDO4, 223 PALMAS_REG_LDO4,
215 PALMAS_REG_LDO5, 224 PALMAS_REG_LDO5,
216 PALMAS_REG_LDO6, 225 PALMAS_REG_LDO6,
217 PALMAS_REG_LDO7, 226 PALMAS_REG_LDO7,
218 PALMAS_REG_LDO8, 227 PALMAS_REG_LDO8,
219 PALMAS_REG_LDO9, 228 PALMAS_REG_LDO9,
220 PALMAS_REG_LDOLN, 229 PALMAS_REG_LDOLN,
221 PALMAS_REG_LDOUSB, 230 PALMAS_REG_LDOUSB,
222 /* External regulators */ 231 /* External regulators */
223 PALMAS_REG_REGEN1, 232 PALMAS_REG_REGEN1,
224 PALMAS_REG_REGEN2, 233 PALMAS_REG_REGEN2,
225 PALMAS_REG_REGEN3, 234 PALMAS_REG_REGEN3,
226 PALMAS_REG_SYSEN1, 235 PALMAS_REG_SYSEN1,
227 PALMAS_REG_SYSEN2, 236 PALMAS_REG_SYSEN2,
228 /* Total number of regulators */ 237 /* Total number of regulators */
229 PALMAS_NUM_REGS, 238 PALMAS_NUM_REGS,
230 }; 239 };
231 240
232 enum tps65917_regulators { 241 enum tps65917_regulators {
233 /* SMPS regulators */ 242 /* SMPS regulators */
234 TPS65917_REG_SMPS1, 243 TPS65917_REG_SMPS1,
235 TPS65917_REG_SMPS2, 244 TPS65917_REG_SMPS2,
236 TPS65917_REG_SMPS3, 245 TPS65917_REG_SMPS3,
237 TPS65917_REG_SMPS4, 246 TPS65917_REG_SMPS4,
238 TPS65917_REG_SMPS5, 247 TPS65917_REG_SMPS5,
239 TPS65917_REG_SMPS12, 248 TPS65917_REG_SMPS12,
240 /* LDO regulators */ 249 /* LDO regulators */
241 TPS65917_REG_LDO1, 250 TPS65917_REG_LDO1,
242 TPS65917_REG_LDO2, 251 TPS65917_REG_LDO2,
243 TPS65917_REG_LDO3, 252 TPS65917_REG_LDO3,
244 TPS65917_REG_LDO4, 253 TPS65917_REG_LDO4,
245 TPS65917_REG_LDO5, 254 TPS65917_REG_LDO5,
246 TPS65917_REG_REGEN1, 255 TPS65917_REG_REGEN1,
247 TPS65917_REG_REGEN2, 256 TPS65917_REG_REGEN2,
248 TPS65917_REG_REGEN3, 257 TPS65917_REG_REGEN3,
249 258
250 /* Total number of regulators */ 259 /* Total number of regulators */
251 TPS65917_NUM_REGS, 260 TPS65917_NUM_REGS,
252 }; 261 };
253 262
254 /* External controll signal name */ 263 /* External controll signal name */
255 enum { 264 enum {
256 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 265 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
257 PALMAS_EXT_CONTROL_ENABLE2 = 0x2, 266 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
258 PALMAS_EXT_CONTROL_NSLEEP = 0x4, 267 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
259 }; 268 };
260 269
261 /* 270 /*
262 * Palmas device resources can be controlled e 271 * Palmas device resources can be controlled externally for
263 * enabling/disabling it rather than register 272 * enabling/disabling it rather than register write through i2c.
264 * Add the external controlled requestor ID fo 273 * Add the external controlled requestor ID for different resources.
265 */ 274 */
266 enum palmas_external_requestor_id { 275 enum palmas_external_requestor_id {
267 PALMAS_EXTERNAL_REQSTR_ID_REGEN1, 276 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
268 PALMAS_EXTERNAL_REQSTR_ID_REGEN2, 277 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
269 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, 278 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
270 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, 279 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
271 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG, 280 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
272 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO 281 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
273 PALMAS_EXTERNAL_REQSTR_ID_REGEN3, 282 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
274 PALMAS_EXTERNAL_REQSTR_ID_SMPS12, 283 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
275 PALMAS_EXTERNAL_REQSTR_ID_SMPS3, 284 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
276 PALMAS_EXTERNAL_REQSTR_ID_SMPS45, 285 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
277 PALMAS_EXTERNAL_REQSTR_ID_SMPS6, 286 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
278 PALMAS_EXTERNAL_REQSTR_ID_SMPS7, 287 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
279 PALMAS_EXTERNAL_REQSTR_ID_SMPS8, 288 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
280 PALMAS_EXTERNAL_REQSTR_ID_SMPS9, 289 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
281 PALMAS_EXTERNAL_REQSTR_ID_SMPS10, 290 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
282 PALMAS_EXTERNAL_REQSTR_ID_LDO1, 291 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
283 PALMAS_EXTERNAL_REQSTR_ID_LDO2, 292 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
284 PALMAS_EXTERNAL_REQSTR_ID_LDO3, 293 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
285 PALMAS_EXTERNAL_REQSTR_ID_LDO4, 294 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
286 PALMAS_EXTERNAL_REQSTR_ID_LDO5, 295 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
287 PALMAS_EXTERNAL_REQSTR_ID_LDO6, 296 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
288 PALMAS_EXTERNAL_REQSTR_ID_LDO7, 297 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
289 PALMAS_EXTERNAL_REQSTR_ID_LDO8, 298 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
290 PALMAS_EXTERNAL_REQSTR_ID_LDO9, 299 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
291 PALMAS_EXTERNAL_REQSTR_ID_LDOLN, 300 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
292 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, 301 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
293 302
294 /* Last entry */ 303 /* Last entry */
295 PALMAS_EXTERNAL_REQSTR_ID_MAX, 304 PALMAS_EXTERNAL_REQSTR_ID_MAX,
296 }; 305 };
297 306
298 enum tps65917_external_requestor_id { 307 enum tps65917_external_requestor_id {
299 TPS65917_EXTERNAL_REQSTR_ID_REGEN1, 308 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
300 TPS65917_EXTERNAL_REQSTR_ID_REGEN2, 309 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
301 TPS65917_EXTERNAL_REQSTR_ID_REGEN3, 310 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
302 TPS65917_EXTERNAL_REQSTR_ID_SMPS1, 311 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
303 TPS65917_EXTERNAL_REQSTR_ID_SMPS2, 312 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
304 TPS65917_EXTERNAL_REQSTR_ID_SMPS3, 313 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
305 TPS65917_EXTERNAL_REQSTR_ID_SMPS4, 314 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
306 TPS65917_EXTERNAL_REQSTR_ID_SMPS5, 315 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
307 TPS65917_EXTERNAL_REQSTR_ID_SMPS12, 316 TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
308 TPS65917_EXTERNAL_REQSTR_ID_LDO1, 317 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
309 TPS65917_EXTERNAL_REQSTR_ID_LDO2, 318 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
310 TPS65917_EXTERNAL_REQSTR_ID_LDO3, 319 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
311 TPS65917_EXTERNAL_REQSTR_ID_LDO4, 320 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
312 TPS65917_EXTERNAL_REQSTR_ID_LDO5, 321 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
313 /* Last entry */ 322 /* Last entry */
314 TPS65917_EXTERNAL_REQSTR_ID_MAX, 323 TPS65917_EXTERNAL_REQSTR_ID_MAX,
315 }; 324 };
316 325
317 struct palmas_pmic_platform_data { 326 struct palmas_pmic_platform_data {
318 /* An array of pointers to regulator i 327 /* An array of pointers to regulator init data indexed by regulator
319 * ID 328 * ID
320 */ 329 */
321 struct regulator_init_data *reg_data[P 330 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
322 331
323 /* An array of pointers to structures 332 /* An array of pointers to structures containing sleep mode and DVS
324 * configuration for regulators indexe 333 * configuration for regulators indexed by ID
325 */ 334 */
326 struct palmas_reg_init *reg_init[PALMA 335 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
327 336
328 /* use LDO6 for vibrator control */ 337 /* use LDO6 for vibrator control */
329 int ldo6_vibrator; 338 int ldo6_vibrator;
330 339
331 /* Enable tracking mode of LDO8 */ 340 /* Enable tracking mode of LDO8 */
332 bool enable_ldo8_tracking; 341 bool enable_ldo8_tracking;
333 }; 342 };
334 343
335 struct palmas_usb_platform_data { 344 struct palmas_usb_platform_data {
336 /* Do we enable the wakeup comparator 345 /* Do we enable the wakeup comparator on probe */
337 int wakeup; 346 int wakeup;
338 }; 347 };
339 348
340 struct palmas_resource_platform_data { 349 struct palmas_resource_platform_data {
341 int regen1_mode_sleep; 350 int regen1_mode_sleep;
342 int regen2_mode_sleep; 351 int regen2_mode_sleep;
343 int sysen1_mode_sleep; 352 int sysen1_mode_sleep;
344 int sysen2_mode_sleep; 353 int sysen2_mode_sleep;
345 354
346 /* bitfield to be loaded to NSLEEP_RES 355 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
347 u8 nsleep_res; 356 u8 nsleep_res;
348 /* bitfield to be loaded to NSLEEP_SMP 357 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
349 u8 nsleep_smps; 358 u8 nsleep_smps;
350 /* bitfield to be loaded to NSLEEP_LDO 359 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
351 u8 nsleep_ldo1; 360 u8 nsleep_ldo1;
352 /* bitfield to be loaded to NSLEEP_LDO 361 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
353 u8 nsleep_ldo2; 362 u8 nsleep_ldo2;
354 363
355 /* bitfield to be loaded to ENABLE1_RE 364 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
356 u8 enable1_res; 365 u8 enable1_res;
357 /* bitfield to be loaded to ENABLE1_SM 366 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
358 u8 enable1_smps; 367 u8 enable1_smps;
359 /* bitfield to be loaded to ENABLE1_LD 368 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
360 u8 enable1_ldo1; 369 u8 enable1_ldo1;
361 /* bitfield to be loaded to ENABLE1_LD 370 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
362 u8 enable1_ldo2; 371 u8 enable1_ldo2;
363 372
364 /* bitfield to be loaded to ENABLE2_RE 373 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
365 u8 enable2_res; 374 u8 enable2_res;
366 /* bitfield to be loaded to ENABLE2_SM 375 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
367 u8 enable2_smps; 376 u8 enable2_smps;
368 /* bitfield to be loaded to ENABLE2_LD 377 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
369 u8 enable2_ldo1; 378 u8 enable2_ldo1;
370 /* bitfield to be loaded to ENABLE2_LD 379 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
371 u8 enable2_ldo2; 380 u8 enable2_ldo2;
372 }; 381 };
373 382
374 struct palmas_clk_platform_data { 383 struct palmas_clk_platform_data {
375 int clk32kg_mode_sleep; 384 int clk32kg_mode_sleep;
376 int clk32kgaudio_mode_sleep; 385 int clk32kgaudio_mode_sleep;
377 }; 386 };
378 387
379 struct palmas_platform_data { 388 struct palmas_platform_data {
380 int irq_flags; 389 int irq_flags;
381 int gpio_base; 390 int gpio_base;
382 391
383 /* bit value to be loaded to the POWER 392 /* bit value to be loaded to the POWER_CTRL register */
384 u8 power_ctrl; 393 u8 power_ctrl;
385 394
386 /* 395 /*
387 * boolean to select if we want to con 396 * boolean to select if we want to configure muxing here
388 * then the two value to load into the 397 * then the two value to load into the registers if true
389 */ 398 */
390 int mux_from_pdata; 399 int mux_from_pdata;
391 u8 pad1, pad2; 400 u8 pad1, pad2;
392 bool pm_off; 401 bool pm_off;
393 402
394 struct palmas_pmic_platform_data *pmic 403 struct palmas_pmic_platform_data *pmic_pdata;
395 struct palmas_gpadc_platform_data *gpa 404 struct palmas_gpadc_platform_data *gpadc_pdata;
396 struct palmas_usb_platform_data *usb_p 405 struct palmas_usb_platform_data *usb_pdata;
397 struct palmas_resource_platform_data * 406 struct palmas_resource_platform_data *resource_pdata;
398 struct palmas_clk_platform_data *clk_p 407 struct palmas_clk_platform_data *clk_pdata;
399 }; 408 };
400 409
401 struct palmas_gpadc_calibration { 410 struct palmas_gpadc_calibration {
402 s32 gain; 411 s32 gain;
403 s32 gain_error; 412 s32 gain_error;
404 s32 offset_error; 413 s32 offset_error;
405 }; 414 };
406 415
407 #define PALMAS_DATASHEET_NAME(_name) "palma 416 #define PALMAS_DATASHEET_NAME(_name) "palmas-gpadc-chan-"#_name
408 417
409 struct palmas_gpadc_result { 418 struct palmas_gpadc_result {
410 s32 raw_code; 419 s32 raw_code;
411 s32 corrected_code; 420 s32 corrected_code;
412 s32 result; 421 s32 result;
413 }; 422 };
414 423
415 #define PALMAS_MAX_CHANNELS 16 424 #define PALMAS_MAX_CHANNELS 16
416 425
417 /* Define the tps65917 IRQ numbers */ 426 /* Define the tps65917 IRQ numbers */
418 enum tps65917_irqs { 427 enum tps65917_irqs {
419 /* INT1 registers */ 428 /* INT1 registers */
420 TPS65917_RESERVED1, 429 TPS65917_RESERVED1,
421 TPS65917_PWRON_IRQ, 430 TPS65917_PWRON_IRQ,
422 TPS65917_LONG_PRESS_KEY_IRQ, 431 TPS65917_LONG_PRESS_KEY_IRQ,
423 TPS65917_RESERVED2, 432 TPS65917_RESERVED2,
424 TPS65917_PWRDOWN_IRQ, 433 TPS65917_PWRDOWN_IRQ,
425 TPS65917_HOTDIE_IRQ, 434 TPS65917_HOTDIE_IRQ,
426 TPS65917_VSYS_MON_IRQ, 435 TPS65917_VSYS_MON_IRQ,
427 TPS65917_RESERVED3, 436 TPS65917_RESERVED3,
428 /* INT2 registers */ 437 /* INT2 registers */
429 TPS65917_RESERVED4, 438 TPS65917_RESERVED4,
430 TPS65917_OTP_ERROR_IRQ, 439 TPS65917_OTP_ERROR_IRQ,
431 TPS65917_WDT_IRQ, 440 TPS65917_WDT_IRQ,
432 TPS65917_RESERVED5, 441 TPS65917_RESERVED5,
433 TPS65917_RESET_IN_IRQ, 442 TPS65917_RESET_IN_IRQ,
434 TPS65917_FSD_IRQ, 443 TPS65917_FSD_IRQ,
435 TPS65917_SHORT_IRQ, 444 TPS65917_SHORT_IRQ,
436 TPS65917_RESERVED6, 445 TPS65917_RESERVED6,
437 /* INT3 registers */ 446 /* INT3 registers */
438 TPS65917_GPADC_AUTO_0_IRQ, 447 TPS65917_GPADC_AUTO_0_IRQ,
439 TPS65917_GPADC_AUTO_1_IRQ, 448 TPS65917_GPADC_AUTO_1_IRQ,
440 TPS65917_GPADC_EOC_SW_IRQ, 449 TPS65917_GPADC_EOC_SW_IRQ,
441 TPS65917_RESREVED6, 450 TPS65917_RESREVED6,
442 TPS65917_RESERVED7, 451 TPS65917_RESERVED7,
443 TPS65917_RESERVED8, 452 TPS65917_RESERVED8,
444 TPS65917_RESERVED9, 453 TPS65917_RESERVED9,
445 TPS65917_VBUS_IRQ, 454 TPS65917_VBUS_IRQ,
446 /* INT4 registers */ 455 /* INT4 registers */
447 TPS65917_GPIO_0_IRQ, 456 TPS65917_GPIO_0_IRQ,
448 TPS65917_GPIO_1_IRQ, 457 TPS65917_GPIO_1_IRQ,
449 TPS65917_GPIO_2_IRQ, 458 TPS65917_GPIO_2_IRQ,
450 TPS65917_GPIO_3_IRQ, 459 TPS65917_GPIO_3_IRQ,
451 TPS65917_GPIO_4_IRQ, 460 TPS65917_GPIO_4_IRQ,
452 TPS65917_GPIO_5_IRQ, 461 TPS65917_GPIO_5_IRQ,
453 TPS65917_GPIO_6_IRQ, 462 TPS65917_GPIO_6_IRQ,
454 TPS65917_RESERVED10, 463 TPS65917_RESERVED10,
455 /* Total Number IRQs */ 464 /* Total Number IRQs */
456 TPS65917_NUM_IRQ, 465 TPS65917_NUM_IRQ,
457 }; 466 };
458 467
459 /* Define the palmas IRQ numbers */ 468 /* Define the palmas IRQ numbers */
460 enum palmas_irqs { 469 enum palmas_irqs {
461 /* INT1 registers */ 470 /* INT1 registers */
462 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 471 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
463 PALMAS_PWRON_IRQ, 472 PALMAS_PWRON_IRQ,
464 PALMAS_LONG_PRESS_KEY_IRQ, 473 PALMAS_LONG_PRESS_KEY_IRQ,
465 PALMAS_RPWRON_IRQ, 474 PALMAS_RPWRON_IRQ,
466 PALMAS_PWRDOWN_IRQ, 475 PALMAS_PWRDOWN_IRQ,
467 PALMAS_HOTDIE_IRQ, 476 PALMAS_HOTDIE_IRQ,
468 PALMAS_VSYS_MON_IRQ, 477 PALMAS_VSYS_MON_IRQ,
469 PALMAS_VBAT_MON_IRQ, 478 PALMAS_VBAT_MON_IRQ,
470 /* INT2 registers */ 479 /* INT2 registers */
471 PALMAS_RTC_ALARM_IRQ, 480 PALMAS_RTC_ALARM_IRQ,
472 PALMAS_RTC_TIMER_IRQ, 481 PALMAS_RTC_TIMER_IRQ,
473 PALMAS_WDT_IRQ, 482 PALMAS_WDT_IRQ,
474 PALMAS_BATREMOVAL_IRQ, 483 PALMAS_BATREMOVAL_IRQ,
475 PALMAS_RESET_IN_IRQ, 484 PALMAS_RESET_IN_IRQ,
476 PALMAS_FBI_BB_IRQ, 485 PALMAS_FBI_BB_IRQ,
477 PALMAS_SHORT_IRQ, 486 PALMAS_SHORT_IRQ,
478 PALMAS_VAC_ACOK_IRQ, 487 PALMAS_VAC_ACOK_IRQ,
479 /* INT3 registers */ 488 /* INT3 registers */
480 PALMAS_GPADC_AUTO_0_IRQ, 489 PALMAS_GPADC_AUTO_0_IRQ,
481 PALMAS_GPADC_AUTO_1_IRQ, 490 PALMAS_GPADC_AUTO_1_IRQ,
482 PALMAS_GPADC_EOC_SW_IRQ, 491 PALMAS_GPADC_EOC_SW_IRQ,
483 PALMAS_GPADC_EOC_RT_IRQ, 492 PALMAS_GPADC_EOC_RT_IRQ,
484 PALMAS_ID_OTG_IRQ, 493 PALMAS_ID_OTG_IRQ,
485 PALMAS_ID_IRQ, 494 PALMAS_ID_IRQ,
486 PALMAS_VBUS_OTG_IRQ, 495 PALMAS_VBUS_OTG_IRQ,
487 PALMAS_VBUS_IRQ, 496 PALMAS_VBUS_IRQ,
488 /* INT4 registers */ 497 /* INT4 registers */
489 PALMAS_GPIO_0_IRQ, 498 PALMAS_GPIO_0_IRQ,
490 PALMAS_GPIO_1_IRQ, 499 PALMAS_GPIO_1_IRQ,
491 PALMAS_GPIO_2_IRQ, 500 PALMAS_GPIO_2_IRQ,
492 PALMAS_GPIO_3_IRQ, 501 PALMAS_GPIO_3_IRQ,
493 PALMAS_GPIO_4_IRQ, 502 PALMAS_GPIO_4_IRQ,
494 PALMAS_GPIO_5_IRQ, 503 PALMAS_GPIO_5_IRQ,
495 PALMAS_GPIO_6_IRQ, 504 PALMAS_GPIO_6_IRQ,
496 PALMAS_GPIO_7_IRQ, 505 PALMAS_GPIO_7_IRQ,
497 /* Total Number IRQs */ 506 /* Total Number IRQs */
498 PALMAS_NUM_IRQ, 507 PALMAS_NUM_IRQ,
499 }; 508 };
500 509
501 /* Palmas GPADC Channels */ 510 /* Palmas GPADC Channels */
502 enum { 511 enum {
503 PALMAS_ADC_CH_IN0, 512 PALMAS_ADC_CH_IN0,
504 PALMAS_ADC_CH_IN1, 513 PALMAS_ADC_CH_IN1,
505 PALMAS_ADC_CH_IN2, 514 PALMAS_ADC_CH_IN2,
506 PALMAS_ADC_CH_IN3, 515 PALMAS_ADC_CH_IN3,
507 PALMAS_ADC_CH_IN4, 516 PALMAS_ADC_CH_IN4,
508 PALMAS_ADC_CH_IN5, 517 PALMAS_ADC_CH_IN5,
509 PALMAS_ADC_CH_IN6, 518 PALMAS_ADC_CH_IN6,
510 PALMAS_ADC_CH_IN7, 519 PALMAS_ADC_CH_IN7,
511 PALMAS_ADC_CH_IN8, 520 PALMAS_ADC_CH_IN8,
512 PALMAS_ADC_CH_IN9, 521 PALMAS_ADC_CH_IN9,
513 PALMAS_ADC_CH_IN10, 522 PALMAS_ADC_CH_IN10,
514 PALMAS_ADC_CH_IN11, 523 PALMAS_ADC_CH_IN11,
515 PALMAS_ADC_CH_IN12, 524 PALMAS_ADC_CH_IN12,
516 PALMAS_ADC_CH_IN13, 525 PALMAS_ADC_CH_IN13,
517 PALMAS_ADC_CH_IN14, 526 PALMAS_ADC_CH_IN14,
518 PALMAS_ADC_CH_IN15, 527 PALMAS_ADC_CH_IN15,
519 PALMAS_ADC_CH_MAX, 528 PALMAS_ADC_CH_MAX,
520 }; 529 };
521 530
522 /* Palmas GPADC Channel0 Current Source */ 531 /* Palmas GPADC Channel0 Current Source */
523 enum { 532 enum {
524 PALMAS_ADC_CH0_CURRENT_SRC_0, 533 PALMAS_ADC_CH0_CURRENT_SRC_0,
525 PALMAS_ADC_CH0_CURRENT_SRC_5, 534 PALMAS_ADC_CH0_CURRENT_SRC_5,
526 PALMAS_ADC_CH0_CURRENT_SRC_15, 535 PALMAS_ADC_CH0_CURRENT_SRC_15,
527 PALMAS_ADC_CH0_CURRENT_SRC_20, 536 PALMAS_ADC_CH0_CURRENT_SRC_20,
528 }; 537 };
529 538
530 /* Palmas GPADC Channel3 Current Source */ 539 /* Palmas GPADC Channel3 Current Source */
531 enum { 540 enum {
532 PALMAS_ADC_CH3_CURRENT_SRC_0, 541 PALMAS_ADC_CH3_CURRENT_SRC_0,
533 PALMAS_ADC_CH3_CURRENT_SRC_10, 542 PALMAS_ADC_CH3_CURRENT_SRC_10,
534 PALMAS_ADC_CH3_CURRENT_SRC_400, 543 PALMAS_ADC_CH3_CURRENT_SRC_400,
535 PALMAS_ADC_CH3_CURRENT_SRC_800, 544 PALMAS_ADC_CH3_CURRENT_SRC_800,
536 }; 545 };
537 546
538 struct palmas_pmic { 547 struct palmas_pmic {
539 struct palmas *palmas; 548 struct palmas *palmas;
540 struct device *dev; 549 struct device *dev;
541 struct regulator_desc desc[PALMAS_NUM_ 550 struct regulator_desc desc[PALMAS_NUM_REGS];
542 struct mutex mutex; 551 struct mutex mutex;
543 552
544 int smps123; 553 int smps123;
545 int smps457; 554 int smps457;
546 int smps12; 555 int smps12;
547 556
548 int range[PALMAS_REG_SMPS10_OUT1]; 557 int range[PALMAS_REG_SMPS10_OUT1];
549 unsigned int ramp_delay[PALMAS_REG_SMP 558 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
550 unsigned int current_reg_mode[PALMAS_R 559 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
551 }; 560 };
552 561
553 struct palmas_resource { 562 struct palmas_resource {
554 struct palmas *palmas; 563 struct palmas *palmas;
555 struct device *dev; 564 struct device *dev;
556 }; 565 };
557 566
558 struct palmas_usb { 567 struct palmas_usb {
559 struct palmas *palmas; 568 struct palmas *palmas;
560 struct device *dev; 569 struct device *dev;
561 570
562 struct extcon_dev *edev; 571 struct extcon_dev *edev;
563 572
564 int id_otg_irq; 573 int id_otg_irq;
565 int id_irq; 574 int id_irq;
566 int vbus_otg_irq; 575 int vbus_otg_irq;
567 int vbus_irq; 576 int vbus_irq;
568 577
569 int gpio_id_irq; 578 int gpio_id_irq;
570 int gpio_vbus_irq; 579 int gpio_vbus_irq;
571 struct gpio_desc *id_gpiod; 580 struct gpio_desc *id_gpiod;
572 struct gpio_desc *vbus_gpiod; 581 struct gpio_desc *vbus_gpiod;
573 unsigned long sw_debounce_jiffies; 582 unsigned long sw_debounce_jiffies;
574 struct delayed_work wq_detectid; 583 struct delayed_work wq_detectid;
575 584
576 enum palmas_usb_state linkstat; 585 enum palmas_usb_state linkstat;
577 int wakeup; 586 int wakeup;
578 bool enable_vbus_detection; 587 bool enable_vbus_detection;
579 bool enable_id_detection; 588 bool enable_id_detection;
580 bool enable_gpio_id_detection; 589 bool enable_gpio_id_detection;
581 bool enable_gpio_vbus_detection; 590 bool enable_gpio_vbus_detection;
582 }; 591 };
583 592
584 #define comparator_to_palmas(x) container_of(( 593 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
585 594
586 enum usb_irq_events { 595 enum usb_irq_events {
587 /* Wakeup events from INT3 */ 596 /* Wakeup events from INT3 */
588 PALMAS_USB_ID_WAKEPUP, 597 PALMAS_USB_ID_WAKEPUP,
589 PALMAS_USB_VBUS_WAKEUP, 598 PALMAS_USB_VBUS_WAKEUP,
590 599
591 /* ID_OTG_EVENTS */ 600 /* ID_OTG_EVENTS */
592 PALMAS_USB_ID_GND, 601 PALMAS_USB_ID_GND,
593 N_PALMAS_USB_ID_GND, 602 N_PALMAS_USB_ID_GND,
594 PALMAS_USB_ID_C, 603 PALMAS_USB_ID_C,
595 N_PALMAS_USB_ID_C, 604 N_PALMAS_USB_ID_C,
596 PALMAS_USB_ID_B, 605 PALMAS_USB_ID_B,
597 N_PALMAS_USB_ID_B, 606 N_PALMAS_USB_ID_B,
598 PALMAS_USB_ID_A, 607 PALMAS_USB_ID_A,
599 N_PALMAS_USB_ID_A, 608 N_PALMAS_USB_ID_A,
600 PALMAS_USB_ID_FLOAT, 609 PALMAS_USB_ID_FLOAT,
601 N_PALMAS_USB_ID_FLOAT, 610 N_PALMAS_USB_ID_FLOAT,
602 611
603 /* VBUS_OTG_EVENTS */ 612 /* VBUS_OTG_EVENTS */
604 PALMAS_USB_VB_SESS_END, 613 PALMAS_USB_VB_SESS_END,
605 N_PALMAS_USB_VB_SESS_END, 614 N_PALMAS_USB_VB_SESS_END,
606 PALMAS_USB_VB_SESS_VLD, 615 PALMAS_USB_VB_SESS_VLD,
607 N_PALMAS_USB_VB_SESS_VLD, 616 N_PALMAS_USB_VB_SESS_VLD,
608 PALMAS_USB_VA_SESS_VLD, 617 PALMAS_USB_VA_SESS_VLD,
609 N_PALMAS_USB_VA_SESS_VLD, 618 N_PALMAS_USB_VA_SESS_VLD,
610 PALMAS_USB_VA_VBUS_VLD, 619 PALMAS_USB_VA_VBUS_VLD,
611 N_PALMAS_USB_VA_VBUS_VLD, 620 N_PALMAS_USB_VA_VBUS_VLD,
612 PALMAS_USB_VADP_SNS, 621 PALMAS_USB_VADP_SNS,
613 N_PALMAS_USB_VADP_SNS, 622 N_PALMAS_USB_VADP_SNS,
614 PALMAS_USB_VADP_PRB, 623 PALMAS_USB_VADP_PRB,
615 N_PALMAS_USB_VADP_PRB, 624 N_PALMAS_USB_VADP_PRB,
616 PALMAS_USB_VOTG_SESS_VLD, 625 PALMAS_USB_VOTG_SESS_VLD,
617 N_PALMAS_USB_VOTG_SESS_VLD, 626 N_PALMAS_USB_VOTG_SESS_VLD,
618 }; 627 };
619 628
620 /* defines so we can store the mux settings */ 629 /* defines so we can store the mux settings */
621 #define PALMAS_GPIO_0_MUXED 630 #define PALMAS_GPIO_0_MUXED (1 << 0)
622 #define PALMAS_GPIO_1_MUXED 631 #define PALMAS_GPIO_1_MUXED (1 << 1)
623 #define PALMAS_GPIO_2_MUXED 632 #define PALMAS_GPIO_2_MUXED (1 << 2)
624 #define PALMAS_GPIO_3_MUXED 633 #define PALMAS_GPIO_3_MUXED (1 << 3)
625 #define PALMAS_GPIO_4_MUXED 634 #define PALMAS_GPIO_4_MUXED (1 << 4)
626 #define PALMAS_GPIO_5_MUXED 635 #define PALMAS_GPIO_5_MUXED (1 << 5)
627 #define PALMAS_GPIO_6_MUXED 636 #define PALMAS_GPIO_6_MUXED (1 << 6)
628 #define PALMAS_GPIO_7_MUXED 637 #define PALMAS_GPIO_7_MUXED (1 << 7)
629 638
630 #define PALMAS_LED1_MUXED 639 #define PALMAS_LED1_MUXED (1 << 0)
631 #define PALMAS_LED2_MUXED 640 #define PALMAS_LED2_MUXED (1 << 1)
632 641
633 #define PALMAS_PWM1_MUXED 642 #define PALMAS_PWM1_MUXED (1 << 0)
634 #define PALMAS_PWM2_MUXED 643 #define PALMAS_PWM2_MUXED (1 << 1)
635 644
636 /* helper macro to get correct slave number */ 645 /* helper macro to get correct slave number */
637 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 646 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
638 #define PALMAS_BASE_TO_REG(x, y) ((x & 647 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
639 648
640 /* Base addresses of IP blocks in Palmas */ 649 /* Base addresses of IP blocks in Palmas */
641 #define PALMAS_SMPS_DVS_BASE 650 #define PALMAS_SMPS_DVS_BASE 0x020
642 #define PALMAS_RTC_BASE 651 #define PALMAS_RTC_BASE 0x100
643 #define PALMAS_VALIDITY_BASE 652 #define PALMAS_VALIDITY_BASE 0x118
644 #define PALMAS_SMPS_BASE 653 #define PALMAS_SMPS_BASE 0x120
645 #define PALMAS_LDO_BASE 654 #define PALMAS_LDO_BASE 0x150
646 #define PALMAS_DVFS_BASE 655 #define PALMAS_DVFS_BASE 0x180
647 #define PALMAS_PMU_CONTROL_BASE 656 #define PALMAS_PMU_CONTROL_BASE 0x1A0
648 #define PALMAS_RESOURCE_BASE 657 #define PALMAS_RESOURCE_BASE 0x1D4
649 #define PALMAS_PU_PD_OD_BASE 658 #define PALMAS_PU_PD_OD_BASE 0x1F0
650 #define PALMAS_LED_BASE 659 #define PALMAS_LED_BASE 0x200
651 #define PALMAS_INTERRUPT_BASE 660 #define PALMAS_INTERRUPT_BASE 0x210
652 #define PALMAS_USB_OTG_BASE 661 #define PALMAS_USB_OTG_BASE 0x250
653 #define PALMAS_VIBRATOR_BASE 662 #define PALMAS_VIBRATOR_BASE 0x270
654 #define PALMAS_GPIO_BASE 663 #define PALMAS_GPIO_BASE 0x280
655 #define PALMAS_USB_BASE 664 #define PALMAS_USB_BASE 0x290
656 #define PALMAS_GPADC_BASE 665 #define PALMAS_GPADC_BASE 0x2C0
657 #define PALMAS_TRIM_GPADC_BASE 666 #define PALMAS_TRIM_GPADC_BASE 0x3CD
658 667
659 /* Registers for function RTC */ 668 /* Registers for function RTC */
660 #define PALMAS_SECONDS_REG 669 #define PALMAS_SECONDS_REG 0x00
661 #define PALMAS_MINUTES_REG 670 #define PALMAS_MINUTES_REG 0x01
662 #define PALMAS_HOURS_REG 671 #define PALMAS_HOURS_REG 0x02
663 #define PALMAS_DAYS_REG 672 #define PALMAS_DAYS_REG 0x03
664 #define PALMAS_MONTHS_REG 673 #define PALMAS_MONTHS_REG 0x04
665 #define PALMAS_YEARS_REG 674 #define PALMAS_YEARS_REG 0x05
666 #define PALMAS_WEEKS_REG 675 #define PALMAS_WEEKS_REG 0x06
667 #define PALMAS_ALARM_SECONDS_REG 676 #define PALMAS_ALARM_SECONDS_REG 0x08
668 #define PALMAS_ALARM_MINUTES_REG 677 #define PALMAS_ALARM_MINUTES_REG 0x09
669 #define PALMAS_ALARM_HOURS_REG 678 #define PALMAS_ALARM_HOURS_REG 0x0A
670 #define PALMAS_ALARM_DAYS_REG 679 #define PALMAS_ALARM_DAYS_REG 0x0B
671 #define PALMAS_ALARM_MONTHS_REG 680 #define PALMAS_ALARM_MONTHS_REG 0x0C
672 #define PALMAS_ALARM_YEARS_REG 681 #define PALMAS_ALARM_YEARS_REG 0x0D
673 #define PALMAS_RTC_CTRL_REG 682 #define PALMAS_RTC_CTRL_REG 0x10
674 #define PALMAS_RTC_STATUS_REG 683 #define PALMAS_RTC_STATUS_REG 0x11
675 #define PALMAS_RTC_INTERRUPTS_REG 684 #define PALMAS_RTC_INTERRUPTS_REG 0x12
676 #define PALMAS_RTC_COMP_LSB_REG 685 #define PALMAS_RTC_COMP_LSB_REG 0x13
677 #define PALMAS_RTC_COMP_MSB_REG 686 #define PALMAS_RTC_COMP_MSB_REG 0x14
678 #define PALMAS_RTC_RES_PROG_REG 687 #define PALMAS_RTC_RES_PROG_REG 0x15
679 #define PALMAS_RTC_RESET_STATUS_REG 688 #define PALMAS_RTC_RESET_STATUS_REG 0x16
680 689
681 /* Bit definitions for SECONDS_REG */ 690 /* Bit definitions for SECONDS_REG */
682 #define PALMAS_SECONDS_REG_SEC1_MASK 691 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
683 #define PALMAS_SECONDS_REG_SEC1_SHIFT 692 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
684 #define PALMAS_SECONDS_REG_SEC0_MASK 693 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
685 #define PALMAS_SECONDS_REG_SEC0_SHIFT 694 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
686 695
687 /* Bit definitions for MINUTES_REG */ 696 /* Bit definitions for MINUTES_REG */
688 #define PALMAS_MINUTES_REG_MIN1_MASK 697 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
689 #define PALMAS_MINUTES_REG_MIN1_SHIFT 698 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
690 #define PALMAS_MINUTES_REG_MIN0_MASK 699 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
691 #define PALMAS_MINUTES_REG_MIN0_SHIFT 700 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
692 701
693 /* Bit definitions for HOURS_REG */ 702 /* Bit definitions for HOURS_REG */
694 #define PALMAS_HOURS_REG_PM_NAM 703 #define PALMAS_HOURS_REG_PM_NAM 0x80
695 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 704 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
696 #define PALMAS_HOURS_REG_HOUR1_MASK 705 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
697 #define PALMAS_HOURS_REG_HOUR1_SHIFT 706 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
698 #define PALMAS_HOURS_REG_HOUR0_MASK 707 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
699 #define PALMAS_HOURS_REG_HOUR0_SHIFT 708 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
700 709
701 /* Bit definitions for DAYS_REG */ 710 /* Bit definitions for DAYS_REG */
702 #define PALMAS_DAYS_REG_DAY1_MASK 711 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
703 #define PALMAS_DAYS_REG_DAY1_SHIFT 712 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
704 #define PALMAS_DAYS_REG_DAY0_MASK 713 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F
705 #define PALMAS_DAYS_REG_DAY0_SHIFT 714 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
706 715
707 /* Bit definitions for MONTHS_REG */ 716 /* Bit definitions for MONTHS_REG */
708 #define PALMAS_MONTHS_REG_MONTH1 717 #define PALMAS_MONTHS_REG_MONTH1 0x10
709 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 718 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
710 #define PALMAS_MONTHS_REG_MONTH0_MASK 719 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
711 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 720 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
712 721
713 /* Bit definitions for YEARS_REG */ 722 /* Bit definitions for YEARS_REG */
714 #define PALMAS_YEARS_REG_YEAR1_MASK 723 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
715 #define PALMAS_YEARS_REG_YEAR1_SHIFT 724 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
716 #define PALMAS_YEARS_REG_YEAR0_MASK 725 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
717 #define PALMAS_YEARS_REG_YEAR0_SHIFT 726 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
718 727
719 /* Bit definitions for WEEKS_REG */ 728 /* Bit definitions for WEEKS_REG */
720 #define PALMAS_WEEKS_REG_WEEK_MASK 729 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
721 #define PALMAS_WEEKS_REG_WEEK_SHIFT 730 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
722 731
723 /* Bit definitions for ALARM_SECONDS_REG */ 732 /* Bit definitions for ALARM_SECONDS_REG */
724 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MA 733 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
725 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SH 734 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
726 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MA 735 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
727 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SH 736 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
728 737
729 /* Bit definitions for ALARM_MINUTES_REG */ 738 /* Bit definitions for ALARM_MINUTES_REG */
730 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MA 739 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
731 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SH 740 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
732 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MA 741 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
733 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SH 742 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
734 743
735 /* Bit definitions for ALARM_HOURS_REG */ 744 /* Bit definitions for ALARM_HOURS_REG */
736 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 745 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
737 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SH 746 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
738 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MAS 747 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
739 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHI 748 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
740 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MAS 749 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
741 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHI 750 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
742 751
743 /* Bit definitions for ALARM_DAYS_REG */ 752 /* Bit definitions for ALARM_DAYS_REG */
744 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 753 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
745 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 754 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
746 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 755 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
747 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 756 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
748 757
749 /* Bit definitions for ALARM_MONTHS_REG */ 758 /* Bit definitions for ALARM_MONTHS_REG */
750 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 759 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
751 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_S 760 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
752 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_M 761 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
753 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_S 762 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
754 763
755 /* Bit definitions for ALARM_YEARS_REG */ 764 /* Bit definitions for ALARM_YEARS_REG */
756 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MAS 765 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
757 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHI 766 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
758 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MAS 767 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
759 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHI 768 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
760 769
761 /* Bit definitions for RTC_CTRL_REG */ 770 /* Bit definitions for RTC_CTRL_REG */
762 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 771 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
763 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 772 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
764 #define PALMAS_RTC_CTRL_REG_GET_TIME 773 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
765 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 774 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
766 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 775 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
767 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHI 776 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
768 #define PALMAS_RTC_CTRL_REG_TEST_MODE 777 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
769 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 778 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
770 #define PALMAS_RTC_CTRL_REG_MODE_12_24 779 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
771 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 780 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
772 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 781 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
773 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 782 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
774 #define PALMAS_RTC_CTRL_REG_ROUND_30S 783 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
775 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 784 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
776 #define PALMAS_RTC_CTRL_REG_STOP_RTC 785 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
777 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 786 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
778 787
779 /* Bit definitions for RTC_STATUS_REG */ 788 /* Bit definitions for RTC_STATUS_REG */
780 #define PALMAS_RTC_STATUS_REG_POWER_UP 789 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
781 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 790 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
782 #define PALMAS_RTC_STATUS_REG_ALARM 791 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
783 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 792 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
784 #define PALMAS_RTC_STATUS_REG_EVENT_1D 793 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
785 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 794 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
786 #define PALMAS_RTC_STATUS_REG_EVENT_1H 795 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
787 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 796 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
788 #define PALMAS_RTC_STATUS_REG_EVENT_1M 797 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
789 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 798 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
790 #define PALMAS_RTC_STATUS_REG_EVENT_1S 799 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
791 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 800 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
792 #define PALMAS_RTC_STATUS_REG_RUN 801 #define PALMAS_RTC_STATUS_REG_RUN 0x02
793 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 802 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
794 803
795 /* Bit definitions for RTC_INTERRUPTS_REG */ 804 /* Bit definitions for RTC_INTERRUPTS_REG */
796 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MAS 805 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
797 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MAS 806 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
798 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 807 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
799 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHI 808 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
800 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 809 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
801 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHI 810 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
802 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 811 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
803 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 812 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
804 813
805 /* Bit definitions for RTC_COMP_LSB_REG */ 814 /* Bit definitions for RTC_COMP_LSB_REG */
806 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_M 815 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
807 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_S 816 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
808 817
809 /* Bit definitions for RTC_COMP_MSB_REG */ 818 /* Bit definitions for RTC_COMP_MSB_REG */
810 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_M 819 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
811 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_S 820 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
812 821
813 /* Bit definitions for RTC_RES_PROG_REG */ 822 /* Bit definitions for RTC_RES_PROG_REG */
814 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MA 823 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
815 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SH 824 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
816 825
817 /* Bit definitions for RTC_RESET_STATUS_REG */ 826 /* Bit definitions for RTC_RESET_STATUS_REG */
818 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STAT 827 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
819 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STAT 828 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
820 829
821 /* Registers for function BACKUP */ 830 /* Registers for function BACKUP */
822 #define PALMAS_BACKUP0 831 #define PALMAS_BACKUP0 0x00
823 #define PALMAS_BACKUP1 832 #define PALMAS_BACKUP1 0x01
824 #define PALMAS_BACKUP2 833 #define PALMAS_BACKUP2 0x02
825 #define PALMAS_BACKUP3 834 #define PALMAS_BACKUP3 0x03
826 #define PALMAS_BACKUP4 835 #define PALMAS_BACKUP4 0x04
827 #define PALMAS_BACKUP5 836 #define PALMAS_BACKUP5 0x05
828 #define PALMAS_BACKUP6 837 #define PALMAS_BACKUP6 0x06
829 #define PALMAS_BACKUP7 838 #define PALMAS_BACKUP7 0x07
830 839
831 /* Bit definitions for BACKUP0 */ 840 /* Bit definitions for BACKUP0 */
832 #define PALMAS_BACKUP0_BACKUP_MASK 841 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF
833 #define PALMAS_BACKUP0_BACKUP_SHIFT 842 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
834 843
835 /* Bit definitions for BACKUP1 */ 844 /* Bit definitions for BACKUP1 */
836 #define PALMAS_BACKUP1_BACKUP_MASK 845 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF
837 #define PALMAS_BACKUP1_BACKUP_SHIFT 846 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
838 847
839 /* Bit definitions for BACKUP2 */ 848 /* Bit definitions for BACKUP2 */
840 #define PALMAS_BACKUP2_BACKUP_MASK 849 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF
841 #define PALMAS_BACKUP2_BACKUP_SHIFT 850 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
842 851
843 /* Bit definitions for BACKUP3 */ 852 /* Bit definitions for BACKUP3 */
844 #define PALMAS_BACKUP3_BACKUP_MASK 853 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF
845 #define PALMAS_BACKUP3_BACKUP_SHIFT 854 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
846 855
847 /* Bit definitions for BACKUP4 */ 856 /* Bit definitions for BACKUP4 */
848 #define PALMAS_BACKUP4_BACKUP_MASK 857 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF
849 #define PALMAS_BACKUP4_BACKUP_SHIFT 858 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
850 859
851 /* Bit definitions for BACKUP5 */ 860 /* Bit definitions for BACKUP5 */
852 #define PALMAS_BACKUP5_BACKUP_MASK 861 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF
853 #define PALMAS_BACKUP5_BACKUP_SHIFT 862 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
854 863
855 /* Bit definitions for BACKUP6 */ 864 /* Bit definitions for BACKUP6 */
856 #define PALMAS_BACKUP6_BACKUP_MASK 865 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF
857 #define PALMAS_BACKUP6_BACKUP_SHIFT 866 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
858 867
859 /* Bit definitions for BACKUP7 */ 868 /* Bit definitions for BACKUP7 */
860 #define PALMAS_BACKUP7_BACKUP_MASK 869 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF
861 #define PALMAS_BACKUP7_BACKUP_SHIFT 870 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
862 871
863 /* Registers for function SMPS */ 872 /* Registers for function SMPS */
864 #define PALMAS_SMPS12_CTRL 873 #define PALMAS_SMPS12_CTRL 0x00
865 #define PALMAS_SMPS12_TSTEP 874 #define PALMAS_SMPS12_TSTEP 0x01
866 #define PALMAS_SMPS12_FORCE 875 #define PALMAS_SMPS12_FORCE 0x02
867 #define PALMAS_SMPS12_VOLTAGE 876 #define PALMAS_SMPS12_VOLTAGE 0x03
868 #define PALMAS_SMPS3_CTRL 877 #define PALMAS_SMPS3_CTRL 0x04
869 #define PALMAS_SMPS3_VOLTAGE 878 #define PALMAS_SMPS3_VOLTAGE 0x07
870 #define PALMAS_SMPS45_CTRL 879 #define PALMAS_SMPS45_CTRL 0x08
871 #define PALMAS_SMPS45_TSTEP 880 #define PALMAS_SMPS45_TSTEP 0x09
872 #define PALMAS_SMPS45_FORCE 881 #define PALMAS_SMPS45_FORCE 0x0A
873 #define PALMAS_SMPS45_VOLTAGE 882 #define PALMAS_SMPS45_VOLTAGE 0x0B
874 #define PALMAS_SMPS6_CTRL 883 #define PALMAS_SMPS6_CTRL 0x0C
875 #define PALMAS_SMPS6_TSTEP 884 #define PALMAS_SMPS6_TSTEP 0x0D
876 #define PALMAS_SMPS6_FORCE 885 #define PALMAS_SMPS6_FORCE 0x0E
877 #define PALMAS_SMPS6_VOLTAGE 886 #define PALMAS_SMPS6_VOLTAGE 0x0F
878 #define PALMAS_SMPS7_CTRL 887 #define PALMAS_SMPS7_CTRL 0x10
879 #define PALMAS_SMPS7_VOLTAGE 888 #define PALMAS_SMPS7_VOLTAGE 0x13
880 #define PALMAS_SMPS8_CTRL 889 #define PALMAS_SMPS8_CTRL 0x14
881 #define PALMAS_SMPS8_TSTEP 890 #define PALMAS_SMPS8_TSTEP 0x15
882 #define PALMAS_SMPS8_FORCE 891 #define PALMAS_SMPS8_FORCE 0x16
883 #define PALMAS_SMPS8_VOLTAGE 892 #define PALMAS_SMPS8_VOLTAGE 0x17
884 #define PALMAS_SMPS9_CTRL 893 #define PALMAS_SMPS9_CTRL 0x18
885 #define PALMAS_SMPS9_VOLTAGE 894 #define PALMAS_SMPS9_VOLTAGE 0x1B
886 #define PALMAS_SMPS10_CTRL 895 #define PALMAS_SMPS10_CTRL 0x1C
887 #define PALMAS_SMPS10_STATUS 896 #define PALMAS_SMPS10_STATUS 0x1F
888 #define PALMAS_SMPS_CTRL 897 #define PALMAS_SMPS_CTRL 0x24
889 #define PALMAS_SMPS_PD_CTRL 898 #define PALMAS_SMPS_PD_CTRL 0x25
890 #define PALMAS_SMPS_DITHER_EN 899 #define PALMAS_SMPS_DITHER_EN 0x26
891 #define PALMAS_SMPS_THERMAL_EN 900 #define PALMAS_SMPS_THERMAL_EN 0x27
892 #define PALMAS_SMPS_THERMAL_STATUS 901 #define PALMAS_SMPS_THERMAL_STATUS 0x28
893 #define PALMAS_SMPS_SHORT_STATUS 902 #define PALMAS_SMPS_SHORT_STATUS 0x29
894 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 903 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
895 #define PALMAS_SMPS_POWERGOOD_MASK1 904 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
896 #define PALMAS_SMPS_POWERGOOD_MASK2 905 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
897 906
898 /* Bit definitions for SMPS12_CTRL */ 907 /* Bit definitions for SMPS12_CTRL */
899 #define PALMAS_SMPS12_CTRL_WR_S 908 #define PALMAS_SMPS12_CTRL_WR_S 0x80
900 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 909 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
901 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 910 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
902 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 911 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
903 #define PALMAS_SMPS12_CTRL_STATUS_MASK 912 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
904 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 913 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
905 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 914 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
906 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 915 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
907 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 916 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
908 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 917 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
909 918
910 /* Bit definitions for SMPS12_TSTEP */ 919 /* Bit definitions for SMPS12_TSTEP */
911 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 920 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
912 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 921 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
913 922
914 /* Bit definitions for SMPS12_FORCE */ 923 /* Bit definitions for SMPS12_FORCE */
915 #define PALMAS_SMPS12_FORCE_CMD 924 #define PALMAS_SMPS12_FORCE_CMD 0x80
916 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 925 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
917 #define PALMAS_SMPS12_FORCE_VSEL_MASK 926 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
918 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 927 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
919 928
920 /* Bit definitions for SMPS12_VOLTAGE */ 929 /* Bit definitions for SMPS12_VOLTAGE */
921 #define PALMAS_SMPS12_VOLTAGE_RANGE 930 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
922 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 931 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
923 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 932 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
924 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 933 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
925 934
926 /* Bit definitions for SMPS3_CTRL */ 935 /* Bit definitions for SMPS3_CTRL */
927 #define PALMAS_SMPS3_CTRL_WR_S 936 #define PALMAS_SMPS3_CTRL_WR_S 0x80
928 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 937 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
929 #define PALMAS_SMPS3_CTRL_STATUS_MASK 938 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
930 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 939 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
931 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 940 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
932 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 941 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
933 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 942 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
934 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 943 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
935 944
936 /* Bit definitions for SMPS3_VOLTAGE */ 945 /* Bit definitions for SMPS3_VOLTAGE */
937 #define PALMAS_SMPS3_VOLTAGE_RANGE 946 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
938 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 947 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
939 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 948 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
940 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 949 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
941 950
942 /* Bit definitions for SMPS45_CTRL */ 951 /* Bit definitions for SMPS45_CTRL */
943 #define PALMAS_SMPS45_CTRL_WR_S 952 #define PALMAS_SMPS45_CTRL_WR_S 0x80
944 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 953 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
945 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 954 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
946 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 955 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
947 #define PALMAS_SMPS45_CTRL_STATUS_MASK 956 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
948 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 957 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
949 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 958 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
950 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 959 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
951 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 960 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
952 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 961 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
953 962
954 /* Bit definitions for SMPS45_TSTEP */ 963 /* Bit definitions for SMPS45_TSTEP */
955 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 964 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
956 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 965 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
957 966
958 /* Bit definitions for SMPS45_FORCE */ 967 /* Bit definitions for SMPS45_FORCE */
959 #define PALMAS_SMPS45_FORCE_CMD 968 #define PALMAS_SMPS45_FORCE_CMD 0x80
960 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 969 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
961 #define PALMAS_SMPS45_FORCE_VSEL_MASK 970 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
962 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 971 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
963 972
964 /* Bit definitions for SMPS45_VOLTAGE */ 973 /* Bit definitions for SMPS45_VOLTAGE */
965 #define PALMAS_SMPS45_VOLTAGE_RANGE 974 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
966 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 975 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
967 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 976 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
968 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 977 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
969 978
970 /* Bit definitions for SMPS6_CTRL */ 979 /* Bit definitions for SMPS6_CTRL */
971 #define PALMAS_SMPS6_CTRL_WR_S 980 #define PALMAS_SMPS6_CTRL_WR_S 0x80
972 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 981 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
973 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 982 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
974 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 983 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
975 #define PALMAS_SMPS6_CTRL_STATUS_MASK 984 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
976 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 985 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
977 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 986 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
978 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 987 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
979 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 988 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
980 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 989 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
981 990
982 /* Bit definitions for SMPS6_TSTEP */ 991 /* Bit definitions for SMPS6_TSTEP */
983 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 992 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
984 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 993 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
985 994
986 /* Bit definitions for SMPS6_FORCE */ 995 /* Bit definitions for SMPS6_FORCE */
987 #define PALMAS_SMPS6_FORCE_CMD 996 #define PALMAS_SMPS6_FORCE_CMD 0x80
988 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 997 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
989 #define PALMAS_SMPS6_FORCE_VSEL_MASK 998 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
990 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 999 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
991 1000
992 /* Bit definitions for SMPS6_VOLTAGE */ 1001 /* Bit definitions for SMPS6_VOLTAGE */
993 #define PALMAS_SMPS6_VOLTAGE_RANGE 1002 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
994 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 1003 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
995 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 1004 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
996 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 1005 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
997 1006
998 /* Bit definitions for SMPS7_CTRL */ 1007 /* Bit definitions for SMPS7_CTRL */
999 #define PALMAS_SMPS7_CTRL_WR_S 1008 #define PALMAS_SMPS7_CTRL_WR_S 0x80
1000 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 1009 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
1001 #define PALMAS_SMPS7_CTRL_STATUS_MASK 1010 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
1002 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 1011 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
1003 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 1012 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
1004 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 1013 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
1005 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 1014 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
1006 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 1015 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
1007 1016
1008 /* Bit definitions for SMPS7_VOLTAGE */ 1017 /* Bit definitions for SMPS7_VOLTAGE */
1009 #define PALMAS_SMPS7_VOLTAGE_RANGE 1018 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
1010 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 1019 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
1011 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 1020 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
1012 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 1021 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
1013 1022
1014 /* Bit definitions for SMPS8_CTRL */ 1023 /* Bit definitions for SMPS8_CTRL */
1015 #define PALMAS_SMPS8_CTRL_WR_S 1024 #define PALMAS_SMPS8_CTRL_WR_S 0x80
1016 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 1025 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
1017 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 1026 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
1018 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 1027 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
1019 #define PALMAS_SMPS8_CTRL_STATUS_MASK 1028 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
1020 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 1029 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
1021 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 1030 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
1022 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 1031 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
1023 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 1032 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
1024 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 1033 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
1025 1034
1026 /* Bit definitions for SMPS8_TSTEP */ 1035 /* Bit definitions for SMPS8_TSTEP */
1027 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 1036 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
1028 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 1037 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
1029 1038
1030 /* Bit definitions for SMPS8_FORCE */ 1039 /* Bit definitions for SMPS8_FORCE */
1031 #define PALMAS_SMPS8_FORCE_CMD 1040 #define PALMAS_SMPS8_FORCE_CMD 0x80
1032 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 1041 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
1033 #define PALMAS_SMPS8_FORCE_VSEL_MASK 1042 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
1034 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 1043 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
1035 1044
1036 /* Bit definitions for SMPS8_VOLTAGE */ 1045 /* Bit definitions for SMPS8_VOLTAGE */
1037 #define PALMAS_SMPS8_VOLTAGE_RANGE 1046 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
1038 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 1047 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
1039 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 1048 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
1040 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 1049 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
1041 1050
1042 /* Bit definitions for SMPS9_CTRL */ 1051 /* Bit definitions for SMPS9_CTRL */
1043 #define PALMAS_SMPS9_CTRL_WR_S 1052 #define PALMAS_SMPS9_CTRL_WR_S 0x80
1044 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 1053 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
1045 #define PALMAS_SMPS9_CTRL_STATUS_MASK 1054 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
1046 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 1055 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
1047 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 1056 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
1048 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 1057 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
1049 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 1058 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
1050 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 1059 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
1051 1060
1052 /* Bit definitions for SMPS9_VOLTAGE */ 1061 /* Bit definitions for SMPS9_VOLTAGE */
1053 #define PALMAS_SMPS9_VOLTAGE_RANGE 1062 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
1054 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 1063 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1055 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 1064 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1056 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 1065 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
1057 1066
1058 /* Bit definitions for SMPS10_CTRL */ 1067 /* Bit definitions for SMPS10_CTRL */
1059 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 1068 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
1060 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 1069 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1061 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 1070 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1062 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 1071 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
1063 1072
1064 /* Bit definitions for SMPS10_STATUS */ 1073 /* Bit definitions for SMPS10_STATUS */
1065 #define PALMAS_SMPS10_STATUS_STATUS_MASK 1074 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1066 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 1075 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
1067 1076
1068 /* Bit definitions for SMPS_CTRL */ 1077 /* Bit definitions for SMPS_CTRL */
1069 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 1078 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
1070 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SH 1079 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
1071 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 1080 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
1072 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SH 1081 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
1073 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MA 1082 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
1074 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SH 1083 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
1075 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_M 1084 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
1076 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_S 1085 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
1077 1086
1078 /* Bit definitions for SMPS_PD_CTRL */ 1087 /* Bit definitions for SMPS_PD_CTRL */
1079 #define PALMAS_SMPS_PD_CTRL_SMPS9 1088 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
1080 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 1089 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
1081 #define PALMAS_SMPS_PD_CTRL_SMPS8 1090 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
1082 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 1091 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
1083 #define PALMAS_SMPS_PD_CTRL_SMPS7 1092 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
1084 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 1093 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
1085 #define PALMAS_SMPS_PD_CTRL_SMPS6 1094 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
1086 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 1095 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
1087 #define PALMAS_SMPS_PD_CTRL_SMPS45 1096 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
1088 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 1097 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
1089 #define PALMAS_SMPS_PD_CTRL_SMPS3 1098 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
1090 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1099 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
1091 #define PALMAS_SMPS_PD_CTRL_SMPS12 1100 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
1092 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 1101 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
1093 1102
1094 /* Bit definitions for SMPS_THERMAL_EN */ 1103 /* Bit definitions for SMPS_THERMAL_EN */
1095 #define PALMAS_SMPS_THERMAL_EN_SMPS9 1104 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
1096 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 1105 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
1097 #define PALMAS_SMPS_THERMAL_EN_SMPS8 1106 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
1098 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 1107 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
1099 #define PALMAS_SMPS_THERMAL_EN_SMPS6 1108 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
1100 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 1109 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
1101 #define PALMAS_SMPS_THERMAL_EN_SMPS457 1110 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
1102 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 1111 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
1103 #define PALMAS_SMPS_THERMAL_EN_SMPS123 1112 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
1104 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 1113 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
1105 1114
1106 /* Bit definitions for SMPS_THERMAL_STATUS */ 1115 /* Bit definitions for SMPS_THERMAL_STATUS */
1107 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 1116 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
1108 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIF 1117 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
1109 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 1118 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
1110 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIF 1119 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
1111 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 1120 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
1112 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIF 1121 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
1113 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 1122 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
1114 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SH 1123 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
1115 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 1124 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
1116 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SH 1125 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
1117 1126
1118 /* Bit definitions for SMPS_SHORT_STATUS */ 1127 /* Bit definitions for SMPS_SHORT_STATUS */
1119 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 1128 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
1120 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 1129 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
1121 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 1130 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
1122 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 1131 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
1123 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 1132 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
1124 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 1133 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
1125 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
1126 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 1135 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
1127 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 1136 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
1128 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 1137 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
1129 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 1138 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
1130 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 1139 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
1131 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 1140 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
1132 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1141 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
1133 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 1142 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
1134 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 1143 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
1135 1144
1136 /* Bit definitions for SMPS_NEGATIVE_CURRENT_ 1145 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1137 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1146 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
1138 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1147 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
1139 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1148 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
1140 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1149 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
1141 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1150 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
1142 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1151 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
1143 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1152 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
1144 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1153 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
1145 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1154 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
1146 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1155 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
1147 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1156 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
1148 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1157 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
1149 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1158 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
1150 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 1159 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
1151 1160
1152 /* Bit definitions for SMPS_POWERGOOD_MASK1 * 1161 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1153 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 1162 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1154 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SH 1163 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1155 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 1164 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1156 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHI 1165 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1157 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 1166 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1158 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHI 1167 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1159 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1160 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHI 1169 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1161 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 1170 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1162 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHI 1171 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1163 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 1172 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1164 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SH 1173 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1165 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 1174 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1166 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHI 1175 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1167 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 1176 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1168 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SH 1177 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1169 1178
1170 /* Bit definitions for SMPS_POWERGOOD_MASK2 * 1179 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1171 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD 1180 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1172 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD 1181 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1173 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 1182 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1174 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SH 1183 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1175 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 1184 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1176 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIF 1185 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1177 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 1186 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1178 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIF 1187 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1179 1188
1180 /* Registers for function LDO */ 1189 /* Registers for function LDO */
1181 #define PALMAS_LDO1_CTRL 1190 #define PALMAS_LDO1_CTRL 0x00
1182 #define PALMAS_LDO1_VOLTAGE 1191 #define PALMAS_LDO1_VOLTAGE 0x01
1183 #define PALMAS_LDO2_CTRL 1192 #define PALMAS_LDO2_CTRL 0x02
1184 #define PALMAS_LDO2_VOLTAGE 1193 #define PALMAS_LDO2_VOLTAGE 0x03
1185 #define PALMAS_LDO3_CTRL 1194 #define PALMAS_LDO3_CTRL 0x04
1186 #define PALMAS_LDO3_VOLTAGE 1195 #define PALMAS_LDO3_VOLTAGE 0x05
1187 #define PALMAS_LDO4_CTRL 1196 #define PALMAS_LDO4_CTRL 0x06
1188 #define PALMAS_LDO4_VOLTAGE 1197 #define PALMAS_LDO4_VOLTAGE 0x07
1189 #define PALMAS_LDO5_CTRL 1198 #define PALMAS_LDO5_CTRL 0x08
1190 #define PALMAS_LDO5_VOLTAGE 1199 #define PALMAS_LDO5_VOLTAGE 0x09
1191 #define PALMAS_LDO6_CTRL 1200 #define PALMAS_LDO6_CTRL 0x0A
1192 #define PALMAS_LDO6_VOLTAGE 1201 #define PALMAS_LDO6_VOLTAGE 0x0B
1193 #define PALMAS_LDO7_CTRL 1202 #define PALMAS_LDO7_CTRL 0x0C
1194 #define PALMAS_LDO7_VOLTAGE 1203 #define PALMAS_LDO7_VOLTAGE 0x0D
1195 #define PALMAS_LDO8_CTRL 1204 #define PALMAS_LDO8_CTRL 0x0E
1196 #define PALMAS_LDO8_VOLTAGE 1205 #define PALMAS_LDO8_VOLTAGE 0x0F
1197 #define PALMAS_LDO9_CTRL 1206 #define PALMAS_LDO9_CTRL 0x10
1198 #define PALMAS_LDO9_VOLTAGE 1207 #define PALMAS_LDO9_VOLTAGE 0x11
1199 #define PALMAS_LDOLN_CTRL 1208 #define PALMAS_LDOLN_CTRL 0x12
1200 #define PALMAS_LDOLN_VOLTAGE 1209 #define PALMAS_LDOLN_VOLTAGE 0x13
1201 #define PALMAS_LDOUSB_CTRL 1210 #define PALMAS_LDOUSB_CTRL 0x14
1202 #define PALMAS_LDOUSB_VOLTAGE 1211 #define PALMAS_LDOUSB_VOLTAGE 0x15
1203 #define PALMAS_LDO_CTRL 1212 #define PALMAS_LDO_CTRL 0x1A
1204 #define PALMAS_LDO_PD_CTRL1 1213 #define PALMAS_LDO_PD_CTRL1 0x1B
1205 #define PALMAS_LDO_PD_CTRL2 1214 #define PALMAS_LDO_PD_CTRL2 0x1C
1206 #define PALMAS_LDO_SHORT_STATUS1 1215 #define PALMAS_LDO_SHORT_STATUS1 0x1D
1207 #define PALMAS_LDO_SHORT_STATUS2 1216 #define PALMAS_LDO_SHORT_STATUS2 0x1E
1208 1217
1209 /* Bit definitions for LDO1_CTRL */ 1218 /* Bit definitions for LDO1_CTRL */
1210 #define PALMAS_LDO1_CTRL_WR_S 1219 #define PALMAS_LDO1_CTRL_WR_S 0x80
1211 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 1220 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1212 #define PALMAS_LDO1_CTRL_STATUS 1221 #define PALMAS_LDO1_CTRL_STATUS 0x10
1213 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 1222 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1214 #define PALMAS_LDO1_CTRL_MODE_SLEEP 1223 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1215 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 1224 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1216 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 1225 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1217 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 1226 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1218 1227
1219 /* Bit definitions for LDO1_VOLTAGE */ 1228 /* Bit definitions for LDO1_VOLTAGE */
1220 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 1229 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1221 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 1230 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1222 1231
1223 /* Bit definitions for LDO2_CTRL */ 1232 /* Bit definitions for LDO2_CTRL */
1224 #define PALMAS_LDO2_CTRL_WR_S 1233 #define PALMAS_LDO2_CTRL_WR_S 0x80
1225 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 1234 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1226 #define PALMAS_LDO2_CTRL_STATUS 1235 #define PALMAS_LDO2_CTRL_STATUS 0x10
1227 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 1236 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1228 #define PALMAS_LDO2_CTRL_MODE_SLEEP 1237 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1229 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 1238 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1230 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 1239 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1231 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 1240 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1232 1241
1233 /* Bit definitions for LDO2_VOLTAGE */ 1242 /* Bit definitions for LDO2_VOLTAGE */
1234 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 1243 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1235 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 1244 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1236 1245
1237 /* Bit definitions for LDO3_CTRL */ 1246 /* Bit definitions for LDO3_CTRL */
1238 #define PALMAS_LDO3_CTRL_WR_S 1247 #define PALMAS_LDO3_CTRL_WR_S 0x80
1239 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 1248 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1240 #define PALMAS_LDO3_CTRL_STATUS 1249 #define PALMAS_LDO3_CTRL_STATUS 0x10
1241 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 1250 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1242 #define PALMAS_LDO3_CTRL_MODE_SLEEP 1251 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1243 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 1252 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1244 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 1253 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1245 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 1254 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1246 1255
1247 /* Bit definitions for LDO3_VOLTAGE */ 1256 /* Bit definitions for LDO3_VOLTAGE */
1248 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 1257 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1249 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 1258 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1250 1259
1251 /* Bit definitions for LDO4_CTRL */ 1260 /* Bit definitions for LDO4_CTRL */
1252 #define PALMAS_LDO4_CTRL_WR_S 1261 #define PALMAS_LDO4_CTRL_WR_S 0x80
1253 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 1262 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1254 #define PALMAS_LDO4_CTRL_STATUS 1263 #define PALMAS_LDO4_CTRL_STATUS 0x10
1255 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 1264 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1256 #define PALMAS_LDO4_CTRL_MODE_SLEEP 1265 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1257 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 1266 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1258 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 1267 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1259 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 1268 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1260 1269
1261 /* Bit definitions for LDO4_VOLTAGE */ 1270 /* Bit definitions for LDO4_VOLTAGE */
1262 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 1271 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1263 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 1272 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1264 1273
1265 /* Bit definitions for LDO5_CTRL */ 1274 /* Bit definitions for LDO5_CTRL */
1266 #define PALMAS_LDO5_CTRL_WR_S 1275 #define PALMAS_LDO5_CTRL_WR_S 0x80
1267 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 1276 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1268 #define PALMAS_LDO5_CTRL_STATUS 1277 #define PALMAS_LDO5_CTRL_STATUS 0x10
1269 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 1278 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1270 #define PALMAS_LDO5_CTRL_MODE_SLEEP 1279 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1271 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 1280 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1272 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 1281 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1273 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 1282 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1274 1283
1275 /* Bit definitions for LDO5_VOLTAGE */ 1284 /* Bit definitions for LDO5_VOLTAGE */
1276 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 1285 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1277 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 1286 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1278 1287
1279 /* Bit definitions for LDO6_CTRL */ 1288 /* Bit definitions for LDO6_CTRL */
1280 #define PALMAS_LDO6_CTRL_WR_S 1289 #define PALMAS_LDO6_CTRL_WR_S 0x80
1281 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 1290 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1282 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 1291 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1283 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 1292 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1284 #define PALMAS_LDO6_CTRL_STATUS 1293 #define PALMAS_LDO6_CTRL_STATUS 0x10
1285 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 1294 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1286 #define PALMAS_LDO6_CTRL_MODE_SLEEP 1295 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1287 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 1296 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1288 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 1297 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1289 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 1298 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1290 1299
1291 /* Bit definitions for LDO6_VOLTAGE */ 1300 /* Bit definitions for LDO6_VOLTAGE */
1292 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 1301 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1293 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 1302 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1294 1303
1295 /* Bit definitions for LDO7_CTRL */ 1304 /* Bit definitions for LDO7_CTRL */
1296 #define PALMAS_LDO7_CTRL_WR_S 1305 #define PALMAS_LDO7_CTRL_WR_S 0x80
1297 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 1306 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1298 #define PALMAS_LDO7_CTRL_STATUS 1307 #define PALMAS_LDO7_CTRL_STATUS 0x10
1299 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 1308 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1300 #define PALMAS_LDO7_CTRL_MODE_SLEEP 1309 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1301 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 1310 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1302 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 1311 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1303 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 1312 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1304 1313
1305 /* Bit definitions for LDO7_VOLTAGE */ 1314 /* Bit definitions for LDO7_VOLTAGE */
1306 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 1315 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1307 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 1316 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1308 1317
1309 /* Bit definitions for LDO8_CTRL */ 1318 /* Bit definitions for LDO8_CTRL */
1310 #define PALMAS_LDO8_CTRL_WR_S 1319 #define PALMAS_LDO8_CTRL_WR_S 0x80
1311 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 1320 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1312 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 1321 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1313 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIF 1322 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1314 #define PALMAS_LDO8_CTRL_STATUS 1323 #define PALMAS_LDO8_CTRL_STATUS 0x10
1315 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 1324 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1316 #define PALMAS_LDO8_CTRL_MODE_SLEEP 1325 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1317 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 1326 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1318 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 1327 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1319 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 1328 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1320 1329
1321 /* Bit definitions for LDO8_VOLTAGE */ 1330 /* Bit definitions for LDO8_VOLTAGE */
1322 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 1331 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1323 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 1332 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1324 1333
1325 /* Bit definitions for LDO9_CTRL */ 1334 /* Bit definitions for LDO9_CTRL */
1326 #define PALMAS_LDO9_CTRL_WR_S 1335 #define PALMAS_LDO9_CTRL_WR_S 0x80
1327 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 1336 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1328 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 1337 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1329 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 1338 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1330 #define PALMAS_LDO9_CTRL_STATUS 1339 #define PALMAS_LDO9_CTRL_STATUS 0x10
1331 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 1340 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1332 #define PALMAS_LDO9_CTRL_MODE_SLEEP 1341 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1333 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 1342 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1334 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 1343 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1335 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 1344 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1336 1345
1337 /* Bit definitions for LDO9_VOLTAGE */ 1346 /* Bit definitions for LDO9_VOLTAGE */
1338 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 1347 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1339 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 1348 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1340 1349
1341 /* Bit definitions for LDOLN_CTRL */ 1350 /* Bit definitions for LDOLN_CTRL */
1342 #define PALMAS_LDOLN_CTRL_WR_S 1351 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1343 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 1352 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1344 #define PALMAS_LDOLN_CTRL_STATUS 1353 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1345 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 1354 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1346 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 1355 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1347 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 1356 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1348 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 1357 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1349 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 1358 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1350 1359
1351 /* Bit definitions for LDOLN_VOLTAGE */ 1360 /* Bit definitions for LDOLN_VOLTAGE */
1352 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 1361 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1353 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 1362 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1354 1363
1355 /* Bit definitions for LDOUSB_CTRL */ 1364 /* Bit definitions for LDOUSB_CTRL */
1356 #define PALMAS_LDOUSB_CTRL_WR_S 1365 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1357 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 1366 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1358 #define PALMAS_LDOUSB_CTRL_STATUS 1367 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1359 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 1368 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1360 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 1369 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1361 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 1370 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1362 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 1371 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1363 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 1372 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1364 1373
1365 /* Bit definitions for LDOUSB_VOLTAGE */ 1374 /* Bit definitions for LDOUSB_VOLTAGE */
1366 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 1375 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1367 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 1376 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1368 1377
1369 /* Bit definitions for LDO_CTRL */ 1378 /* Bit definitions for LDO_CTRL */
1370 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 1379 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1371 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_S 1380 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1372 1381
1373 /* Bit definitions for LDO_PD_CTRL1 */ 1382 /* Bit definitions for LDO_PD_CTRL1 */
1374 #define PALMAS_LDO_PD_CTRL1_LDO8 1383 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1375 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 1384 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1376 #define PALMAS_LDO_PD_CTRL1_LDO7 1385 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1377 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 1386 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1378 #define PALMAS_LDO_PD_CTRL1_LDO6 1387 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1379 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 1388 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1380 #define PALMAS_LDO_PD_CTRL1_LDO5 1389 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1381 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 1390 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1382 #define PALMAS_LDO_PD_CTRL1_LDO4 1391 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1383 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 1392 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1384 #define PALMAS_LDO_PD_CTRL1_LDO3 1393 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1385 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 1394 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1386 #define PALMAS_LDO_PD_CTRL1_LDO2 1395 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1387 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1396 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1388 #define PALMAS_LDO_PD_CTRL1_LDO1 1397 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1389 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 1398 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1390 1399
1391 /* Bit definitions for LDO_PD_CTRL2 */ 1400 /* Bit definitions for LDO_PD_CTRL2 */
1392 #define PALMAS_LDO_PD_CTRL2_LDOUSB 1401 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1393 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 1402 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1394 #define PALMAS_LDO_PD_CTRL2_LDOLN 1403 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1395 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1404 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1396 #define PALMAS_LDO_PD_CTRL2_LDO9 1405 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1397 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 1406 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1398 1407
1399 /* Bit definitions for LDO_SHORT_STATUS1 */ 1408 /* Bit definitions for LDO_SHORT_STATUS1 */
1400 #define PALMAS_LDO_SHORT_STATUS1_LDO8 1409 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1401 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 1410 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1402 #define PALMAS_LDO_SHORT_STATUS1_LDO7 1411 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1403 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 1412 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1404 #define PALMAS_LDO_SHORT_STATUS1_LDO6 1413 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1405 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 1414 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1406 #define PALMAS_LDO_SHORT_STATUS1_LDO5 1415 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1407 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 1416 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1408 #define PALMAS_LDO_SHORT_STATUS1_LDO4 1417 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1409 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 1418 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1410 #define PALMAS_LDO_SHORT_STATUS1_LDO3 1419 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1411 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 1420 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1412 #define PALMAS_LDO_SHORT_STATUS1_LDO2 1421 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1413 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1422 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1414 #define PALMAS_LDO_SHORT_STATUS1_LDO1 1423 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1415 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 1424 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1416 1425
1417 /* Bit definitions for LDO_SHORT_STATUS2 */ 1426 /* Bit definitions for LDO_SHORT_STATUS2 */
1418 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 1427 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1419 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIF 1428 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1420 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 1429 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1421 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 1430 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1422 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 1431 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1423 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1432 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1424 #define PALMAS_LDO_SHORT_STATUS2_LDO9 1433 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1425 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 1434 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1426 1435
1427 /* Registers for function PMU_CONTROL */ 1436 /* Registers for function PMU_CONTROL */
1428 #define PALMAS_DEV_CTRL 1437 #define PALMAS_DEV_CTRL 0x00
1429 #define PALMAS_POWER_CTRL 1438 #define PALMAS_POWER_CTRL 0x01
1430 #define PALMAS_VSYS_LO 1439 #define PALMAS_VSYS_LO 0x02
1431 #define PALMAS_VSYS_MON 1440 #define PALMAS_VSYS_MON 0x03
1432 #define PALMAS_VBAT_MON 1441 #define PALMAS_VBAT_MON 0x04
1433 #define PALMAS_WATCHDOG 1442 #define PALMAS_WATCHDOG 0x05
1434 #define PALMAS_BOOT_STATUS 1443 #define PALMAS_BOOT_STATUS 0x06
1435 #define PALMAS_BATTERY_BOUNCE 1444 #define PALMAS_BATTERY_BOUNCE 0x07
1436 #define PALMAS_BACKUP_BATTERY_CTRL 1445 #define PALMAS_BACKUP_BATTERY_CTRL 0x08
1437 #define PALMAS_LONG_PRESS_KEY 1446 #define PALMAS_LONG_PRESS_KEY 0x09
1438 #define PALMAS_OSC_THERM_CTRL 1447 #define PALMAS_OSC_THERM_CTRL 0x0A
1439 #define PALMAS_BATDEBOUNCING 1448 #define PALMAS_BATDEBOUNCING 0x0B
1440 #define PALMAS_SWOFF_HWRST 1449 #define PALMAS_SWOFF_HWRST 0x0F
1441 #define PALMAS_SWOFF_COLDRST 1450 #define PALMAS_SWOFF_COLDRST 0x10
1442 #define PALMAS_SWOFF_STATUS 1451 #define PALMAS_SWOFF_STATUS 0x11
1443 #define PALMAS_PMU_CONFIG 1452 #define PALMAS_PMU_CONFIG 0x12
1444 #define PALMAS_SPARE 1453 #define PALMAS_SPARE 0x14
1445 #define PALMAS_PMU_SECONDARY_INT 1454 #define PALMAS_PMU_SECONDARY_INT 0x15
1446 #define PALMAS_SW_REVISION 1455 #define PALMAS_SW_REVISION 0x17
1447 #define PALMAS_EXT_CHRG_CTRL 1456 #define PALMAS_EXT_CHRG_CTRL 0x18
1448 #define PALMAS_PMU_SECONDARY_INT2 1457 #define PALMAS_PMU_SECONDARY_INT2 0x19
1449 1458
1450 /* Bit definitions for DEV_CTRL */ 1459 /* Bit definitions for DEV_CTRL */
1451 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 1460 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1452 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 1461 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1453 #define PALMAS_DEV_CTRL_SW_RST 1462 #define PALMAS_DEV_CTRL_SW_RST 0x02
1454 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 1463 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1455 #define PALMAS_DEV_CTRL_DEV_ON 1464 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1456 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 1465 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1457 1466
1458 /* Bit definitions for POWER_CTRL */ 1467 /* Bit definitions for POWER_CTRL */
1459 #define PALMAS_POWER_CTRL_ENABLE2_MASK 1468 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1460 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 1469 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1461 #define PALMAS_POWER_CTRL_ENABLE1_MASK 1470 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1462 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1471 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1463 #define PALMAS_POWER_CTRL_NSLEEP_MASK 1472 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1464 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 1473 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1465 1474
1466 /* Bit definitions for VSYS_LO */ 1475 /* Bit definitions for VSYS_LO */
1467 #define PALMAS_VSYS_LO_THRESHOLD_MASK 1476 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1468 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 1477 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1469 1478
1470 /* Bit definitions for VSYS_MON */ 1479 /* Bit definitions for VSYS_MON */
1471 #define PALMAS_VSYS_MON_ENABLE 1480 #define PALMAS_VSYS_MON_ENABLE 0x80
1472 #define PALMAS_VSYS_MON_ENABLE_SHIFT 1481 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1473 #define PALMAS_VSYS_MON_THRESHOLD_MASK 1482 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1474 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 1483 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1475 1484
1476 /* Bit definitions for VBAT_MON */ 1485 /* Bit definitions for VBAT_MON */
1477 #define PALMAS_VBAT_MON_ENABLE 1486 #define PALMAS_VBAT_MON_ENABLE 0x80
1478 #define PALMAS_VBAT_MON_ENABLE_SHIFT 1487 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1479 #define PALMAS_VBAT_MON_THRESHOLD_MASK 1488 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1480 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 1489 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1481 1490
1482 /* Bit definitions for WATCHDOG */ 1491 /* Bit definitions for WATCHDOG */
1483 #define PALMAS_WATCHDOG_LOCK 1492 #define PALMAS_WATCHDOG_LOCK 0x20
1484 #define PALMAS_WATCHDOG_LOCK_SHIFT 1493 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1485 #define PALMAS_WATCHDOG_ENABLE 1494 #define PALMAS_WATCHDOG_ENABLE 0x10
1486 #define PALMAS_WATCHDOG_ENABLE_SHIFT 1495 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1487 #define PALMAS_WATCHDOG_MODE 1496 #define PALMAS_WATCHDOG_MODE 0x08
1488 #define PALMAS_WATCHDOG_MODE_SHIFT 1497 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1489 #define PALMAS_WATCHDOG_TIMER_MASK 1498 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1490 #define PALMAS_WATCHDOG_TIMER_SHIFT 1499 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1491 1500
1492 /* Bit definitions for BOOT_STATUS */ 1501 /* Bit definitions for BOOT_STATUS */
1493 #define PALMAS_BOOT_STATUS_BOOT1 1502 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1494 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1503 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1495 #define PALMAS_BOOT_STATUS_BOOT0 1504 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1496 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 1505 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1497 1506
1498 /* Bit definitions for BATTERY_BOUNCE */ 1507 /* Bit definitions for BATTERY_BOUNCE */
1499 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 1508 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1500 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 1509 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1501 1510
1502 /* Bit definitions for BACKUP_BATTERY_CTRL */ 1511 /* Bit definitions for BACKUP_BATTERY_CTRL */
1503 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 1512 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1504 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 1513 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1505 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SL 1514 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1506 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SL 1515 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1507 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OF 1516 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1508 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OF 1517 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1509 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 1518 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1510 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_ 1519 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1511 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LO 1520 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1512 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LO 1521 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1513 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MAS 1522 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1514 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHI 1523 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1515 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 1524 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1516 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_ 1525 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1517 1526
1518 /* Bit definitions for LONG_PRESS_KEY */ 1527 /* Bit definitions for LONG_PRESS_KEY */
1519 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 1528 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1520 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 1529 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1521 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 1530 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1522 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHI 1531 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1523 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 1532 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1524 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 1533 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1525 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_ 1534 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1526 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_ 1535 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1527 1536
1528 /* Bit definitions for OSC_THERM_CTRL */ 1537 /* Bit definitions for OSC_THERM_CTRL */
1529 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEE 1538 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1530 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEE 1539 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1531 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLE 1540 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1532 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLE 1541 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1533 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_S 1542 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1534 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_S 1543 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1535 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SL 1544 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1536 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SL 1545 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1537 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MA 1546 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1538 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SH 1547 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1539 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 1548 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1540 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIF 1549 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1541 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 1550 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1542 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIF 1551 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1543 1552
1544 /* Bit definitions for BATDEBOUNCING */ 1553 /* Bit definitions for BATDEBOUNCING */
1545 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 1554 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1546 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_S 1555 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1547 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 1556 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1548 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 1557 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1549 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 1558 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1550 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 1559 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1551 1560
1552 /* Bit definitions for SWOFF_HWRST */ 1561 /* Bit definitions for SWOFF_HWRST */
1553 #define PALMAS_SWOFF_HWRST_PWRON_LPK 1562 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1554 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 1563 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1555 #define PALMAS_SWOFF_HWRST_PWRDOWN 1564 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1556 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 1565 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1557 #define PALMAS_SWOFF_HWRST_WTD 1566 #define PALMAS_SWOFF_HWRST_WTD 0x20
1558 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 1567 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1559 #define PALMAS_SWOFF_HWRST_TSHUT 1568 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1560 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 1569 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1561 #define PALMAS_SWOFF_HWRST_RESET_IN 1570 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1562 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 1571 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1563 #define PALMAS_SWOFF_HWRST_SW_RST 1572 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1564 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 1573 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1565 #define PALMAS_SWOFF_HWRST_VSYS_LO 1574 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1566 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1575 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1567 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 1576 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1568 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHI 1577 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1569 1578
1570 /* Bit definitions for SWOFF_COLDRST */ 1579 /* Bit definitions for SWOFF_COLDRST */
1571 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 1580 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1572 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 1581 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1573 #define PALMAS_SWOFF_COLDRST_PWRDOWN 1582 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1574 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 1583 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1575 #define PALMAS_SWOFF_COLDRST_WTD 1584 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1576 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 1585 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1577 #define PALMAS_SWOFF_COLDRST_TSHUT 1586 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1578 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 1587 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1579 #define PALMAS_SWOFF_COLDRST_RESET_IN 1588 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1580 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 1589 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1581 #define PALMAS_SWOFF_COLDRST_SW_RST 1590 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1582 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 1591 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1583 #define PALMAS_SWOFF_COLDRST_VSYS_LO 1592 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1584 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1593 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1585 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 1594 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1586 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_S 1595 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1587 1596
1588 /* Bit definitions for SWOFF_STATUS */ 1597 /* Bit definitions for SWOFF_STATUS */
1589 #define PALMAS_SWOFF_STATUS_PWRON_LPK 1598 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1590 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 1599 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1591 #define PALMAS_SWOFF_STATUS_PWRDOWN 1600 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1592 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 1601 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1593 #define PALMAS_SWOFF_STATUS_WTD 1602 #define PALMAS_SWOFF_STATUS_WTD 0x20
1594 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 1603 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1595 #define PALMAS_SWOFF_STATUS_TSHUT 1604 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1596 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 1605 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1597 #define PALMAS_SWOFF_STATUS_RESET_IN 1606 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1598 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 1607 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1599 #define PALMAS_SWOFF_STATUS_SW_RST 1608 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1600 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 1609 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1601 #define PALMAS_SWOFF_STATUS_VSYS_LO 1610 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1602 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1611 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1603 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 1612 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1604 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SH 1613 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1605 1614
1606 /* Bit definitions for PMU_CONFIG */ 1615 /* Bit definitions for PMU_CONFIG */
1607 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 1616 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1608 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 1617 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1609 #define PALMAS_PMU_CONFIG_SPARE_MASK 1618 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1610 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 1619 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1611 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 1620 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1612 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 1621 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1613 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 1622 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1614 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIF 1623 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1615 #define PALMAS_PMU_CONFIG_AUTODEVON 1624 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1616 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 1625 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1617 1626
1618 /* Bit definitions for SPARE */ 1627 /* Bit definitions for SPARE */
1619 #define PALMAS_SPARE_SPARE_MASK 1628 #define PALMAS_SPARE_SPARE_MASK 0xf8
1620 #define PALMAS_SPARE_SPARE_SHIFT 1629 #define PALMAS_SPARE_SPARE_SHIFT 0x03
1621 #define PALMAS_SPARE_REGEN3_OD 1630 #define PALMAS_SPARE_REGEN3_OD 0x04
1622 #define PALMAS_SPARE_REGEN3_OD_SHIFT 1631 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1623 #define PALMAS_SPARE_REGEN2_OD 1632 #define PALMAS_SPARE_REGEN2_OD 0x02
1624 #define PALMAS_SPARE_REGEN2_OD_SHIFT 1633 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1625 #define PALMAS_SPARE_REGEN1_OD 1634 #define PALMAS_SPARE_REGEN1_OD 0x01
1626 #define PALMAS_SPARE_REGEN1_OD_SHIFT 1635 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1627 1636
1628 /* Bit definitions for PMU_SECONDARY_INT */ 1637 /* Bit definitions for PMU_SECONDARY_INT */
1629 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT 1638 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1630 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT 1639 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1631 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_ 1640 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1632 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_ 1641 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1633 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 1642 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1634 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_S 1643 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1635 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 1644 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1636 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_ 1645 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1637 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MAS 1646 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1638 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MAS 1647 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1639 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_ 1648 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1640 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_ 1649 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1641 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 1650 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1642 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIF 1651 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1643 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 1652 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1644 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHI 1653 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1645 1654
1646 /* Bit definitions for SW_REVISION */ 1655 /* Bit definitions for SW_REVISION */
1647 #define PALMAS_SW_REVISION_SW_REVISION_MASK 1656 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1648 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 1657 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1649 1658
1650 /* Bit definitions for EXT_CHRG_CTRL */ 1659 /* Bit definitions for EXT_CHRG_CTRL */
1651 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 1660 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1652 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_ 1661 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1653 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STAT 1662 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1654 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STAT 1663 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1655 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DE 1664 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1656 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DE 1665 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1657 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 1666 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1658 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 1667 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1659 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 1668 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1660 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIF 1669 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1661 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 1670 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1662 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_S 1671 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1663 1672
1664 /* Bit definitions for PMU_SECONDARY_INT2 */ 1673 /* Bit definitions for PMU_SECONDARY_INT2 */
1665 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_S 1674 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1666 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_S 1675 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1667 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_S 1676 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1668 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_S 1677 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1669 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 1678 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1670 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_ 1679 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1671 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 1680 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1672 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_ 1681 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1673 1682
1674 /* Registers for function RESOURCE */ 1683 /* Registers for function RESOURCE */
1675 #define PALMAS_CLK32KG_CTRL 1684 #define PALMAS_CLK32KG_CTRL 0x00
1676 #define PALMAS_CLK32KGAUDIO_CTRL 1685 #define PALMAS_CLK32KGAUDIO_CTRL 0x01
1677 #define PALMAS_REGEN1_CTRL 1686 #define PALMAS_REGEN1_CTRL 0x02
1678 #define PALMAS_REGEN2_CTRL 1687 #define PALMAS_REGEN2_CTRL 0x03
1679 #define PALMAS_SYSEN1_CTRL 1688 #define PALMAS_SYSEN1_CTRL 0x04
1680 #define PALMAS_SYSEN2_CTRL 1689 #define PALMAS_SYSEN2_CTRL 0x05
1681 #define PALMAS_NSLEEP_RES_ASSIGN 1690 #define PALMAS_NSLEEP_RES_ASSIGN 0x06
1682 #define PALMAS_NSLEEP_SMPS_ASSIGN 1691 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1683 #define PALMAS_NSLEEP_LDO_ASSIGN1 1692 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1684 #define PALMAS_NSLEEP_LDO_ASSIGN2 1693 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1685 #define PALMAS_ENABLE1_RES_ASSIGN 1694 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1686 #define PALMAS_ENABLE1_SMPS_ASSIGN 1695 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1687 #define PALMAS_ENABLE1_LDO_ASSIGN1 1696 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1688 #define PALMAS_ENABLE1_LDO_ASSIGN2 1697 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1689 #define PALMAS_ENABLE2_RES_ASSIGN 1698 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1690 #define PALMAS_ENABLE2_SMPS_ASSIGN 1699 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1691 #define PALMAS_ENABLE2_LDO_ASSIGN1 1700 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1692 #define PALMAS_ENABLE2_LDO_ASSIGN2 1701 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1693 #define PALMAS_REGEN3_CTRL 1702 #define PALMAS_REGEN3_CTRL 0x12
1694 1703
1695 /* Bit definitions for CLK32KG_CTRL */ 1704 /* Bit definitions for CLK32KG_CTRL */
1696 #define PALMAS_CLK32KG_CTRL_STATUS 1705 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1697 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 1706 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1698 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 1707 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1699 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 1708 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1700 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 1709 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1701 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 1710 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1702 1711
1703 /* Bit definitions for CLK32KGAUDIO_CTRL */ 1712 /* Bit definitions for CLK32KGAUDIO_CTRL */
1704 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 1713 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1705 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 1714 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1706 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 1715 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1707 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SH 1716 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1708 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 1717 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1709 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_S 1718 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1710 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 1719 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1711 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_ 1720 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1712 1721
1713 /* Bit definitions for REGEN1_CTRL */ 1722 /* Bit definitions for REGEN1_CTRL */
1714 #define PALMAS_REGEN1_CTRL_STATUS 1723 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1715 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 1724 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1716 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 1725 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1717 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 1726 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1718 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 1727 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1719 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 1728 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1720 1729
1721 /* Bit definitions for REGEN2_CTRL */ 1730 /* Bit definitions for REGEN2_CTRL */
1722 #define PALMAS_REGEN2_CTRL_STATUS 1731 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1723 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 1732 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1724 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 1733 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1725 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 1734 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1726 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 1735 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1727 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 1736 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1728 1737
1729 /* Bit definitions for SYSEN1_CTRL */ 1738 /* Bit definitions for SYSEN1_CTRL */
1730 #define PALMAS_SYSEN1_CTRL_STATUS 1739 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1731 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 1740 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1732 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 1741 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1733 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 1742 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1734 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 1743 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1735 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 1744 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1736 1745
1737 /* Bit definitions for SYSEN2_CTRL */ 1746 /* Bit definitions for SYSEN2_CTRL */
1738 #define PALMAS_SYSEN2_CTRL_STATUS 1747 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1739 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 1748 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1740 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 1749 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1741 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 1750 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1742 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 1751 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1743 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 1752 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1744 1753
1745 /* Bit definitions for NSLEEP_RES_ASSIGN */ 1754 /* Bit definitions for NSLEEP_RES_ASSIGN */
1746 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 1755 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1747 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 1756 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1748 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 1757 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1749 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 1758 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1750 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 1759 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1751 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIF 1760 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1752 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 1761 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1753 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 1762 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1754 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 1763 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1755 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 1764 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1756 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 1765 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1757 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1766 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1758 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 1767 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1759 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 1768 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1760 1769
1761 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1770 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1762 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 1771 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1763 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIF 1772 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1764 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 1773 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1765 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 1774 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1766 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 1775 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1767 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 1776 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1768 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1769 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 1778 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1770 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 1779 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1771 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 1780 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1772 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 1781 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1773 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIF 1782 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1774 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 1783 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1775 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1784 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1776 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 1785 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1777 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIF 1786 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1778 1787
1779 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1788 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1780 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 1789 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1781 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 1790 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1782 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 1791 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1783 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 1792 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1784 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 1793 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1785 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 1794 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1786 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1787 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 1796 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1788 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 1797 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1789 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 1798 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1790 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 1799 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1791 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 1800 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1792 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 1801 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1793 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1802 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1794 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 1803 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1795 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 1804 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1796 1805
1797 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1806 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1798 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 1807 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1799 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIF 1808 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1800 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 1809 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1801 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1810 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1802 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 1811 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1803 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 1812 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1804 1813
1805 /* Bit definitions for ENABLE1_RES_ASSIGN */ 1814 /* Bit definitions for ENABLE1_RES_ASSIGN */
1806 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 1815 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1807 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIF 1816 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1808 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDI 1817 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1809 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDI 1818 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1810 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 1819 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1811 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHI 1820 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1812 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 1821 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1813 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIF 1822 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1814 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 1823 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1815 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIF 1824 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1816 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 1825 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1817 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIF 1826 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1818 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 1827 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1819 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIF 1828 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1820 1829
1821 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1830 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1822 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 1831 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1823 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHI 1832 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1824 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 1833 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1825 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIF 1834 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1826 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 1835 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1827 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIF 1836 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1828 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1829 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIF 1838 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1830 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 1839 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1831 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIF 1840 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1832 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 1841 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1833 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHI 1842 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1834 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 1843 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1835 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIF 1844 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1836 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 1845 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1837 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHI 1846 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1838 1847
1839 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1848 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1840 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 1849 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1841 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 1850 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1842 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 1851 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1843 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 1852 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1844 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 1853 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1845 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 1854 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1846 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1847 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 1856 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1848 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 1857 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1849 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 1858 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1850 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 1859 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1851 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 1860 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1852 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 1861 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1853 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1862 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1854 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 1863 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1855 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 1864 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1856 1865
1857 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1866 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1858 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 1867 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1859 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHI 1868 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1860 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 1869 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1861 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIF 1870 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1862 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 1871 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1863 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 1872 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1864 1873
1865 /* Bit definitions for ENABLE2_RES_ASSIGN */ 1874 /* Bit definitions for ENABLE2_RES_ASSIGN */
1866 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 1875 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1867 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIF 1876 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1868 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDI 1877 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1869 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDI 1878 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1870 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 1879 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1871 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHI 1880 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1872 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 1881 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1873 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIF 1882 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1874 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 1883 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1875 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIF 1884 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1876 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 1885 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1877 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIF 1886 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1878 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 1887 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1879 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIF 1888 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1880 1889
1881 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1890 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1882 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 1891 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1883 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHI 1892 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1884 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 1893 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1885 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIF 1894 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1886 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 1895 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1887 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIF 1896 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1888 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1889 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIF 1898 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1890 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 1899 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1891 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIF 1900 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1892 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 1901 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1893 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHI 1902 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1894 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 1903 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1895 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIF 1904 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1896 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 1905 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1897 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHI 1906 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1898 1907
1899 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1908 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1900 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 1909 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1901 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 1910 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1902 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 1911 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1903 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 1912 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1904 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 1913 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1905 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 1914 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1906 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1907 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 1916 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1908 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 1917 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1909 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 1918 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1910 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 1919 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1911 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 1920 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1912 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 1921 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1913 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1922 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1914 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 1923 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1915 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 1924 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1916 1925
1917 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1926 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1918 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 1927 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1919 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHI 1928 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1920 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 1929 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1921 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIF 1930 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1922 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 1931 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1923 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 1932 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1924 1933
1925 /* Bit definitions for REGEN3_CTRL */ 1934 /* Bit definitions for REGEN3_CTRL */
1926 #define PALMAS_REGEN3_CTRL_STATUS 1935 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1927 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 1936 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1928 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 1937 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1929 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 1938 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1930 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 1939 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1931 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 1940 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1932 1941
1933 /* Registers for function PAD_CONTROL */ 1942 /* Registers for function PAD_CONTROL */
1934 #define PALMAS_OD_OUTPUT_CTRL2 1943 #define PALMAS_OD_OUTPUT_CTRL2 0x02
1935 #define PALMAS_POLARITY_CTRL2 1944 #define PALMAS_POLARITY_CTRL2 0x03
1936 #define PALMAS_PU_PD_INPUT_CTRL1 1945 #define PALMAS_PU_PD_INPUT_CTRL1 0x04
1937 #define PALMAS_PU_PD_INPUT_CTRL2 1946 #define PALMAS_PU_PD_INPUT_CTRL2 0x05
1938 #define PALMAS_PU_PD_INPUT_CTRL3 1947 #define PALMAS_PU_PD_INPUT_CTRL3 0x06
1939 #define PALMAS_PU_PD_INPUT_CTRL5 1948 #define PALMAS_PU_PD_INPUT_CTRL5 0x07
1940 #define PALMAS_OD_OUTPUT_CTRL 1949 #define PALMAS_OD_OUTPUT_CTRL 0x08
1941 #define PALMAS_POLARITY_CTRL 1950 #define PALMAS_POLARITY_CTRL 0x09
1942 #define PALMAS_PRIMARY_SECONDARY_PAD1 1951 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1943 #define PALMAS_PRIMARY_SECONDARY_PAD2 1952 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1944 #define PALMAS_I2C_SPI 1953 #define PALMAS_I2C_SPI 0x0C
1945 #define PALMAS_PU_PD_INPUT_CTRL4 1954 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1946 #define PALMAS_PRIMARY_SECONDARY_PAD3 1955 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1947 #define PALMAS_PRIMARY_SECONDARY_PAD4 1956 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1948 1957
1949 /* Bit definitions for PU_PD_INPUT_CTRL1 */ 1958 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1950 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 1959 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1951 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_ 1960 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1952 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_ 1961 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1953 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_ 1962 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1954 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_ 1963 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1955 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_ 1964 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1956 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 1965 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1957 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_S 1966 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1958 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 1967 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1959 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_ 1968 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1960 1969
1961 /* Bit definitions for PU_PD_INPUT_CTRL2 */ 1970 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1962 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 1971 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1963 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_S 1972 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1964 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 1973 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1965 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_S 1974 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1966 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 1975 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1967 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_S 1976 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1968 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 1977 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1969 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_S 1978 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1970 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 1979 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1971 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SH 1980 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1972 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 1981 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1973 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SH 1982 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1974 1983
1975 /* Bit definitions for PU_PD_INPUT_CTRL3 */ 1984 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1976 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 1985 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1977 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIF 1986 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1978 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_P 1987 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1979 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_P 1988 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1980 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 1989 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1981 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 1990 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1982 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 1991 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1983 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_S 1992 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1984 1993
1985 /* Bit definitions for OD_OUTPUT_CTRL */ 1994 /* Bit definitions for OD_OUTPUT_CTRL */
1986 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 1995 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1987 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 1996 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1988 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 1997 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1989 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIF 1998 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1990 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 1999 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1991 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 2000 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1992 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 2001 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1993 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 2002 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1994 2003
1995 /* Bit definitions for POLARITY_CTRL */ 2004 /* Bit definitions for POLARITY_CTRL */
1996 #define PALMAS_POLARITY_CTRL_INT_POLARITY 2005 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1997 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHI 2006 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1998 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 2007 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1999 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 2008 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2000 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 2009 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
2001 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 2010 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2002 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 2011 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
2003 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_ 2012 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2004 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARIT 2013 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
2005 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARIT 2014 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2006 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_ 2015 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
2007 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_ 2016 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2008 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PS 2017 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
2009 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PS 2018 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2010 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 2019 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
2011 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 2020 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2012 2021
2013 /* Bit definitions for PRIMARY_SECONDARY_PAD1 2022 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2014 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 2023 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
2015 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_ 2024 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2016 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_ 2025 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
2017 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_ 2026 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2018 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_ 2027 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
2019 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_ 2028 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2020 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 2029 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
2021 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_ 2030 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2022 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 2031 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
2023 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHI 2032 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2024 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGO 2033 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
2025 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGO 2034 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2026 2035
2027 /* Bit definitions for PRIMARY_SECONDARY_PAD2 2036 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2028 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_ 2037 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
2029 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_ 2038 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2030 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 2039 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
2031 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_ 2040 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2032 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_ 2041 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
2033 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_ 2042 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2034 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 2043 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
2035 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_ 2044 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2036 2045
2037 /* Bit definitions for I2C_SPI */ 2046 /* Bit definitions for I2C_SPI */
2038 #define PALMAS_I2C_SPI_I2C2OTP_EN 2047 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
2039 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 2048 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2040 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 2049 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
2041 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 2050 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2042 #define PALMAS_I2C_SPI_ID_I2C2 2051 #define PALMAS_I2C_SPI_ID_I2C2 0x20
2043 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 2052 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2044 #define PALMAS_I2C_SPI_I2C_SPI 2053 #define PALMAS_I2C_SPI_I2C_SPI 0x10
2045 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 2054 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
2046 #define PALMAS_I2C_SPI_ID_I2C1_MASK 2055 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
2047 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 2056 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2048 2057
2049 /* Bit definitions for PU_PD_INPUT_CTRL4 */ 2058 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2050 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 2059 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
2051 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 2060 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2052 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 2061 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
2053 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 2062 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2054 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 2063 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
2055 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 2064 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2056 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 2065 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
2057 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 2066 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2058 2067
2059 /* Bit definitions for PRIMARY_SECONDARY_PAD3 2068 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2060 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 2069 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
2061 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_S 2070 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2062 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 2071 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
2063 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_S 2072 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2064 2073
2065 /* Registers for function LED_PWM */ 2074 /* Registers for function LED_PWM */
2066 #define PALMAS_LED_PERIOD_CTRL 2075 #define PALMAS_LED_PERIOD_CTRL 0x00
2067 #define PALMAS_LED_CTRL 2076 #define PALMAS_LED_CTRL 0x01
2068 #define PALMAS_PWM_CTRL1 2077 #define PALMAS_PWM_CTRL1 0x02
2069 #define PALMAS_PWM_CTRL2 2078 #define PALMAS_PWM_CTRL2 0x03
2070 2079
2071 /* Bit definitions for LED_PERIOD_CTRL */ 2080 /* Bit definitions for LED_PERIOD_CTRL */
2072 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_M 2081 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
2073 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_S 2082 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2074 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_M 2083 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
2075 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_S 2084 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2076 2085
2077 /* Bit definitions for LED_CTRL */ 2086 /* Bit definitions for LED_CTRL */
2078 #define PALMAS_LED_CTRL_LED_2_SEQ 2087 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
2079 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 2088 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2080 #define PALMAS_LED_CTRL_LED_1_SEQ 2089 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
2081 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 2090 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2082 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 2091 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
2083 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2092 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2084 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 2093 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
2085 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 2094 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2086 2095
2087 /* Bit definitions for PWM_CTRL1 */ 2096 /* Bit definitions for PWM_CTRL1 */
2088 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 2097 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
2089 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 2098 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2090 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 2099 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
2091 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 2100 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2092 2101
2093 /* Bit definitions for PWM_CTRL2 */ 2102 /* Bit definitions for PWM_CTRL2 */
2094 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 2103 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2095 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 2104 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2096 2105
2097 /* Registers for function INTERRUPT */ 2106 /* Registers for function INTERRUPT */
2098 #define PALMAS_INT1_STATUS 2107 #define PALMAS_INT1_STATUS 0x00
2099 #define PALMAS_INT1_MASK 2108 #define PALMAS_INT1_MASK 0x01
2100 #define PALMAS_INT1_LINE_STATE 2109 #define PALMAS_INT1_LINE_STATE 0x02
2101 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 2110 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2102 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 2111 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2103 #define PALMAS_INT2_STATUS 2112 #define PALMAS_INT2_STATUS 0x05
2104 #define PALMAS_INT2_MASK 2113 #define PALMAS_INT2_MASK 0x06
2105 #define PALMAS_INT2_LINE_STATE 2114 #define PALMAS_INT2_LINE_STATE 0x07
2106 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 2115 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2107 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 2116 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2108 #define PALMAS_INT3_STATUS 2117 #define PALMAS_INT3_STATUS 0x0A
2109 #define PALMAS_INT3_MASK 2118 #define PALMAS_INT3_MASK 0x0B
2110 #define PALMAS_INT3_LINE_STATE 2119 #define PALMAS_INT3_LINE_STATE 0x0C
2111 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 2120 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2112 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 2121 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2113 #define PALMAS_INT4_STATUS 2122 #define PALMAS_INT4_STATUS 0x0F
2114 #define PALMAS_INT4_MASK 2123 #define PALMAS_INT4_MASK 0x10
2115 #define PALMAS_INT4_LINE_STATE 2124 #define PALMAS_INT4_LINE_STATE 0x11
2116 #define PALMAS_INT4_EDGE_DETECT1 2125 #define PALMAS_INT4_EDGE_DETECT1 0x12
2117 #define PALMAS_INT4_EDGE_DETECT2 2126 #define PALMAS_INT4_EDGE_DETECT2 0x13
2118 #define PALMAS_INT_CTRL 2127 #define PALMAS_INT_CTRL 0x14
2119 2128
2120 /* Bit definitions for INT1_STATUS */ 2129 /* Bit definitions for INT1_STATUS */
2121 #define PALMAS_INT1_STATUS_VBAT_MON 2130 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
2122 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 2131 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2123 #define PALMAS_INT1_STATUS_VSYS_MON 2132 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
2124 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 2133 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2125 #define PALMAS_INT1_STATUS_HOTDIE 2134 #define PALMAS_INT1_STATUS_HOTDIE 0x20
2126 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 2135 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2127 #define PALMAS_INT1_STATUS_PWRDOWN 2136 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
2128 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 2137 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2129 #define PALMAS_INT1_STATUS_RPWRON 2138 #define PALMAS_INT1_STATUS_RPWRON 0x08
2130 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 2139 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2131 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 2140 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
2132 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHI 2141 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2133 #define PALMAS_INT1_STATUS_PWRON 2142 #define PALMAS_INT1_STATUS_PWRON 0x02
2134 #define PALMAS_INT1_STATUS_PWRON_SHIFT 2143 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2135 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_O 2144 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
2136 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_O 2145 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2137 2146
2138 /* Bit definitions for INT1_MASK */ 2147 /* Bit definitions for INT1_MASK */
2139 #define PALMAS_INT1_MASK_VBAT_MON 2148 #define PALMAS_INT1_MASK_VBAT_MON 0x80
2140 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 2149 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2141 #define PALMAS_INT1_MASK_VSYS_MON 2150 #define PALMAS_INT1_MASK_VSYS_MON 0x40
2142 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 2151 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2143 #define PALMAS_INT1_MASK_HOTDIE 2152 #define PALMAS_INT1_MASK_HOTDIE 0x20
2144 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 2153 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2145 #define PALMAS_INT1_MASK_PWRDOWN 2154 #define PALMAS_INT1_MASK_PWRDOWN 0x10
2146 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 2155 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2147 #define PALMAS_INT1_MASK_RPWRON 2156 #define PALMAS_INT1_MASK_RPWRON 0x08
2148 #define PALMAS_INT1_MASK_RPWRON_SHIFT 2157 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2149 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 2158 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
2150 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2159 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2151 #define PALMAS_INT1_MASK_PWRON 2160 #define PALMAS_INT1_MASK_PWRON 0x02
2152 #define PALMAS_INT1_MASK_PWRON_SHIFT 2161 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2153 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 2162 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2154 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 2163 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2155 2164
2156 /* Bit definitions for INT1_LINE_STATE */ 2165 /* Bit definitions for INT1_LINE_STATE */
2157 #define PALMAS_INT1_LINE_STATE_VBAT_MON 2166 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2158 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 2167 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2159 #define PALMAS_INT1_LINE_STATE_VSYS_MON 2168 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2160 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 2169 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2161 #define PALMAS_INT1_LINE_STATE_HOTDIE 2170 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2162 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 2171 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2163 #define PALMAS_INT1_LINE_STATE_PWRDOWN 2172 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2164 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 2173 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2165 #define PALMAS_INT1_LINE_STATE_RPWRON 2174 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2166 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 2175 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2167 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 2176 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2168 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 2177 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2169 #define PALMAS_INT1_LINE_STATE_PWRON 2178 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
2170 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 2179 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2171 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VB 2180 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2172 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VB 2181 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2173 2182
2174 /* Bit definitions for INT2_STATUS */ 2183 /* Bit definitions for INT2_STATUS */
2175 #define PALMAS_INT2_STATUS_VAC_ACOK 2184 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2176 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 2185 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2177 #define PALMAS_INT2_STATUS_SHORT 2186 #define PALMAS_INT2_STATUS_SHORT 0x40
2178 #define PALMAS_INT2_STATUS_SHORT_SHIFT 2187 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2179 #define PALMAS_INT2_STATUS_FBI_BB 2188 #define PALMAS_INT2_STATUS_FBI_BB 0x20
2180 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 2189 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2181 #define PALMAS_INT2_STATUS_RESET_IN 2190 #define PALMAS_INT2_STATUS_RESET_IN 0x10
2182 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 2191 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2183 #define PALMAS_INT2_STATUS_BATREMOVAL 2192 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2184 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 2193 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2185 #define PALMAS_INT2_STATUS_WDT 2194 #define PALMAS_INT2_STATUS_WDT 0x04
2186 #define PALMAS_INT2_STATUS_WDT_SHIFT 2195 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2187 #define PALMAS_INT2_STATUS_RTC_TIMER 2196 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2188 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 2197 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2189 #define PALMAS_INT2_STATUS_RTC_ALARM 2198 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2190 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 2199 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2191 2200
2192 /* Bit definitions for INT2_MASK */ 2201 /* Bit definitions for INT2_MASK */
2193 #define PALMAS_INT2_MASK_VAC_ACOK 2202 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
2194 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 2203 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2195 #define PALMAS_INT2_MASK_SHORT 2204 #define PALMAS_INT2_MASK_SHORT 0x40
2196 #define PALMAS_INT2_MASK_SHORT_SHIFT 2205 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2197 #define PALMAS_INT2_MASK_FBI_BB 2206 #define PALMAS_INT2_MASK_FBI_BB 0x20
2198 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 2207 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2199 #define PALMAS_INT2_MASK_RESET_IN 2208 #define PALMAS_INT2_MASK_RESET_IN 0x10
2200 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 2209 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2201 #define PALMAS_INT2_MASK_BATREMOVAL 2210 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
2202 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 2211 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2203 #define PALMAS_INT2_MASK_WDT 2212 #define PALMAS_INT2_MASK_WDT 0x04
2204 #define PALMAS_INT2_MASK_WDT_SHIFT 2213 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2205 #define PALMAS_INT2_MASK_RTC_TIMER 2214 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
2206 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 2215 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2207 #define PALMAS_INT2_MASK_RTC_ALARM 2216 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
2208 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 2217 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2209 2218
2210 /* Bit definitions for INT2_LINE_STATE */ 2219 /* Bit definitions for INT2_LINE_STATE */
2211 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 2220 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2212 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 2221 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2213 #define PALMAS_INT2_LINE_STATE_SHORT 2222 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
2214 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 2223 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2215 #define PALMAS_INT2_LINE_STATE_FBI_BB 2224 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2216 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 2225 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2217 #define PALMAS_INT2_LINE_STATE_RESET_IN 2226 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2218 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 2227 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2219 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 2228 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2220 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHI 2229 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2221 #define PALMAS_INT2_LINE_STATE_WDT 2230 #define PALMAS_INT2_LINE_STATE_WDT 0x04
2222 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2231 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2223 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 2232 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2224 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIF 2233 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2225 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 2234 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2226 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIF 2235 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2227 2236
2228 /* Bit definitions for INT3_STATUS */ 2237 /* Bit definitions for INT3_STATUS */
2229 #define PALMAS_INT3_STATUS_VBUS 2238 #define PALMAS_INT3_STATUS_VBUS 0x80
2230 #define PALMAS_INT3_STATUS_VBUS_SHIFT 2239 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2231 #define PALMAS_INT3_STATUS_VBUS_OTG 2240 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2232 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 2241 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2233 #define PALMAS_INT3_STATUS_ID 2242 #define PALMAS_INT3_STATUS_ID 0x20
2234 #define PALMAS_INT3_STATUS_ID_SHIFT 2243 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2235 #define PALMAS_INT3_STATUS_ID_OTG 2244 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2236 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 2245 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2237 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 2246 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2238 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 2247 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2239 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 2248 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2240 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2249 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2241 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 2250 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2242 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 2251 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2243 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 2252 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2244 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 2253 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2245 2254
2246 /* Bit definitions for INT3_MASK */ 2255 /* Bit definitions for INT3_MASK */
2247 #define PALMAS_INT3_MASK_VBUS 2256 #define PALMAS_INT3_MASK_VBUS 0x80
2248 #define PALMAS_INT3_MASK_VBUS_SHIFT 2257 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2249 #define PALMAS_INT3_MASK_VBUS_OTG 2258 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2250 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 2259 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2251 #define PALMAS_INT3_MASK_ID 2260 #define PALMAS_INT3_MASK_ID 0x20
2252 #define PALMAS_INT3_MASK_ID_SHIFT 2261 #define PALMAS_INT3_MASK_ID_SHIFT 0x05
2253 #define PALMAS_INT3_MASK_ID_OTG 2262 #define PALMAS_INT3_MASK_ID_OTG 0x10
2254 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 2263 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2255 #define PALMAS_INT3_MASK_GPADC_EOC_RT 2264 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2256 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 2265 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2257 #define PALMAS_INT3_MASK_GPADC_EOC_SW 2266 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2258 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2267 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2259 #define PALMAS_INT3_MASK_GPADC_AUTO_1 2268 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2260 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 2269 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2261 #define PALMAS_INT3_MASK_GPADC_AUTO_0 2270 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2262 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 2271 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2263 2272
2264 /* Bit definitions for INT3_LINE_STATE */ 2273 /* Bit definitions for INT3_LINE_STATE */
2265 #define PALMAS_INT3_LINE_STATE_VBUS 2274 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2266 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 2275 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2267 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 2276 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2268 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 2277 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2269 #define PALMAS_INT3_LINE_STATE_ID 2278 #define PALMAS_INT3_LINE_STATE_ID 0x20
2270 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 2279 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2271 #define PALMAS_INT3_LINE_STATE_ID_OTG 2280 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2272 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 2281 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2273 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 2282 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2274 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_S 2283 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2275 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 2284 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2276 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_S 2285 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2277 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 2286 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2278 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_S 2287 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2279 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 2288 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2280 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_S 2289 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2281 2290
2282 /* Bit definitions for INT4_STATUS */ 2291 /* Bit definitions for INT4_STATUS */
2283 #define PALMAS_INT4_STATUS_GPIO_7 2292 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2284 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 2293 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2285 #define PALMAS_INT4_STATUS_GPIO_6 2294 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2286 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 2295 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2287 #define PALMAS_INT4_STATUS_GPIO_5 2296 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2288 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 2297 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2289 #define PALMAS_INT4_STATUS_GPIO_4 2298 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2290 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 2299 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2291 #define PALMAS_INT4_STATUS_GPIO_3 2300 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2292 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 2301 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2293 #define PALMAS_INT4_STATUS_GPIO_2 2302 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2294 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2303 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2295 #define PALMAS_INT4_STATUS_GPIO_1 2304 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2296 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 2305 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2297 #define PALMAS_INT4_STATUS_GPIO_0 2306 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2298 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 2307 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2299 2308
2300 /* Bit definitions for INT4_MASK */ 2309 /* Bit definitions for INT4_MASK */
2301 #define PALMAS_INT4_MASK_GPIO_7 2310 #define PALMAS_INT4_MASK_GPIO_7 0x80
2302 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 2311 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2303 #define PALMAS_INT4_MASK_GPIO_6 2312 #define PALMAS_INT4_MASK_GPIO_6 0x40
2304 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 2313 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2305 #define PALMAS_INT4_MASK_GPIO_5 2314 #define PALMAS_INT4_MASK_GPIO_5 0x20
2306 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 2315 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2307 #define PALMAS_INT4_MASK_GPIO_4 2316 #define PALMAS_INT4_MASK_GPIO_4 0x10
2308 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 2317 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2309 #define PALMAS_INT4_MASK_GPIO_3 2318 #define PALMAS_INT4_MASK_GPIO_3 0x08
2310 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 2319 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2311 #define PALMAS_INT4_MASK_GPIO_2 2320 #define PALMAS_INT4_MASK_GPIO_2 0x04
2312 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 2321 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2313 #define PALMAS_INT4_MASK_GPIO_1 2322 #define PALMAS_INT4_MASK_GPIO_1 0x02
2314 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 2323 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2315 #define PALMAS_INT4_MASK_GPIO_0 2324 #define PALMAS_INT4_MASK_GPIO_0 0x01
2316 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 2325 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2317 2326
2318 /* Bit definitions for INT4_LINE_STATE */ 2327 /* Bit definitions for INT4_LINE_STATE */
2319 #define PALMAS_INT4_LINE_STATE_GPIO_7 2328 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2320 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 2329 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2321 #define PALMAS_INT4_LINE_STATE_GPIO_6 2330 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2322 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 2331 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2323 #define PALMAS_INT4_LINE_STATE_GPIO_5 2332 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2324 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 2333 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2325 #define PALMAS_INT4_LINE_STATE_GPIO_4 2334 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2326 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 2335 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2327 #define PALMAS_INT4_LINE_STATE_GPIO_3 2336 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2328 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 2337 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2329 #define PALMAS_INT4_LINE_STATE_GPIO_2 2338 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2330 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2339 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2331 #define PALMAS_INT4_LINE_STATE_GPIO_1 2340 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2332 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 2341 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2333 #define PALMAS_INT4_LINE_STATE_GPIO_0 2342 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2334 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 2343 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2335 2344
2336 /* Bit definitions for INT4_EDGE_DETECT1 */ 2345 /* Bit definitions for INT4_EDGE_DETECT1 */
2337 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISIN 2346 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2338 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISIN 2347 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2339 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLI 2348 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2340 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLI 2349 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2341 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISIN 2350 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2342 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISIN 2351 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2343 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLI 2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2344 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLI 2353 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2345 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISIN 2354 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2346 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISIN 2355 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2347 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLI 2356 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2348 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLI 2357 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2349 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISIN 2358 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2350 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISIN 2359 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2351 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLI 2360 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2352 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLI 2361 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2353 2362
2354 /* Bit definitions for INT4_EDGE_DETECT2 */ 2363 /* Bit definitions for INT4_EDGE_DETECT2 */
2355 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISIN 2364 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2356 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISIN 2365 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2357 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLI 2366 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2358 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLI 2367 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2359 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISIN 2368 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2360 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISIN 2369 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2361 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLI 2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2362 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLI 2371 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2363 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISIN 2372 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2364 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISIN 2373 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2365 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLI 2374 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2366 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLI 2375 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2367 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISIN 2376 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2368 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISIN 2377 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2369 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLI 2378 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2370 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLI 2379 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2371 2380
2372 /* Bit definitions for INT_CTRL */ 2381 /* Bit definitions for INT_CTRL */
2373 #define PALMAS_INT_CTRL_INT_PENDING 2382 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2374 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2383 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2375 #define PALMAS_INT_CTRL_INT_CLEAR 2384 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2376 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 2385 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2377 2386
2378 /* Registers for function USB_OTG */ 2387 /* Registers for function USB_OTG */
2379 #define PALMAS_USB_WAKEUP 2388 #define PALMAS_USB_WAKEUP 0x03
2380 #define PALMAS_USB_VBUS_CTRL_SET 2389 #define PALMAS_USB_VBUS_CTRL_SET 0x04
2381 #define PALMAS_USB_VBUS_CTRL_CLR 2390 #define PALMAS_USB_VBUS_CTRL_CLR 0x05
2382 #define PALMAS_USB_ID_CTRL_SET 2391 #define PALMAS_USB_ID_CTRL_SET 0x06
2383 #define PALMAS_USB_ID_CTRL_CLEAR 2392 #define PALMAS_USB_ID_CTRL_CLEAR 0x07
2384 #define PALMAS_USB_VBUS_INT_SRC 2393 #define PALMAS_USB_VBUS_INT_SRC 0x08
2385 #define PALMAS_USB_VBUS_INT_LATCH_SET 2394 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2386 #define PALMAS_USB_VBUS_INT_LATCH_CLR 2395 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2387 #define PALMAS_USB_VBUS_INT_EN_LO_SET 2396 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2388 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 2397 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2389 #define PALMAS_USB_VBUS_INT_EN_HI_SET 2398 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2390 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 2399 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2391 #define PALMAS_USB_ID_INT_SRC 2400 #define PALMAS_USB_ID_INT_SRC 0x0F
2392 #define PALMAS_USB_ID_INT_LATCH_SET 2401 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2393 #define PALMAS_USB_ID_INT_LATCH_CLR 2402 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2394 #define PALMAS_USB_ID_INT_EN_LO_SET 2403 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2395 #define PALMAS_USB_ID_INT_EN_LO_CLR 2404 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2396 #define PALMAS_USB_ID_INT_EN_HI_SET 2405 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2397 #define PALMAS_USB_ID_INT_EN_HI_CLR 2406 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2398 #define PALMAS_USB_OTG_ADP_CTRL 2407 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2399 #define PALMAS_USB_OTG_ADP_HIGH 2408 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2400 #define PALMAS_USB_OTG_ADP_LOW 2409 #define PALMAS_USB_OTG_ADP_LOW 0x18
2401 #define PALMAS_USB_OTG_ADP_RISE 2410 #define PALMAS_USB_OTG_ADP_RISE 0x19
2402 #define PALMAS_USB_OTG_REVISION 2411 #define PALMAS_USB_OTG_REVISION 0x1A
2403 2412
2404 /* Bit definitions for USB_WAKEUP */ 2413 /* Bit definitions for USB_WAKEUP */
2405 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 2414 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2406 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 2415 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2407 2416
2408 /* Bit definitions for USB_VBUS_CTRL_SET */ 2417 /* Bit definitions for USB_VBUS_CTRL_SET */
2409 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VS 2418 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2410 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VS 2419 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2411 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 2420 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2412 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 2421 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2413 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SR 2422 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2414 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SR 2423 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2415 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SI 2424 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2416 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SI 2425 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2417 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COM 2426 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2418 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COM 2427 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2419 2428
2420 /* Bit definitions for USB_VBUS_CTRL_CLR */ 2429 /* Bit definitions for USB_VBUS_CTRL_CLR */
2421 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VS 2430 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2422 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VS 2431 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2423 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 2432 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2424 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 2433 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2425 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SR 2434 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2426 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SR 2435 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2427 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SI 2436 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2428 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SI 2437 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2429 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COM 2438 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2430 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COM 2439 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2431 2440
2432 /* Bit definitions for USB_ID_CTRL_SET */ 2441 /* Bit definitions for USB_ID_CTRL_SET */
2433 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 2442 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2434 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHI 2443 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2435 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 2444 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2436 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHI 2445 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2437 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 2446 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2438 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHI 2447 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2439 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 2448 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2440 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHI 2449 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2441 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 2450 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2442 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIF 2451 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2443 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 2452 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2444 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SH 2453 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2445 2454
2446 /* Bit definitions for USB_ID_CTRL_CLEAR */ 2455 /* Bit definitions for USB_ID_CTRL_CLEAR */
2447 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 2456 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2448 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_S 2457 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2449 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 2458 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2450 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_S 2459 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2451 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 2460 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2452 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_S 2461 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2453 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 2462 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2454 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_S 2463 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2455 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 2464 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2456 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SH 2465 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2457 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 2466 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2458 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_ 2467 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2459 2468
2460 /* Bit definitions for USB_VBUS_INT_SRC */ 2469 /* Bit definitions for USB_VBUS_INT_SRC */
2461 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 2470 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2462 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 2471 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2463 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 2472 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2464 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIF 2473 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2465 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 2474 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2466 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIF 2475 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2467 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 2476 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2468 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_S 2477 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2469 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 2478 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2470 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_S 2479 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2471 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 2480 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2472 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_S 2481 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2473 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 2482 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2474 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_S 2483 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2475 2484
2476 /* Bit definitions for USB_VBUS_INT_LATCH_SET 2485 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2477 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SE 2486 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2478 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SE 2487 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2479 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PR 2488 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2480 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PR 2489 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2481 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SN 2490 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2482 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SN 2491 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2483 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2484 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHI 2493 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2485 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS 2494 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2486 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS 2495 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2487 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS 2496 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2488 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS 2497 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2489 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS 2498 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2490 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS 2499 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2491 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS 2500 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2492 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS 2501 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2493 2502
2494 /* Bit definitions for USB_VBUS_INT_LATCH_CLR 2503 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2495 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SE 2504 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2496 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SE 2505 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2497 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PR 2506 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2498 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PR 2507 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2499 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SN 2508 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2500 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SN 2509 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2501 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2502 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHI 2511 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2503 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS 2512 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2504 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS 2513 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2505 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS 2514 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2506 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS 2515 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2507 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS 2516 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2508 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS 2517 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2509 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS 2518 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2510 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS 2519 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2511 2520
2512 /* Bit definitions for USB_VBUS_INT_EN_LO_SET 2521 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2513 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SE 2522 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2514 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SE 2523 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2515 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PR 2524 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2516 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PR 2525 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2517 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SN 2526 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2518 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SN 2527 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2519 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS 2528 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2520 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS 2529 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2521 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS 2530 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2522 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS 2531 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2523 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS 2532 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2524 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS 2533 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2525 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS 2534 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2526 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS 2535 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2527 2536
2528 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR 2537 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2529 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SE 2538 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2530 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SE 2539 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2531 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PR 2540 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2532 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PR 2541 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2533 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SN 2542 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2534 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SN 2543 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2535 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS 2544 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2536 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS 2545 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2537 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS 2546 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2538 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS 2547 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2539 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS 2548 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2540 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS 2549 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2541 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS 2550 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2542 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS 2551 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2543 2552
2544 /* Bit definitions for USB_VBUS_INT_EN_HI_SET 2553 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2545 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SE 2554 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2546 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SE 2555 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2547 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PR 2556 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2548 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PR 2557 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2549 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SN 2558 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2550 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SN 2559 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2551 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2552 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHI 2561 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2553 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS 2562 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2554 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS 2563 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2555 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS 2564 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2556 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS 2565 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2557 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS 2566 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2558 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS 2567 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2559 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS 2568 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2560 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS 2569 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2561 2570
2562 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR 2571 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2563 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SE 2572 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2564 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SE 2573 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2565 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PR 2574 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2566 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PR 2575 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2567 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SN 2576 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2568 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SN 2577 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2569 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2570 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHI 2579 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2571 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS 2580 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2572 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS 2581 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2573 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS 2582 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2574 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS 2583 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2575 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS 2584 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2576 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS 2585 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2577 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS 2586 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2578 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS 2587 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2579 2588
2580 /* Bit definitions for USB_ID_INT_SRC */ 2589 /* Bit definitions for USB_ID_INT_SRC */
2581 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 2590 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2582 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 2591 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2583 #define PALMAS_USB_ID_INT_SRC_ID_A 2592 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2584 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 2593 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2585 #define PALMAS_USB_ID_INT_SRC_ID_B 2594 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2586 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2595 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2587 #define PALMAS_USB_ID_INT_SRC_ID_C 2596 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2588 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 2597 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2589 #define PALMAS_USB_ID_INT_SRC_ID_GND 2598 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2590 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 2599 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2591 2600
2592 /* Bit definitions for USB_ID_INT_LATCH_SET * 2601 /* Bit definitions for USB_ID_INT_LATCH_SET */
2593 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 2602 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2594 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_ 2603 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2595 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 2604 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2596 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIF 2605 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2597 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 2606 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2598 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIF 2607 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2599 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 2608 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2600 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIF 2609 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2601 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 2610 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2602 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SH 2611 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2603 2612
2604 /* Bit definitions for USB_ID_INT_LATCH_CLR * 2613 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2605 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 2614 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2606 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_ 2615 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2607 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 2616 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2608 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIF 2617 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2609 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 2618 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2610 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIF 2619 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2611 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 2620 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2612 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIF 2621 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2613 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 2622 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2614 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SH 2623 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2615 2624
2616 /* Bit definitions for USB_ID_INT_EN_LO_SET * 2625 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2617 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 2626 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2618 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_ 2627 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2619 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 2628 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2620 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIF 2629 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2621 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 2630 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2622 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIF 2631 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2623 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 2632 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2624 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIF 2633 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2625 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 2634 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2626 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SH 2635 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2627 2636
2628 /* Bit definitions for USB_ID_INT_EN_LO_CLR * 2637 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2629 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 2638 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2630 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_ 2639 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2631 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 2640 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2632 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIF 2641 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2633 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 2642 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2634 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIF 2643 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2635 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 2644 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2636 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIF 2645 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2637 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 2646 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2638 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SH 2647 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2639 2648
2640 /* Bit definitions for USB_ID_INT_EN_HI_SET * 2649 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2641 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 2650 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2642 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_ 2651 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2643 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 2652 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2644 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIF 2653 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2645 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 2654 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2646 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIF 2655 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2647 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 2656 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2648 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIF 2657 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2649 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 2658 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2650 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SH 2659 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2651 2660
2652 /* Bit definitions for USB_ID_INT_EN_HI_CLR * 2661 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2653 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 2662 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2654 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_ 2663 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2655 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 2664 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2656 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIF 2665 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2657 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 2666 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2658 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIF 2667 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2659 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 2668 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2660 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIF 2669 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2661 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 2670 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2662 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SH 2671 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2663 2672
2664 /* Bit definitions for USB_OTG_ADP_CTRL */ 2673 /* Bit definitions for USB_OTG_ADP_CTRL */
2665 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 2674 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2666 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2675 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2667 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 2676 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2668 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIF 2677 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2669 2678
2670 /* Bit definitions for USB_OTG_ADP_HIGH */ 2679 /* Bit definitions for USB_OTG_ADP_HIGH */
2671 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MA 2680 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2672 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SH 2681 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2673 2682
2674 /* Bit definitions for USB_OTG_ADP_LOW */ 2683 /* Bit definitions for USB_OTG_ADP_LOW */
2675 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 2684 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2676 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIF 2685 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2677 2686
2678 /* Bit definitions for USB_OTG_ADP_RISE */ 2687 /* Bit definitions for USB_OTG_ADP_RISE */
2679 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MA 2688 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2680 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SH 2689 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2681 2690
2682 /* Bit definitions for USB_OTG_REVISION */ 2691 /* Bit definitions for USB_OTG_REVISION */
2683 #define PALMAS_USB_OTG_REVISION_OTG_REV 2692 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2684 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 2693 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2685 2694
2686 /* Registers for function VIBRATOR */ 2695 /* Registers for function VIBRATOR */
2687 #define PALMAS_VIBRA_CTRL 2696 #define PALMAS_VIBRA_CTRL 0x00
2688 2697
2689 /* Bit definitions for VIBRA_CTRL */ 2698 /* Bit definitions for VIBRA_CTRL */
2690 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 2699 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2691 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 2700 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2692 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 2701 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2693 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 2702 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2694 2703
2695 /* Registers for function GPIO */ 2704 /* Registers for function GPIO */
2696 #define PALMAS_GPIO_DATA_IN 2705 #define PALMAS_GPIO_DATA_IN 0x00
2697 #define PALMAS_GPIO_DATA_DIR 2706 #define PALMAS_GPIO_DATA_DIR 0x01
2698 #define PALMAS_GPIO_DATA_OUT 2707 #define PALMAS_GPIO_DATA_OUT 0x02
2699 #define PALMAS_GPIO_DEBOUNCE_EN 2708 #define PALMAS_GPIO_DEBOUNCE_EN 0x03
2700 #define PALMAS_GPIO_CLEAR_DATA_OUT 2709 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2701 #define PALMAS_GPIO_SET_DATA_OUT 2710 #define PALMAS_GPIO_SET_DATA_OUT 0x05
2702 #define PALMAS_PU_PD_GPIO_CTRL1 2711 #define PALMAS_PU_PD_GPIO_CTRL1 0x06
2703 #define PALMAS_PU_PD_GPIO_CTRL2 2712 #define PALMAS_PU_PD_GPIO_CTRL2 0x07
2704 #define PALMAS_OD_OUTPUT_GPIO_CTRL 2713 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2705 #define PALMAS_GPIO_DATA_IN2 2714 #define PALMAS_GPIO_DATA_IN2 0x09
2706 #define PALMAS_GPIO_DATA_DIR2 2715 #define PALMAS_GPIO_DATA_DIR2 0x0A
2707 #define PALMAS_GPIO_DATA_OUT2 2716 #define PALMAS_GPIO_DATA_OUT2 0x0B
2708 #define PALMAS_GPIO_DEBOUNCE_EN2 2717 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2709 #define PALMAS_GPIO_CLEAR_DATA_OUT2 2718 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2710 #define PALMAS_GPIO_SET_DATA_OUT2 2719 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2711 #define PALMAS_PU_PD_GPIO_CTRL3 2720 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2712 #define PALMAS_PU_PD_GPIO_CTRL4 2721 #define PALMAS_PU_PD_GPIO_CTRL4 0x10
2713 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 2722 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2714 2723
2715 /* Bit definitions for GPIO_DATA_IN */ 2724 /* Bit definitions for GPIO_DATA_IN */
2716 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 2725 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2717 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 2726 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2718 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 2727 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2719 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 2728 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2720 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 2729 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2721 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 2730 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2722 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 2731 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2723 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 2732 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2724 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 2733 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2725 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 2734 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2726 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 2735 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2727 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2736 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2728 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 2737 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2729 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 2738 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2730 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 2739 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2731 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 2740 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2732 2741
2733 /* Bit definitions for GPIO_DATA_DIR */ 2742 /* Bit definitions for GPIO_DATA_DIR */
2734 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 2743 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2735 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 2744 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2736 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 2745 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2737 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 2746 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2738 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 2747 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2739 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 2748 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2740 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 2749 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2741 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 2750 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2742 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 2751 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2743 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 2752 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2744 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 2753 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2745 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2754 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2746 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 2755 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2747 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 2756 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2748 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 2757 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2749 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 2758 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2750 2759
2751 /* Bit definitions for GPIO_DATA_OUT */ 2760 /* Bit definitions for GPIO_DATA_OUT */
2752 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 2761 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2753 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 2762 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2754 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 2763 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2755 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 2764 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2756 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 2765 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2757 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 2766 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2758 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 2767 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2759 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 2768 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2760 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 2769 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2761 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 2770 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2762 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 2771 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2763 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2772 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2764 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 2773 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2765 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 2774 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2766 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 2775 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2767 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 2776 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2768 2777
2769 /* Bit definitions for GPIO_DEBOUNCE_EN */ 2778 /* Bit definitions for GPIO_DEBOUNCE_EN */
2770 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUN 2779 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2771 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUN 2780 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2772 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUN 2781 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2773 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUN 2782 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2774 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUN 2783 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2775 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUN 2784 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2776 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUN 2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2777 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUN 2786 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2778 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUN 2787 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2779 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUN 2788 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2780 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUN 2789 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2781 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUN 2790 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2782 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUN 2791 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2783 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUN 2792 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2784 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUN 2793 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2785 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUN 2794 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2786 2795
2787 /* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2796 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2788 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLE 2797 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2789 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLE 2798 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2790 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLE 2799 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2791 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLE 2800 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2792 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLE 2801 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2793 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLE 2802 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2794 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLE 2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2795 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLE 2804 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2796 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLE 2805 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2797 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLE 2806 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2798 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLE 2807 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2799 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLE 2808 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2800 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLE 2809 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2801 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLE 2810 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2802 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLE 2811 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2803 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLE 2812 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2804 2813
2805 /* Bit definitions for GPIO_SET_DATA_OUT */ 2814 /* Bit definitions for GPIO_SET_DATA_OUT */
2806 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_D 2815 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2807 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_D 2816 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2808 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_D 2817 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2809 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_D 2818 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2810 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_D 2819 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2811 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_D 2820 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2812 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_D 2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2813 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_D 2822 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2814 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_D 2823 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2815 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_D 2824 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2816 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_D 2825 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2817 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_D 2826 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2818 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_D 2827 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2819 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_D 2828 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2820 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_D 2829 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2821 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_D 2830 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2822 2831
2823 /* Bit definitions for PU_PD_GPIO_CTRL1 */ 2832 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2824 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 2833 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2825 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHI 2834 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2826 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 2835 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2827 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHI 2836 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2828 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 2837 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2829 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHI 2838 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2830 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 2839 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2831 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHI 2840 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2832 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 2841 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2833 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHI 2842 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2834 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 2843 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2835 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHI 2844 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2836 2845
2837 /* Bit definitions for PU_PD_GPIO_CTRL2 */ 2846 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2838 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 2847 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2839 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHI 2848 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2840 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 2849 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2841 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHI 2850 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2842 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 2851 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2843 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHI 2852 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2844 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 2853 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2845 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHI 2854 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2846 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 2855 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2847 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHI 2856 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2848 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 2857 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2849 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHI 2858 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2850 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 2859 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2851 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHI 2860 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2852 2861
2853 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2862 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2854 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 2863 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2855 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_ 2864 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2856 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 2865 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2857 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_ 2866 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2858 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 2867 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2859 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_ 2868 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2860 2869
2861 /* Registers for function GPADC */ 2870 /* Registers for function GPADC */
2862 #define PALMAS_GPADC_CTRL1 2871 #define PALMAS_GPADC_CTRL1 0x00
2863 #define PALMAS_GPADC_CTRL2 2872 #define PALMAS_GPADC_CTRL2 0x01
2864 #define PALMAS_GPADC_RT_CTRL 2873 #define PALMAS_GPADC_RT_CTRL 0x02
2865 #define PALMAS_GPADC_AUTO_CTRL 2874 #define PALMAS_GPADC_AUTO_CTRL 0x03
2866 #define PALMAS_GPADC_STATUS 2875 #define PALMAS_GPADC_STATUS 0x04
2867 #define PALMAS_GPADC_RT_SELECT 2876 #define PALMAS_GPADC_RT_SELECT 0x05
2868 #define PALMAS_GPADC_RT_CONV0_LSB 2877 #define PALMAS_GPADC_RT_CONV0_LSB 0x06
2869 #define PALMAS_GPADC_RT_CONV0_MSB 2878 #define PALMAS_GPADC_RT_CONV0_MSB 0x07
2870 #define PALMAS_GPADC_AUTO_SELECT 2879 #define PALMAS_GPADC_AUTO_SELECT 0x08
2871 #define PALMAS_GPADC_AUTO_CONV0_LSB 2880 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2872 #define PALMAS_GPADC_AUTO_CONV0_MSB 2881 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2873 #define PALMAS_GPADC_AUTO_CONV1_LSB 2882 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2874 #define PALMAS_GPADC_AUTO_CONV1_MSB 2883 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2875 #define PALMAS_GPADC_SW_SELECT 2884 #define PALMAS_GPADC_SW_SELECT 0x0D
2876 #define PALMAS_GPADC_SW_CONV0_LSB 2885 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2877 #define PALMAS_GPADC_SW_CONV0_MSB 2886 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2878 #define PALMAS_GPADC_THRES_CONV0_LSB 2887 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2879 #define PALMAS_GPADC_THRES_CONV0_MSB 2888 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2880 #define PALMAS_GPADC_THRES_CONV1_LSB 2889 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2881 #define PALMAS_GPADC_THRES_CONV1_MSB 2890 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2882 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 2891 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2883 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 2892 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2884 2893
2885 /* Bit definitions for GPADC_CTRL1 */ 2894 /* Bit definitions for GPADC_CTRL1 */
2886 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 2895 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2887 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 2896 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2888 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MA 2897 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2889 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SH 2898 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2890 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MA 2899 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2891 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SH 2900 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2892 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 2901 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2893 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SH 2902 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2894 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 2903 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2895 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 2904 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2896 2905
2897 /* Bit definitions for GPADC_CTRL2 */ 2906 /* Bit definitions for GPADC_CTRL2 */
2898 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 2907 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2899 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 2908 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2900 2909
2901 /* Bit definitions for GPADC_RT_CTRL */ 2910 /* Bit definitions for GPADC_RT_CTRL */
2902 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 2911 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2903 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHI 2912 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2904 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 2913 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2905 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_S 2914 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2906 2915
2907 /* Bit definitions for GPADC_AUTO_CTRL */ 2916 /* Bit definitions for GPADC_AUTO_CTRL */
2908 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 2917 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2909 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 2918 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2910 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 2919 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2911 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 2920 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2912 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 2921 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2913 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_ 2922 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2914 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 2923 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2915 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_ 2924 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2916 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_M 2925 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2917 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_S 2926 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2918 2927
2919 /* Bit definitions for GPADC_STATUS */ 2928 /* Bit definitions for GPADC_STATUS */
2920 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 2929 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2921 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_S 2930 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2922 2931
2923 /* Bit definitions for GPADC_RT_SELECT */ 2932 /* Bit definitions for GPADC_RT_SELECT */
2924 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 2933 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2925 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHI 2934 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2926 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_M 2935 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2927 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_S 2936 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2928 2937
2929 /* Bit definitions for GPADC_RT_CONV0_LSB */ 2938 /* Bit definitions for GPADC_RT_CONV0_LSB */
2930 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LS 2939 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2931 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LS 2940 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2932 2941
2933 /* Bit definitions for GPADC_RT_CONV0_MSB */ 2942 /* Bit definitions for GPADC_RT_CONV0_MSB */
2934 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MS 2943 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2935 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MS 2944 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2936 2945
2937 /* Bit definitions for GPADC_AUTO_SELECT */ 2946 /* Bit definitions for GPADC_AUTO_SELECT */
2938 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_S 2947 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2939 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_S 2948 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2940 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_S 2949 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2941 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_S 2950 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2942 2951
2943 /* Bit definitions for GPADC_AUTO_CONV0_LSB * 2952 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2944 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV 2953 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2945 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV 2954 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2946 2955
2947 /* Bit definitions for GPADC_AUTO_CONV0_MSB * 2956 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2948 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV 2957 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2949 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV 2958 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2950 2959
2951 /* Bit definitions for GPADC_AUTO_CONV1_LSB * 2960 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2952 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV 2961 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2953 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV 2962 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2954 2963
2955 /* Bit definitions for GPADC_AUTO_CONV1_MSB * 2964 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2956 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV 2965 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2957 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV 2966 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2958 2967
2959 /* Bit definitions for GPADC_SW_SELECT */ 2968 /* Bit definitions for GPADC_SW_SELECT */
2960 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 2969 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2961 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHI 2970 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2962 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 2971 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2963 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 2972 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2964 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_M 2973 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2965 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_S 2974 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2966 2975
2967 /* Bit definitions for GPADC_SW_CONV0_LSB */ 2976 /* Bit definitions for GPADC_SW_CONV0_LSB */
2968 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LS 2977 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2969 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LS 2978 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2970 2979
2971 /* Bit definitions for GPADC_SW_CONV0_MSB */ 2980 /* Bit definitions for GPADC_SW_CONV0_MSB */
2972 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MS 2981 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2973 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MS 2982 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2974 2983
2975 /* Bit definitions for GPADC_THRES_CONV0_LSB 2984 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2976 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CO 2985 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2977 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CO 2986 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2978 2987
2979 /* Bit definitions for GPADC_THRES_CONV0_MSB 2988 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2980 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CO 2989 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2981 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CO 2990 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2982 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CO 2991 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2983 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CO 2992 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2984 2993
2985 /* Bit definitions for GPADC_THRES_CONV1_LSB 2994 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2986 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CO 2995 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2987 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CO 2996 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2988 2997
2989 /* Bit definitions for GPADC_THRES_CONV1_MSB 2998 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2990 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CO 2999 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2991 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CO 3000 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2992 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CO 3001 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2993 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CO 3002 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2994 3003
2995 /* Bit definitions for GPADC_SMPS_ILMONITOR_E 3004 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2996 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3005 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2997 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3006 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2998 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3007 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2999 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3008 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
3000 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3009 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
3001 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_I 3010 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
3002 3011
3003 /* Bit definitions for GPADC_SMPS_VSEL_MONITO 3012 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3004 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACT 3013 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
3005 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACT 3014 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
3006 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMP 3015 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
3007 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMP 3016 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
3008 3017
3009 /* Registers for function GPADC */ 3018 /* Registers for function GPADC */
3010 #define PALMAS_GPADC_TRIM1 3019 #define PALMAS_GPADC_TRIM1 0x00
3011 #define PALMAS_GPADC_TRIM2 3020 #define PALMAS_GPADC_TRIM2 0x01
3012 #define PALMAS_GPADC_TRIM3 3021 #define PALMAS_GPADC_TRIM3 0x02
3013 #define PALMAS_GPADC_TRIM4 3022 #define PALMAS_GPADC_TRIM4 0x03
3014 #define PALMAS_GPADC_TRIM5 3023 #define PALMAS_GPADC_TRIM5 0x04
3015 #define PALMAS_GPADC_TRIM6 3024 #define PALMAS_GPADC_TRIM6 0x05
3016 #define PALMAS_GPADC_TRIM7 3025 #define PALMAS_GPADC_TRIM7 0x06
3017 #define PALMAS_GPADC_TRIM8 3026 #define PALMAS_GPADC_TRIM8 0x07
3018 #define PALMAS_GPADC_TRIM9 3027 #define PALMAS_GPADC_TRIM9 0x08
3019 #define PALMAS_GPADC_TRIM10 3028 #define PALMAS_GPADC_TRIM10 0x09
3020 #define PALMAS_GPADC_TRIM11 3029 #define PALMAS_GPADC_TRIM11 0x0A
3021 #define PALMAS_GPADC_TRIM12 3030 #define PALMAS_GPADC_TRIM12 0x0B
3022 #define PALMAS_GPADC_TRIM13 3031 #define PALMAS_GPADC_TRIM13 0x0C
3023 #define PALMAS_GPADC_TRIM14 3032 #define PALMAS_GPADC_TRIM14 0x0D
3024 #define PALMAS_GPADC_TRIM15 3033 #define PALMAS_GPADC_TRIM15 0x0E
3025 #define PALMAS_GPADC_TRIM16 3034 #define PALMAS_GPADC_TRIM16 0x0F
3026 3035
3027 /* TPS659038 regen2_ctrl offset iss different 3036 /* TPS659038 regen2_ctrl offset iss different from palmas */
3028 #define TPS659038_REGEN2_CTRL 3037 #define TPS659038_REGEN2_CTRL 0x12
3029 3038
3030 /* TPS65917 Interrupt registers */ 3039 /* TPS65917 Interrupt registers */
3031 3040
3032 /* Registers for function INTERRUPT */ 3041 /* Registers for function INTERRUPT */
3033 #define TPS65917_INT1_STATUS 3042 #define TPS65917_INT1_STATUS 0x00
3034 #define TPS65917_INT1_MASK 3043 #define TPS65917_INT1_MASK 0x01
3035 #define TPS65917_INT1_LINE_STATE 3044 #define TPS65917_INT1_LINE_STATE 0x02
3036 #define TPS65917_INT2_STATUS 3045 #define TPS65917_INT2_STATUS 0x05
3037 #define TPS65917_INT2_MASK 3046 #define TPS65917_INT2_MASK 0x06
3038 #define TPS65917_INT2_LINE_STATE 3047 #define TPS65917_INT2_LINE_STATE 0x07
3039 #define TPS65917_INT3_STATUS 3048 #define TPS65917_INT3_STATUS 0x0A
3040 #define TPS65917_INT3_MASK 3049 #define TPS65917_INT3_MASK 0x0B
3041 #define TPS65917_INT3_LINE_STATE 3050 #define TPS65917_INT3_LINE_STATE 0x0C
3042 #define TPS65917_INT4_STATUS 3051 #define TPS65917_INT4_STATUS 0x0F
3043 #define TPS65917_INT4_MASK 3052 #define TPS65917_INT4_MASK 0x10
3044 #define TPS65917_INT4_LINE_STATE 3053 #define TPS65917_INT4_LINE_STATE 0x11
3045 #define TPS65917_INT4_EDGE_DETECT1 3054 #define TPS65917_INT4_EDGE_DETECT1 0x12
3046 #define TPS65917_INT4_EDGE_DETECT2 3055 #define TPS65917_INT4_EDGE_DETECT2 0x13
3047 #define TPS65917_INT_CTRL 3056 #define TPS65917_INT_CTRL 0x14
3048 3057
3049 /* Bit definitions for INT1_STATUS */ 3058 /* Bit definitions for INT1_STATUS */
3050 #define TPS65917_INT1_STATUS_VSYS_MON 3059 #define TPS65917_INT1_STATUS_VSYS_MON 0x40
3051 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 3060 #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3052 #define TPS65917_INT1_STATUS_HOTDIE 3061 #define TPS65917_INT1_STATUS_HOTDIE 0x20
3053 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 3062 #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3054 #define TPS65917_INT1_STATUS_PWRDOWN 3063 #define TPS65917_INT1_STATUS_PWRDOWN 0x10
3055 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 3064 #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3056 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 3065 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3057 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_S 3066 #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3058 #define TPS65917_INT1_STATUS_PWRON 3067 #define TPS65917_INT1_STATUS_PWRON 0x02
3059 #define TPS65917_INT1_STATUS_PWRON_SHIFT 3068 #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3060 3069
3061 /* Bit definitions for INT1_MASK */ 3070 /* Bit definitions for INT1_MASK */
3062 #define TPS65917_INT1_MASK_VSYS_MON 3071 #define TPS65917_INT1_MASK_VSYS_MON 0x40
3063 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 3072 #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3064 #define TPS65917_INT1_MASK_HOTDIE 3073 #define TPS65917_INT1_MASK_HOTDIE 0x20
3065 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 3074 #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3066 #define TPS65917_INT1_MASK_PWRDOWN 3075 #define TPS65917_INT1_MASK_PWRDOWN 0x10
3067 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 3076 #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3068 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 3077 #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3069 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHI 3078 #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3070 #define TPS65917_INT1_MASK_PWRON 3079 #define TPS65917_INT1_MASK_PWRON 0x02
3071 #define TPS65917_INT1_MASK_PWRON_SHIFT 3080 #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3072 3081
3073 /* Bit definitions for INT1_LINE_STATE */ 3082 /* Bit definitions for INT1_LINE_STATE */
3074 #define TPS65917_INT1_LINE_STATE_VSYS_MON 3083 #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3075 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHI 3084 #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3076 #define TPS65917_INT1_LINE_STATE_HOTDIE 3085 #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3077 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 3086 #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3078 #define TPS65917_INT1_LINE_STATE_PWRDOWN 3087 #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3079 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIF 3088 #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3080 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_K 3089 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3081 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_K 3090 #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3082 #define TPS65917_INT1_LINE_STATE_PWRON 3091 #define TPS65917_INT1_LINE_STATE_PWRON 0x02
3083 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 3092 #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3084 3093
3085 /* Bit definitions for INT2_STATUS */ 3094 /* Bit definitions for INT2_STATUS */
3086 #define TPS65917_INT2_STATUS_SHORT 3095 #define TPS65917_INT2_STATUS_SHORT 0x40
3087 #define TPS65917_INT2_STATUS_SHORT_SHIFT 3096 #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3088 #define TPS65917_INT2_STATUS_FSD 3097 #define TPS65917_INT2_STATUS_FSD 0x20
3089 #define TPS65917_INT2_STATUS_FSD_SHIFT 3098 #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3090 #define TPS65917_INT2_STATUS_RESET_IN 3099 #define TPS65917_INT2_STATUS_RESET_IN 0x10
3091 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 3100 #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3092 #define TPS65917_INT2_STATUS_WDT 3101 #define TPS65917_INT2_STATUS_WDT 0x04
3093 #define TPS65917_INT2_STATUS_WDT_SHIFT 3102 #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3094 #define TPS65917_INT2_STATUS_OTP_ERROR 3103 #define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3095 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 3104 #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3096 3105
3097 /* Bit definitions for INT2_MASK */ 3106 /* Bit definitions for INT2_MASK */
3098 #define TPS65917_INT2_MASK_SHORT 3107 #define TPS65917_INT2_MASK_SHORT 0x40
3099 #define TPS65917_INT2_MASK_SHORT_SHIFT 3108 #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3100 #define TPS65917_INT2_MASK_FSD 3109 #define TPS65917_INT2_MASK_FSD 0x20
3101 #define TPS65917_INT2_MASK_FSD_SHIFT 3110 #define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3102 #define TPS65917_INT2_MASK_RESET_IN 3111 #define TPS65917_INT2_MASK_RESET_IN 0x10
3103 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 3112 #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3104 #define TPS65917_INT2_MASK_WDT 3113 #define TPS65917_INT2_MASK_WDT 0x04
3105 #define TPS65917_INT2_MASK_WDT_SHIFT 3114 #define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3106 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 3115 #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3107 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 3116 #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3108 3117
3109 /* Bit definitions for INT2_LINE_STATE */ 3118 /* Bit definitions for INT2_LINE_STATE */
3110 #define TPS65917_INT2_LINE_STATE_SHORT 3119 #define TPS65917_INT2_LINE_STATE_SHORT 0x40
3111 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 3120 #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3112 #define TPS65917_INT2_LINE_STATE_FSD 3121 #define TPS65917_INT2_LINE_STATE_FSD 0x20
3113 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 3122 #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3114 #define TPS65917_INT2_LINE_STATE_RESET_IN 3123 #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3115 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHI 3124 #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3116 #define TPS65917_INT2_LINE_STATE_WDT 3125 #define TPS65917_INT2_LINE_STATE_WDT 0x04
3117 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 3126 #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3118 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 3127 #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3119 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SH 3128 #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3120 3129
3121 /* Bit definitions for INT3_STATUS */ 3130 /* Bit definitions for INT3_STATUS */
3122 #define TPS65917_INT3_STATUS_VBUS 3131 #define TPS65917_INT3_STATUS_VBUS 0x80
3123 #define TPS65917_INT3_STATUS_VBUS_SHIFT 3132 #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3124 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 3133 #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3125 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHI 3134 #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3126 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 3135 #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3127 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHI 3136 #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3128 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 3137 #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3129 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHI 3138 #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3130 3139
3131 /* Bit definitions for INT3_MASK */ 3140 /* Bit definitions for INT3_MASK */
3132 #define TPS65917_INT3_MASK_VBUS 3141 #define TPS65917_INT3_MASK_VBUS 0x80
3133 #define TPS65917_INT3_MASK_VBUS_SHIFT 3142 #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3134 #define TPS65917_INT3_MASK_GPADC_EOC_SW 3143 #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3135 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 3144 #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3136 #define TPS65917_INT3_MASK_GPADC_AUTO_1 3145 #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3137 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 3146 #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3138 #define TPS65917_INT3_MASK_GPADC_AUTO_0 3147 #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3139 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 3148 #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3140 3149
3141 /* Bit definitions for INT3_LINE_STATE */ 3150 /* Bit definitions for INT3_LINE_STATE */
3142 #define TPS65917_INT3_LINE_STATE_VBUS 3151 #define TPS65917_INT3_LINE_STATE_VBUS 0x80
3143 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 3152 #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3144 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 3153 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3145 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 3154 #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3146 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 3155 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3147 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 3156 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3148 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 3157 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3149 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 3158 #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3150 3159
3151 /* Bit definitions for INT4_STATUS */ 3160 /* Bit definitions for INT4_STATUS */
3152 #define TPS65917_INT4_STATUS_GPIO_6 3161 #define TPS65917_INT4_STATUS_GPIO_6 0x40
3153 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 3162 #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3154 #define TPS65917_INT4_STATUS_GPIO_5 3163 #define TPS65917_INT4_STATUS_GPIO_5 0x20
3155 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 3164 #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3156 #define TPS65917_INT4_STATUS_GPIO_4 3165 #define TPS65917_INT4_STATUS_GPIO_4 0x10
3157 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 3166 #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3158 #define TPS65917_INT4_STATUS_GPIO_3 3167 #define TPS65917_INT4_STATUS_GPIO_3 0x08
3159 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 3168 #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3160 #define TPS65917_INT4_STATUS_GPIO_2 3169 #define TPS65917_INT4_STATUS_GPIO_2 0x04
3161 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 3170 #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3162 #define TPS65917_INT4_STATUS_GPIO_1 3171 #define TPS65917_INT4_STATUS_GPIO_1 0x02
3163 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 3172 #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3164 #define TPS65917_INT4_STATUS_GPIO_0 3173 #define TPS65917_INT4_STATUS_GPIO_0 0x01
3165 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 3174 #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3166 3175
3167 /* Bit definitions for INT4_MASK */ 3176 /* Bit definitions for INT4_MASK */
3168 #define TPS65917_INT4_MASK_GPIO_6 3177 #define TPS65917_INT4_MASK_GPIO_6 0x40
3169 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 3178 #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3170 #define TPS65917_INT4_MASK_GPIO_5 3179 #define TPS65917_INT4_MASK_GPIO_5 0x20
3171 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 3180 #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3172 #define TPS65917_INT4_MASK_GPIO_4 3181 #define TPS65917_INT4_MASK_GPIO_4 0x10
3173 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 3182 #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3174 #define TPS65917_INT4_MASK_GPIO_3 3183 #define TPS65917_INT4_MASK_GPIO_3 0x08
3175 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 3184 #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3176 #define TPS65917_INT4_MASK_GPIO_2 3185 #define TPS65917_INT4_MASK_GPIO_2 0x04
3177 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 3186 #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3178 #define TPS65917_INT4_MASK_GPIO_1 3187 #define TPS65917_INT4_MASK_GPIO_1 0x02
3179 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 3188 #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3180 #define TPS65917_INT4_MASK_GPIO_0 3189 #define TPS65917_INT4_MASK_GPIO_0 0x01
3181 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 3190 #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3182 3191
3183 /* Bit definitions for INT4_LINE_STATE */ 3192 /* Bit definitions for INT4_LINE_STATE */
3184 #define TPS65917_INT4_LINE_STATE_GPIO_6 3193 #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3185 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 3194 #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3186 #define TPS65917_INT4_LINE_STATE_GPIO_5 3195 #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3187 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 3196 #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3188 #define TPS65917_INT4_LINE_STATE_GPIO_4 3197 #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3189 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 3198 #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3190 #define TPS65917_INT4_LINE_STATE_GPIO_3 3199 #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3191 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 3200 #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3192 #define TPS65917_INT4_LINE_STATE_GPIO_2 3201 #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3193 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 3202 #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3194 #define TPS65917_INT4_LINE_STATE_GPIO_1 3203 #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3195 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 3204 #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3196 #define TPS65917_INT4_LINE_STATE_GPIO_0 3205 #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3197 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 3206 #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3198 3207
3199 /* Bit definitions for INT4_EDGE_DETECT1 */ 3208 /* Bit definitions for INT4_EDGE_DETECT1 */
3200 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RIS 3209 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3201 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RIS 3210 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3202 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FAL 3211 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3203 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FAL 3212 #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3204 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RIS 3213 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3205 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RIS 3214 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3206 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FAL 3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3207 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FAL 3216 #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3208 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RIS 3217 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3209 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RIS 3218 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3210 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FAL 3219 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3211 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FAL 3220 #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3212 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RIS 3221 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3213 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RIS 3222 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3214 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FAL 3223 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3215 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FAL 3224 #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3216 3225
3217 /* Bit definitions for INT4_EDGE_DETECT2 */ 3226 /* Bit definitions for INT4_EDGE_DETECT2 */
3218 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RIS 3227 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3219 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RIS 3228 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3220 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FAL 3229 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3221 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FAL 3230 #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3222 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RIS 3231 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3223 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RIS 3232 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3224 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FAL 3233 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3225 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FAL 3234 #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3226 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RIS 3235 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3227 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RIS 3236 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3228 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FAL 3237 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3229 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FAL 3238 #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3230 3239
3231 /* Bit definitions for INT_CTRL */ 3240 /* Bit definitions for INT_CTRL */
3232 #define TPS65917_INT_CTRL_INT_PENDING 3241 #define TPS65917_INT_CTRL_INT_PENDING 0x04
3233 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 3242 #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3234 #define TPS65917_INT_CTRL_INT_CLEAR 3243 #define TPS65917_INT_CTRL_INT_CLEAR 0x01
3235 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 3244 #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3236 3245
3237 /* TPS65917 SMPS Registers */ 3246 /* TPS65917 SMPS Registers */
3238 3247
3239 /* Registers for function SMPS */ 3248 /* Registers for function SMPS */
3240 #define TPS65917_SMPS1_CTRL 3249 #define TPS65917_SMPS1_CTRL 0x00
3241 #define TPS65917_SMPS1_FORCE 3250 #define TPS65917_SMPS1_FORCE 0x02
3242 #define TPS65917_SMPS1_VOLTAGE 3251 #define TPS65917_SMPS1_VOLTAGE 0x03
3243 #define TPS65917_SMPS2_CTRL 3252 #define TPS65917_SMPS2_CTRL 0x04
3244 #define TPS65917_SMPS2_FORCE 3253 #define TPS65917_SMPS2_FORCE 0x06
3245 #define TPS65917_SMPS2_VOLTAGE 3254 #define TPS65917_SMPS2_VOLTAGE 0x07
3246 #define TPS65917_SMPS3_CTRL 3255 #define TPS65917_SMPS3_CTRL 0x0C
3247 #define TPS65917_SMPS3_FORCE 3256 #define TPS65917_SMPS3_FORCE 0x0E
3248 #define TPS65917_SMPS3_VOLTAGE 3257 #define TPS65917_SMPS3_VOLTAGE 0x0F
3249 #define TPS65917_SMPS4_CTRL 3258 #define TPS65917_SMPS4_CTRL 0x10
3250 #define TPS65917_SMPS4_VOLTAGE 3259 #define TPS65917_SMPS4_VOLTAGE 0x13
3251 #define TPS65917_SMPS5_CTRL 3260 #define TPS65917_SMPS5_CTRL 0x18
3252 #define TPS65917_SMPS5_VOLTAGE 3261 #define TPS65917_SMPS5_VOLTAGE 0x1B
3253 #define TPS65917_SMPS_CTRL 3262 #define TPS65917_SMPS_CTRL 0x24
3254 #define TPS65917_SMPS_PD_CTRL 3263 #define TPS65917_SMPS_PD_CTRL 0x25
3255 #define TPS65917_SMPS_THERMAL_EN 3264 #define TPS65917_SMPS_THERMAL_EN 0x27
3256 #define TPS65917_SMPS_THERMAL_STATUS 3265 #define TPS65917_SMPS_THERMAL_STATUS 0x28
3257 #define TPS65917_SMPS_SHORT_STATUS 3266 #define TPS65917_SMPS_SHORT_STATUS 0x29
3258 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3267 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3259 #define TPS65917_SMPS_POWERGOOD_MASK1 3268 #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3260 #define TPS65917_SMPS_POWERGOOD_MASK2 3269 #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3261 3270
3262 /* Bit definitions for SMPS1_CTRL */ 3271 /* Bit definitions for SMPS1_CTRL */
3263 #define TPS65917_SMPS1_CTRL_WR_S 3272 #define TPS65917_SMPS1_CTRL_WR_S 0x80
3264 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 3273 #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3265 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 3274 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3266 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHI 3275 #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3267 #define TPS65917_SMPS1_CTRL_STATUS_MASK 3276 #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3268 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 3277 #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3269 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 3278 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3270 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 3279 #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3271 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 3280 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3272 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 3281 #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3273 3282
3274 /* Bit definitions for SMPS1_FORCE */ 3283 /* Bit definitions for SMPS1_FORCE */
3275 #define TPS65917_SMPS1_FORCE_CMD 3284 #define TPS65917_SMPS1_FORCE_CMD 0x80
3276 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 3285 #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3277 #define TPS65917_SMPS1_FORCE_VSEL_MASK 3286 #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3278 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 3287 #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3279 3288
3280 /* Bit definitions for SMPS1_VOLTAGE */ 3289 /* Bit definitions for SMPS1_VOLTAGE */
3281 #define TPS65917_SMPS1_VOLTAGE_RANGE 3290 #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3282 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 3291 #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3283 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 3292 #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3284 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 3293 #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3285 3294
3286 /* Bit definitions for SMPS2_CTRL */ 3295 /* Bit definitions for SMPS2_CTRL */
3287 #define TPS65917_SMPS2_CTRL_WR_S 3296 #define TPS65917_SMPS2_CTRL_WR_S 0x80
3288 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 3297 #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3289 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 3298 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3290 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHI 3299 #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3291 #define TPS65917_SMPS2_CTRL_STATUS_MASK 3300 #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3292 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 3301 #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3293 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 3302 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3294 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 3303 #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3295 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 3304 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3296 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 3305 #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3297 3306
3298 /* Bit definitions for SMPS2_FORCE */ 3307 /* Bit definitions for SMPS2_FORCE */
3299 #define TPS65917_SMPS2_FORCE_CMD 3308 #define TPS65917_SMPS2_FORCE_CMD 0x80
3300 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 3309 #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3301 #define TPS65917_SMPS2_FORCE_VSEL_MASK 3310 #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3302 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 3311 #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3303 3312
3304 /* Bit definitions for SMPS2_VOLTAGE */ 3313 /* Bit definitions for SMPS2_VOLTAGE */
3305 #define TPS65917_SMPS2_VOLTAGE_RANGE 3314 #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3306 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 3315 #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3307 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 3316 #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3308 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 3317 #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3309 3318
3310 /* Bit definitions for SMPS3_CTRL */ 3319 /* Bit definitions for SMPS3_CTRL */
3311 #define TPS65917_SMPS3_CTRL_WR_S 3320 #define TPS65917_SMPS3_CTRL_WR_S 0x80
3312 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 3321 #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3313 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 3322 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3314 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHI 3323 #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3315 #define TPS65917_SMPS3_CTRL_STATUS_MASK 3324 #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3316 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 3325 #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3317 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 3326 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3318 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 3327 #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3319 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 3328 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3320 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 3329 #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3321 3330
3322 /* Bit definitions for SMPS3_FORCE */ 3331 /* Bit definitions for SMPS3_FORCE */
3323 #define TPS65917_SMPS3_FORCE_CMD 3332 #define TPS65917_SMPS3_FORCE_CMD 0x80
3324 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 3333 #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3325 #define TPS65917_SMPS3_FORCE_VSEL_MASK 3334 #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3326 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 3335 #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3327 3336
3328 /* Bit definitions for SMPS3_VOLTAGE */ 3337 /* Bit definitions for SMPS3_VOLTAGE */
3329 #define TPS65917_SMPS3_VOLTAGE_RANGE 3338 #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3330 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 3339 #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3331 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 3340 #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3332 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 3341 #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3333 3342
3334 /* Bit definitions for SMPS4_CTRL */ 3343 /* Bit definitions for SMPS4_CTRL */
3335 #define TPS65917_SMPS4_CTRL_WR_S 3344 #define TPS65917_SMPS4_CTRL_WR_S 0x80
3336 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 3345 #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3337 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 3346 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3338 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHI 3347 #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3339 #define TPS65917_SMPS4_CTRL_STATUS_MASK 3348 #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3340 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 3349 #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3341 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 3350 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3342 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 3351 #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3343 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 3352 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3344 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 3353 #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3345 3354
3346 /* Bit definitions for SMPS4_VOLTAGE */ 3355 /* Bit definitions for SMPS4_VOLTAGE */
3347 #define TPS65917_SMPS4_VOLTAGE_RANGE 3356 #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3348 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 3357 #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3349 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 3358 #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3350 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 3359 #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3351 3360
3352 /* Bit definitions for SMPS5_CTRL */ 3361 /* Bit definitions for SMPS5_CTRL */
3353 #define TPS65917_SMPS5_CTRL_WR_S 3362 #define TPS65917_SMPS5_CTRL_WR_S 0x80
3354 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 3363 #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3355 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 3364 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3356 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHI 3365 #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3357 #define TPS65917_SMPS5_CTRL_STATUS_MASK 3366 #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3358 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 3367 #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3359 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 3368 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3360 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 3369 #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3361 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 3370 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3362 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 3371 #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3363 3372
3364 /* Bit definitions for SMPS5_VOLTAGE */ 3373 /* Bit definitions for SMPS5_VOLTAGE */
3365 #define TPS65917_SMPS5_VOLTAGE_RANGE 3374 #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3366 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 3375 #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3367 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 3376 #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3368 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 3377 #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3369 3378
3370 /* Bit definitions for SMPS_CTRL */ 3379 /* Bit definitions for SMPS_CTRL */
3371 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 3380 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3372 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SH 3381 #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3373 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 3382 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3374 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_ 3383 #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3375 3384
3376 /* Bit definitions for SMPS_PD_CTRL */ 3385 /* Bit definitions for SMPS_PD_CTRL */
3377 #define TPS65917_SMPS_PD_CTRL_SMPS5 3386 #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3378 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 3387 #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3379 #define TPS65917_SMPS_PD_CTRL_SMPS4 3388 #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3380 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 3389 #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3381 #define TPS65917_SMPS_PD_CTRL_SMPS3 3390 #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3382 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 3391 #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3383 #define TPS65917_SMPS_PD_CTRL_SMPS2 3392 #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3384 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 3393 #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3385 #define TPS65917_SMPS_PD_CTRL_SMPS1 3394 #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3386 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 3395 #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3387 3396
3388 /* Bit definitions for SMPS_THERMAL_EN */ 3397 /* Bit definitions for SMPS_THERMAL_EN */
3389 #define TPS65917_SMPS_THERMAL_EN_SMPS5 3398 #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3390 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 3399 #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3391 #define TPS65917_SMPS_THERMAL_EN_SMPS3 3400 #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3392 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 3401 #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3393 #define TPS65917_SMPS_THERMAL_EN_SMPS12 3402 #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3394 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 3403 #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3395 3404
3396 /* Bit definitions for SMPS_THERMAL_STATUS */ 3405 /* Bit definitions for SMPS_THERMAL_STATUS */
3397 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 3406 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3398 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SH 3407 #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3399 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 3408 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3400 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SH 3409 #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3401 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 3410 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3402 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_S 3411 #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3403 3412
3404 /* Bit definitions for SMPS_SHORT_STATUS */ 3413 /* Bit definitions for SMPS_SHORT_STATUS */
3405 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 3414 #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3406 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIF 3415 #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3407 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 3416 #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3408 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIF 3417 #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3409 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 3418 #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3410 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIF 3419 #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3411 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 3420 #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3412 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIF 3421 #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3413 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 3422 #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3414 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIF 3423 #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3415 3424
3416 /* Bit definitions for SMPS_NEGATIVE_CURRENT_ 3425 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3417 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3426 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3418 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3427 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3419 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3428 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3420 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3429 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3421 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3430 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3422 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3431 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3423 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3432 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3424 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3433 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3425 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3434 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3426 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_ 3435 #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3427 3436
3428 /* Bit definitions for SMPS_POWERGOOD_MASK1 * 3437 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
3429 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 3438 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3430 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_S 3439 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3431 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 3440 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3432 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_S 3441 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3433 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 3442 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3434 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_S 3443 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3435 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 3444 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3436 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_S 3445 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3437 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 3446 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3438 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_S 3447 #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3439 3448
3440 /* Bit definitions for SMPS_POWERGOOD_MASK2 * 3449 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
3441 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGO 3450 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3442 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGO 3451 #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3443 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALA 3452 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3444 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALA 3453 #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3445 3454
3446 /* Bit definitions for SMPS_PLL_CTRL */ 3455 /* Bit definitions for SMPS_PLL_CTRL */
3447 3456
3448 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYP 3457 #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3449 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYP 3458 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3450 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS 3459 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3451 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS 3460 #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3452 3461
3453 /* Registers for function LDO */ 3462 /* Registers for function LDO */
3454 #define TPS65917_LDO1_CTRL 3463 #define TPS65917_LDO1_CTRL 0x00
3455 #define TPS65917_LDO1_VOLTAGE 3464 #define TPS65917_LDO1_VOLTAGE 0x01
3456 #define TPS65917_LDO2_CTRL 3465 #define TPS65917_LDO2_CTRL 0x02
3457 #define TPS65917_LDO2_VOLTAGE 3466 #define TPS65917_LDO2_VOLTAGE 0x03
3458 #define TPS65917_LDO3_CTRL 3467 #define TPS65917_LDO3_CTRL 0x04
3459 #define TPS65917_LDO3_VOLTAGE 3468 #define TPS65917_LDO3_VOLTAGE 0x05
3460 #define TPS65917_LDO4_CTRL 3469 #define TPS65917_LDO4_CTRL 0x0E
3461 #define TPS65917_LDO4_VOLTAGE 3470 #define TPS65917_LDO4_VOLTAGE 0x0F
3462 #define TPS65917_LDO5_CTRL 3471 #define TPS65917_LDO5_CTRL 0x12
3463 #define TPS65917_LDO5_VOLTAGE 3472 #define TPS65917_LDO5_VOLTAGE 0x13
3464 #define TPS65917_LDO_PD_CTRL1 3473 #define TPS65917_LDO_PD_CTRL1 0x1B
3465 #define TPS65917_LDO_PD_CTRL2 3474 #define TPS65917_LDO_PD_CTRL2 0x1C
3466 #define TPS65917_LDO_SHORT_STATUS1 3475 #define TPS65917_LDO_SHORT_STATUS1 0x1D
3467 #define TPS65917_LDO_SHORT_STATUS2 3476 #define TPS65917_LDO_SHORT_STATUS2 0x1E
3468 #define TPS65917_LDO_PD_CTRL3 3477 #define TPS65917_LDO_PD_CTRL3 0x2D
3469 #define TPS65917_LDO_SHORT_STATUS3 3478 #define TPS65917_LDO_SHORT_STATUS3 0x2E
3470 3479
3471 /* Bit definitions for LDO1_CTRL */ 3480 /* Bit definitions for LDO1_CTRL */
3472 #define TPS65917_LDO1_CTRL_WR_S 3481 #define TPS65917_LDO1_CTRL_WR_S 0x80
3473 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 3482 #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3474 #define TPS65917_LDO1_CTRL_BYPASS_EN 3483 #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3475 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 3484 #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3476 #define TPS65917_LDO1_CTRL_STATUS 3485 #define TPS65917_LDO1_CTRL_STATUS 0x10
3477 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 3486 #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3478 #define TPS65917_LDO1_CTRL_MODE_SLEEP 3487 #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3479 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 3488 #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3480 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 3489 #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3481 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 3490 #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3482 3491
3483 /* Bit definitions for LDO1_VOLTAGE */ 3492 /* Bit definitions for LDO1_VOLTAGE */
3484 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 3493 #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3485 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 3494 #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3486 3495
3487 /* Bit definitions for LDO2_CTRL */ 3496 /* Bit definitions for LDO2_CTRL */
3488 #define TPS65917_LDO2_CTRL_WR_S 3497 #define TPS65917_LDO2_CTRL_WR_S 0x80
3489 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 3498 #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3490 #define TPS65917_LDO2_CTRL_BYPASS_EN 3499 #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3491 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 3500 #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3492 #define TPS65917_LDO2_CTRL_STATUS 3501 #define TPS65917_LDO2_CTRL_STATUS 0x10
3493 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 3502 #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3494 #define TPS65917_LDO2_CTRL_MODE_SLEEP 3503 #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3495 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 3504 #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3496 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 3505 #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3497 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 3506 #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3498 3507
3499 /* Bit definitions for LDO2_VOLTAGE */ 3508 /* Bit definitions for LDO2_VOLTAGE */
3500 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 3509 #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3501 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 3510 #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3502 3511
3503 /* Bit definitions for LDO3_CTRL */ 3512 /* Bit definitions for LDO3_CTRL */
3504 #define TPS65917_LDO3_CTRL_WR_S 3513 #define TPS65917_LDO3_CTRL_WR_S 0x80
3505 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 3514 #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3506 #define TPS65917_LDO3_CTRL_STATUS 3515 #define TPS65917_LDO3_CTRL_STATUS 0x10
3507 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 3516 #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3508 #define TPS65917_LDO3_CTRL_MODE_SLEEP 3517 #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3509 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 3518 #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3510 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 3519 #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3511 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 3520 #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3512 3521
3513 /* Bit definitions for LDO3_VOLTAGE */ 3522 /* Bit definitions for LDO3_VOLTAGE */
3514 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 3523 #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3515 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 3524 #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3516 3525
3517 /* Bit definitions for LDO4_CTRL */ 3526 /* Bit definitions for LDO4_CTRL */
3518 #define TPS65917_LDO4_CTRL_WR_S 3527 #define TPS65917_LDO4_CTRL_WR_S 0x80
3519 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 3528 #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3520 #define TPS65917_LDO4_CTRL_STATUS 3529 #define TPS65917_LDO4_CTRL_STATUS 0x10
3521 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 3530 #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3522 #define TPS65917_LDO4_CTRL_MODE_SLEEP 3531 #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3523 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 3532 #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3524 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 3533 #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3525 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 3534 #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3526 3535
3527 /* Bit definitions for LDO4_VOLTAGE */ 3536 /* Bit definitions for LDO4_VOLTAGE */
3528 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 3537 #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3529 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 3538 #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3530 3539
3531 /* Bit definitions for LDO5_CTRL */ 3540 /* Bit definitions for LDO5_CTRL */
3532 #define TPS65917_LDO5_CTRL_WR_S 3541 #define TPS65917_LDO5_CTRL_WR_S 0x80
3533 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 3542 #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3534 #define TPS65917_LDO5_CTRL_STATUS 3543 #define TPS65917_LDO5_CTRL_STATUS 0x10
3535 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 3544 #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3536 #define TPS65917_LDO5_CTRL_MODE_SLEEP 3545 #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3537 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 3546 #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3538 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 3547 #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3539 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 3548 #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3540 3549
3541 /* Bit definitions for LDO5_VOLTAGE */ 3550 /* Bit definitions for LDO5_VOLTAGE */
3542 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 3551 #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3543 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 3552 #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3544 3553
3545 /* Bit definitions for LDO_PD_CTRL1 */ 3554 /* Bit definitions for LDO_PD_CTRL1 */
3546 #define TPS65917_LDO_PD_CTRL1_LDO4 3555 #define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3547 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 3556 #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3548 #define TPS65917_LDO_PD_CTRL1_LDO2 3557 #define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3549 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 3558 #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3550 #define TPS65917_LDO_PD_CTRL1_LDO1 3559 #define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3551 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 3560 #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3552 3561
3553 /* Bit definitions for LDO_PD_CTRL2 */ 3562 /* Bit definitions for LDO_PD_CTRL2 */
3554 #define TPS65917_LDO_PD_CTRL2_LDO3 3563 #define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3555 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 3564 #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3556 #define TPS65917_LDO_PD_CTRL2_LDO5 3565 #define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3557 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 3566 #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3558 3567
3559 /* Bit definitions for LDO_PD_CTRL3 */ 3568 /* Bit definitions for LDO_PD_CTRL3 */
3560 #define TPS65917_LDO_PD_CTRL2_LDOVANA 3569 #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3561 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 3570 #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3562 3571
3563 /* Bit definitions for LDO_SHORT_STATUS1 */ 3572 /* Bit definitions for LDO_SHORT_STATUS1 */
3564 #define TPS65917_LDO_SHORT_STATUS1_LDO4 3573 #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3565 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 3574 #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3566 #define TPS65917_LDO_SHORT_STATUS1_LDO2 3575 #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3567 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 3576 #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3568 #define TPS65917_LDO_SHORT_STATUS1_LDO1 3577 #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3569 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 3578 #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3570 3579
3571 /* Bit definitions for LDO_SHORT_STATUS2 */ 3580 /* Bit definitions for LDO_SHORT_STATUS2 */
3572 #define TPS65917_LDO_SHORT_STATUS2_LDO3 3581 #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3573 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 3582 #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3574 #define TPS65917_LDO_SHORT_STATUS2_LDO5 3583 #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3575 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 3584 #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3576 3585
3577 /* Bit definitions for LDO_SHORT_STATUS2 */ 3586 /* Bit definitions for LDO_SHORT_STATUS2 */
3578 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 3587 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3579 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SH 3588 #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3580 3589
3581 /* Bit definitions for REGEN1_CTRL */ 3590 /* Bit definitions for REGEN1_CTRL */
3582 #define TPS65917_REGEN1_CTRL_STATUS 3591 #define TPS65917_REGEN1_CTRL_STATUS 0x10
3583 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 3592 #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3584 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 3593 #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3585 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 3594 #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3586 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 3595 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3587 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIF 3596 #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3588 3597
3589 /* Bit definitions for PLLEN_CTRL */ 3598 /* Bit definitions for PLLEN_CTRL */
3590 #define TPS65917_PLLEN_CTRL_STATUS 3599 #define TPS65917_PLLEN_CTRL_STATUS 0x10
3591 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 3600 #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3592 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 3601 #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3593 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 3602 #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3594 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 3603 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3595 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 3604 #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3596 3605
3597 /* Bit definitions for REGEN2_CTRL */ 3606 /* Bit definitions for REGEN2_CTRL */
3598 #define TPS65917_REGEN2_CTRL_STATUS 3607 #define TPS65917_REGEN2_CTRL_STATUS 0x10
3599 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 3608 #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3600 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 3609 #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3601 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 3610 #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3602 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 3611 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3603 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIF 3612 #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3604 3613
3605 /* Bit definitions for NSLEEP_RES_ASSIGN */ 3614 /* Bit definitions for NSLEEP_RES_ASSIGN */
3606 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 3615 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3607 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHI 3616 #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3608 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 3617 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3609 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHI 3618 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3610 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 3619 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3611 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHI 3620 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3612 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 3621 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3613 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHI 3622 #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3614 3623
3615 /* Bit definitions for NSLEEP_SMPS_ASSIGN */ 3624 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
3616 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 3625 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3617 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHI 3626 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3618 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 3627 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3619 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHI 3628 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3620 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 3629 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3621 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHI 3630 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3622 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 3631 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3623 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHI 3632 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3624 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 3633 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3625 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHI 3634 #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3626 3635
3627 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 3636 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3628 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 3637 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3629 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIF 3638 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3630 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 3639 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3631 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIF 3640 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3632 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 3641 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3633 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIF 3642 #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3634 3643
3635 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 3644 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3636 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 3645 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3637 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIF 3646 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3638 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 3647 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3639 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIF 3648 #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3640 3649
3641 /* Bit definitions for ENABLE1_RES_ASSIGN */ 3650 /* Bit definitions for ENABLE1_RES_ASSIGN */
3642 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 3651 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3643 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHI 3652 #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3644 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 3653 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3645 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SH 3654 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3646 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 3655 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3647 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SH 3656 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3648 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 3657 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3649 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SH 3658 #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3650 3659
3651 /* Bit definitions for ENABLE1_SMPS_ASSIGN */ 3660 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
3652 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 3661 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3653 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SH 3662 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3654 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 3663 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3655 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SH 3664 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3656 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 3665 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3657 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SH 3666 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3658 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 3667 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3659 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SH 3668 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3660 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 3669 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3661 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SH 3670 #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3662 3671
3663 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 3672 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3664 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 3673 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3665 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHI 3674 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3666 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 3675 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3667 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHI 3676 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3668 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 3677 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3669 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHI 3678 #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3670 3679
3671 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 3680 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3672 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 3681 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3673 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHI 3682 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3674 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 3683 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3675 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHI 3684 #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3676 3685
3677 /* Bit definitions for ENABLE2_RES_ASSIGN */ 3686 /* Bit definitions for ENABLE2_RES_ASSIGN */
3678 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 3687 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3679 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHI 3688 #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3680 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 3689 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3681 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SH 3690 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3682 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 3691 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3683 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SH 3692 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3684 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 3693 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3685 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SH 3694 #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3686 3695
3687 /* Bit definitions for ENABLE2_SMPS_ASSIGN */ 3696 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
3688 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 3697 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3689 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SH 3698 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3690 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 3699 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3691 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SH 3700 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3692 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 3701 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3693 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SH 3702 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3694 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 3703 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3695 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SH 3704 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3696 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 3705 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3697 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SH 3706 #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3698 3707
3699 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 3708 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3700 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 3709 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3701 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHI 3710 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3702 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 3711 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3703 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHI 3712 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3704 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 3713 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3705 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHI 3714 #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3706 3715
3707 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 3716 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3708 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 3717 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3709 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHI 3718 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3710 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 3719 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3711 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHI 3720 #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3712 3721
3713 /* Bit definitions for REGEN3_CTRL */ 3722 /* Bit definitions for REGEN3_CTRL */
3714 #define TPS65917_REGEN3_CTRL_STATUS 3723 #define TPS65917_REGEN3_CTRL_STATUS 0x10
3715 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 3724 #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3716 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 3725 #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3717 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 3726 #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3718 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 3727 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3719 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIF 3728 #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3720 3729
3721 /* POWERHOLD Mask field for PRIMARY_SECONDARY 3730 /* POWERHOLD Mask field for PRIMARY_SECONDARY_PAD2 register */
3722 #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_ 3731 #define TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0xC
3723 3732
3724 /* Registers for function RESOURCE */ 3733 /* Registers for function RESOURCE */
3725 #define TPS65917_REGEN1_CTRL 3734 #define TPS65917_REGEN1_CTRL 0x2
3726 #define TPS65917_PLLEN_CTRL 3735 #define TPS65917_PLLEN_CTRL 0x3
3727 #define TPS65917_NSLEEP_RES_ASSIGN 3736 #define TPS65917_NSLEEP_RES_ASSIGN 0x6
3728 #define TPS65917_NSLEEP_SMPS_ASSIGN 3737 #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3729 #define TPS65917_NSLEEP_LDO_ASSIGN1 3738 #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3730 #define TPS65917_NSLEEP_LDO_ASSIGN2 3739 #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3731 #define TPS65917_ENABLE1_RES_ASSIGN 3740 #define TPS65917_ENABLE1_RES_ASSIGN 0xA
3732 #define TPS65917_ENABLE1_SMPS_ASSIGN 3741 #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3733 #define TPS65917_ENABLE1_LDO_ASSIGN1 3742 #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3734 #define TPS65917_ENABLE1_LDO_ASSIGN2 3743 #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3735 #define TPS65917_ENABLE2_RES_ASSIGN 3744 #define TPS65917_ENABLE2_RES_ASSIGN 0xE
3736 #define TPS65917_ENABLE2_SMPS_ASSIGN 3745 #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3737 #define TPS65917_ENABLE2_LDO_ASSIGN1 3746 #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3738 #define TPS65917_ENABLE2_LDO_ASSIGN2 3747 #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3739 #define TPS65917_REGEN2_CTRL 3748 #define TPS65917_REGEN2_CTRL 0x12
3740 #define TPS65917_REGEN3_CTRL 3749 #define TPS65917_REGEN3_CTRL 0x13
3741 3750
3742 static inline int palmas_read(struct palmas * 3751 static inline int palmas_read(struct palmas *palmas, unsigned int base,
3743 unsigned int reg, unsigned in 3752 unsigned int reg, unsigned int *val)
3744 { 3753 {
3745 unsigned int addr = PALMAS_BASE_TO_RE 3754 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3746 int slave_id = PALMAS_BASE_TO_SLAVE(b 3755 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3747 3756
3748 return regmap_read(palmas->regmap[sla 3757 return regmap_read(palmas->regmap[slave_id], addr, val);
3749 } 3758 }
3750 3759
3751 static inline int palmas_write(struct palmas 3760 static inline int palmas_write(struct palmas *palmas, unsigned int base,
3752 unsigned int reg, unsigned in 3761 unsigned int reg, unsigned int value)
3753 { 3762 {
3754 unsigned int addr = PALMAS_BASE_TO_RE 3763 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3755 int slave_id = PALMAS_BASE_TO_SLAVE(b 3764 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3756 3765
3757 return regmap_write(palmas->regmap[sl 3766 return regmap_write(palmas->regmap[slave_id], addr, value);
3758 } 3767 }
3759 3768
3760 static inline int palmas_bulk_write(struct pa 3769 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3761 unsigned int reg, const void *val, si 3770 unsigned int reg, const void *val, size_t val_count)
3762 { 3771 {
3763 unsigned int addr = PALMAS_BASE_TO_RE 3772 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3764 int slave_id = PALMAS_BASE_TO_SLAVE(b 3773 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3765 3774
3766 return regmap_bulk_write(palmas->regm 3775 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3767 val, val_count); 3776 val, val_count);
3768 } 3777 }
3769 3778
3770 static inline int palmas_bulk_read(struct pal 3779 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3771 unsigned int reg, void *val, 3780 unsigned int reg, void *val, size_t val_count)
3772 { 3781 {
3773 unsigned int addr = PALMAS_BASE_TO_RE 3782 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3774 int slave_id = PALMAS_BASE_TO_SLAVE(b 3783 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3775 3784
3776 return regmap_bulk_read(palmas->regma 3785 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3777 val, val_count); 3786 val, val_count);
3778 } 3787 }
3779 3788
3780 static inline int palmas_update_bits(struct p 3789 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3781 unsigned int reg, unsigned int mask, 3790 unsigned int reg, unsigned int mask, unsigned int val)
3782 { 3791 {
3783 unsigned int addr = PALMAS_BASE_TO_RE 3792 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3784 int slave_id = PALMAS_BASE_TO_SLAVE(b 3793 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3785 3794
3786 return regmap_update_bits(palmas->reg 3795 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3787 } 3796 }
3788 3797
3789 static inline int palmas_irq_get_virq(struct 3798 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3790 { 3799 {
3791 return regmap_irq_get_virq(palmas->ir 3800 return regmap_irq_get_virq(palmas->irq_data, irq);
3792 } 3801 }
3793 3802
3794 3803
3795 int palmas_ext_control_req_config(struct palm 3804 int palmas_ext_control_req_config(struct palmas *palmas,
3796 enum palmas_external_requestor_id ext 3805 enum palmas_external_requestor_id ext_control_req_id,
3797 int ext_ctrl, bool enable); 3806 int ext_ctrl, bool enable);
3798 3807
3799 #endif /* __LINUX_MFD_PALMAS_H */ 3808 #endif /* __LINUX_MFD_PALMAS_H */
3800 3809
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.