1 /* SPDX-License-Identifier: GPL-2.0+ */ !! 1 /* irq.h
2 /* !! 2 *
3 * Copyright (c) 2012 Samsung Electronics Co., 3 * Copyright (c) 2012 Samsung Electronics Co., Ltd
4 * http://www.samsung.com 4 * http://www.samsung.com
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
>> 10 *
5 */ 11 */
6 12
7 #ifndef __LINUX_MFD_SEC_IRQ_H 13 #ifndef __LINUX_MFD_SEC_IRQ_H
8 #define __LINUX_MFD_SEC_IRQ_H 14 #define __LINUX_MFD_SEC_IRQ_H
9 15
10 enum s2mpa01_irq { 16 enum s2mpa01_irq {
11 S2MPA01_IRQ_PWRONF, 17 S2MPA01_IRQ_PWRONF,
12 S2MPA01_IRQ_PWRONR, 18 S2MPA01_IRQ_PWRONR,
13 S2MPA01_IRQ_JIGONBF, 19 S2MPA01_IRQ_JIGONBF,
14 S2MPA01_IRQ_JIGONBR, 20 S2MPA01_IRQ_JIGONBR,
15 S2MPA01_IRQ_ACOKBF, 21 S2MPA01_IRQ_ACOKBF,
16 S2MPA01_IRQ_ACOKBR, 22 S2MPA01_IRQ_ACOKBR,
17 S2MPA01_IRQ_PWRON1S, 23 S2MPA01_IRQ_PWRON1S,
18 S2MPA01_IRQ_MRB, 24 S2MPA01_IRQ_MRB,
19 25
20 S2MPA01_IRQ_RTC60S, 26 S2MPA01_IRQ_RTC60S,
21 S2MPA01_IRQ_RTCA1, 27 S2MPA01_IRQ_RTCA1,
22 S2MPA01_IRQ_RTCA0, 28 S2MPA01_IRQ_RTCA0,
23 S2MPA01_IRQ_SMPL, 29 S2MPA01_IRQ_SMPL,
24 S2MPA01_IRQ_RTC1S, 30 S2MPA01_IRQ_RTC1S,
25 S2MPA01_IRQ_WTSR, 31 S2MPA01_IRQ_WTSR,
26 32
27 S2MPA01_IRQ_INT120C, 33 S2MPA01_IRQ_INT120C,
28 S2MPA01_IRQ_INT140C, 34 S2MPA01_IRQ_INT140C,
29 S2MPA01_IRQ_LDO3_TSD, 35 S2MPA01_IRQ_LDO3_TSD,
30 S2MPA01_IRQ_B16_TSD, 36 S2MPA01_IRQ_B16_TSD,
31 S2MPA01_IRQ_B24_TSD, 37 S2MPA01_IRQ_B24_TSD,
32 S2MPA01_IRQ_B35_TSD, 38 S2MPA01_IRQ_B35_TSD,
33 39
34 S2MPA01_IRQ_NR, 40 S2MPA01_IRQ_NR,
35 }; 41 };
36 42
37 #define S2MPA01_IRQ_PWRONF_MASK (1 << 43 #define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
38 #define S2MPA01_IRQ_PWRONR_MASK (1 << 44 #define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
39 #define S2MPA01_IRQ_JIGONBF_MASK (1 << 45 #define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
40 #define S2MPA01_IRQ_JIGONBR_MASK (1 << 46 #define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
41 #define S2MPA01_IRQ_ACOKBF_MASK (1 << 47 #define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
42 #define S2MPA01_IRQ_ACOKBR_MASK (1 << 48 #define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
43 #define S2MPA01_IRQ_PWRON1S_MASK (1 << 49 #define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
44 #define S2MPA01_IRQ_MRB_MASK (1 << 50 #define S2MPA01_IRQ_MRB_MASK (1 << 7)
45 51
46 #define S2MPA01_IRQ_RTC60S_MASK (1 << 52 #define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
47 #define S2MPA01_IRQ_RTCA1_MASK (1 << 53 #define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
48 #define S2MPA01_IRQ_RTCA0_MASK (1 << 54 #define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
49 #define S2MPA01_IRQ_SMPL_MASK (1 << 55 #define S2MPA01_IRQ_SMPL_MASK (1 << 3)
50 #define S2MPA01_IRQ_RTC1S_MASK (1 << 56 #define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
51 #define S2MPA01_IRQ_WTSR_MASK (1 << 57 #define S2MPA01_IRQ_WTSR_MASK (1 << 5)
52 58
53 #define S2MPA01_IRQ_INT120C_MASK (1 << 59 #define S2MPA01_IRQ_INT120C_MASK (1 << 0)
54 #define S2MPA01_IRQ_INT140C_MASK (1 << 60 #define S2MPA01_IRQ_INT140C_MASK (1 << 1)
55 #define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 61 #define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
56 #define S2MPA01_IRQ_B16_TSD_MASK (1 << 62 #define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
57 #define S2MPA01_IRQ_B24_TSD_MASK (1 << 63 #define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
58 #define S2MPA01_IRQ_B35_TSD_MASK (1 << 64 #define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
59 65
60 enum s2mps11_irq { 66 enum s2mps11_irq {
61 S2MPS11_IRQ_PWRONF, 67 S2MPS11_IRQ_PWRONF,
62 S2MPS11_IRQ_PWRONR, 68 S2MPS11_IRQ_PWRONR,
63 S2MPS11_IRQ_JIGONBF, 69 S2MPS11_IRQ_JIGONBF,
64 S2MPS11_IRQ_JIGONBR, 70 S2MPS11_IRQ_JIGONBR,
65 S2MPS11_IRQ_ACOKBF, 71 S2MPS11_IRQ_ACOKBF,
66 S2MPS11_IRQ_ACOKBR, 72 S2MPS11_IRQ_ACOKBR,
67 S2MPS11_IRQ_PWRON1S, 73 S2MPS11_IRQ_PWRON1S,
68 S2MPS11_IRQ_MRB, 74 S2MPS11_IRQ_MRB,
69 75
70 S2MPS11_IRQ_RTC60S, 76 S2MPS11_IRQ_RTC60S,
71 S2MPS11_IRQ_RTCA1, 77 S2MPS11_IRQ_RTCA1,
72 S2MPS11_IRQ_RTCA0, 78 S2MPS11_IRQ_RTCA0,
73 S2MPS11_IRQ_SMPL, 79 S2MPS11_IRQ_SMPL,
74 S2MPS11_IRQ_RTC1S, 80 S2MPS11_IRQ_RTC1S,
75 S2MPS11_IRQ_WTSR, 81 S2MPS11_IRQ_WTSR,
76 82
77 S2MPS11_IRQ_INT120C, 83 S2MPS11_IRQ_INT120C,
78 S2MPS11_IRQ_INT140C, 84 S2MPS11_IRQ_INT140C,
79 85
80 S2MPS11_IRQ_NR, 86 S2MPS11_IRQ_NR,
81 }; 87 };
82 88
83 #define S2MPS11_IRQ_PWRONF_MASK (1 << 89 #define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
84 #define S2MPS11_IRQ_PWRONR_MASK (1 << 90 #define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
85 #define S2MPS11_IRQ_JIGONBF_MASK (1 << 91 #define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
86 #define S2MPS11_IRQ_JIGONBR_MASK (1 << 92 #define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
87 #define S2MPS11_IRQ_ACOKBF_MASK (1 << 93 #define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
88 #define S2MPS11_IRQ_ACOKBR_MASK (1 << 94 #define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
89 #define S2MPS11_IRQ_PWRON1S_MASK (1 << 95 #define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
90 #define S2MPS11_IRQ_MRB_MASK (1 << 96 #define S2MPS11_IRQ_MRB_MASK (1 << 7)
91 97
92 #define S2MPS11_IRQ_RTC60S_MASK (1 << 98 #define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
93 #define S2MPS11_IRQ_RTCA1_MASK (1 << 99 #define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
94 #define S2MPS11_IRQ_RTCA0_MASK (1 << 100 #define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
95 #define S2MPS11_IRQ_SMPL_MASK (1 << 101 #define S2MPS11_IRQ_SMPL_MASK (1 << 3)
96 #define S2MPS11_IRQ_RTC1S_MASK (1 << 102 #define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
97 #define S2MPS11_IRQ_WTSR_MASK (1 << 103 #define S2MPS11_IRQ_WTSR_MASK (1 << 5)
98 104
99 #define S2MPS11_IRQ_INT120C_MASK (1 << 105 #define S2MPS11_IRQ_INT120C_MASK (1 << 0)
100 #define S2MPS11_IRQ_INT140C_MASK (1 << 106 #define S2MPS11_IRQ_INT140C_MASK (1 << 1)
101 107
102 enum s2mps14_irq { 108 enum s2mps14_irq {
103 S2MPS14_IRQ_PWRONF, 109 S2MPS14_IRQ_PWRONF,
104 S2MPS14_IRQ_PWRONR, 110 S2MPS14_IRQ_PWRONR,
105 S2MPS14_IRQ_JIGONBF, 111 S2MPS14_IRQ_JIGONBF,
106 S2MPS14_IRQ_JIGONBR, 112 S2MPS14_IRQ_JIGONBR,
107 S2MPS14_IRQ_ACOKBF, 113 S2MPS14_IRQ_ACOKBF,
108 S2MPS14_IRQ_ACOKBR, 114 S2MPS14_IRQ_ACOKBR,
109 S2MPS14_IRQ_PWRON1S, 115 S2MPS14_IRQ_PWRON1S,
110 S2MPS14_IRQ_MRB, 116 S2MPS14_IRQ_MRB,
111 117
112 S2MPS14_IRQ_RTC60S, 118 S2MPS14_IRQ_RTC60S,
113 S2MPS14_IRQ_RTCA1, 119 S2MPS14_IRQ_RTCA1,
114 S2MPS14_IRQ_RTCA0, 120 S2MPS14_IRQ_RTCA0,
115 S2MPS14_IRQ_SMPL, 121 S2MPS14_IRQ_SMPL,
116 S2MPS14_IRQ_RTC1S, 122 S2MPS14_IRQ_RTC1S,
117 S2MPS14_IRQ_WTSR, 123 S2MPS14_IRQ_WTSR,
118 124
119 S2MPS14_IRQ_INT120C, 125 S2MPS14_IRQ_INT120C,
120 S2MPS14_IRQ_INT140C, 126 S2MPS14_IRQ_INT140C,
121 S2MPS14_IRQ_TSD, 127 S2MPS14_IRQ_TSD,
122 128
123 S2MPS14_IRQ_NR, 129 S2MPS14_IRQ_NR,
124 }; 130 };
125 131
126 enum s2mpu02_irq { 132 enum s2mpu02_irq {
127 S2MPU02_IRQ_PWRONF, 133 S2MPU02_IRQ_PWRONF,
128 S2MPU02_IRQ_PWRONR, 134 S2MPU02_IRQ_PWRONR,
129 S2MPU02_IRQ_JIGONBF, 135 S2MPU02_IRQ_JIGONBF,
130 S2MPU02_IRQ_JIGONBR, 136 S2MPU02_IRQ_JIGONBR,
131 S2MPU02_IRQ_ACOKBF, 137 S2MPU02_IRQ_ACOKBF,
132 S2MPU02_IRQ_ACOKBR, 138 S2MPU02_IRQ_ACOKBR,
133 S2MPU02_IRQ_PWRON1S, 139 S2MPU02_IRQ_PWRON1S,
134 S2MPU02_IRQ_MRB, 140 S2MPU02_IRQ_MRB,
135 141
136 S2MPU02_IRQ_RTC60S, 142 S2MPU02_IRQ_RTC60S,
137 S2MPU02_IRQ_RTCA1, 143 S2MPU02_IRQ_RTCA1,
138 S2MPU02_IRQ_RTCA0, 144 S2MPU02_IRQ_RTCA0,
139 S2MPU02_IRQ_SMPL, 145 S2MPU02_IRQ_SMPL,
140 S2MPU02_IRQ_RTC1S, 146 S2MPU02_IRQ_RTC1S,
141 S2MPU02_IRQ_WTSR, 147 S2MPU02_IRQ_WTSR,
142 148
143 S2MPU02_IRQ_INT120C, 149 S2MPU02_IRQ_INT120C,
144 S2MPU02_IRQ_INT140C, 150 S2MPU02_IRQ_INT140C,
145 S2MPU02_IRQ_TSD, 151 S2MPU02_IRQ_TSD,
146 152
147 S2MPU02_IRQ_NR, 153 S2MPU02_IRQ_NR,
148 }; 154 };
149 155
150 /* Masks for interrupts are the same as in s2m 156 /* Masks for interrupts are the same as in s2mps11 */
151 #define S2MPS14_IRQ_TSD_MASK (1 << 157 #define S2MPS14_IRQ_TSD_MASK (1 << 2)
152 158
153 enum s5m8767_irq { 159 enum s5m8767_irq {
154 S5M8767_IRQ_PWRR, 160 S5M8767_IRQ_PWRR,
155 S5M8767_IRQ_PWRF, 161 S5M8767_IRQ_PWRF,
156 S5M8767_IRQ_PWR1S, 162 S5M8767_IRQ_PWR1S,
157 S5M8767_IRQ_JIGR, 163 S5M8767_IRQ_JIGR,
158 S5M8767_IRQ_JIGF, 164 S5M8767_IRQ_JIGF,
159 S5M8767_IRQ_LOWBAT2, 165 S5M8767_IRQ_LOWBAT2,
160 S5M8767_IRQ_LOWBAT1, 166 S5M8767_IRQ_LOWBAT1,
161 167
162 S5M8767_IRQ_MRB, 168 S5M8767_IRQ_MRB,
163 S5M8767_IRQ_DVSOK2, 169 S5M8767_IRQ_DVSOK2,
164 S5M8767_IRQ_DVSOK3, 170 S5M8767_IRQ_DVSOK3,
165 S5M8767_IRQ_DVSOK4, 171 S5M8767_IRQ_DVSOK4,
166 172
167 S5M8767_IRQ_RTC60S, 173 S5M8767_IRQ_RTC60S,
168 S5M8767_IRQ_RTCA1, 174 S5M8767_IRQ_RTCA1,
169 S5M8767_IRQ_RTCA2, 175 S5M8767_IRQ_RTCA2,
170 S5M8767_IRQ_SMPL, 176 S5M8767_IRQ_SMPL,
171 S5M8767_IRQ_RTC1S, 177 S5M8767_IRQ_RTC1S,
172 S5M8767_IRQ_WTSR, 178 S5M8767_IRQ_WTSR,
173 179
174 S5M8767_IRQ_NR, 180 S5M8767_IRQ_NR,
175 }; 181 };
176 182
177 #define S5M8767_IRQ_PWRR_MASK (1 << 183 #define S5M8767_IRQ_PWRR_MASK (1 << 0)
178 #define S5M8767_IRQ_PWRF_MASK (1 << 184 #define S5M8767_IRQ_PWRF_MASK (1 << 1)
179 #define S5M8767_IRQ_PWR1S_MASK (1 << 185 #define S5M8767_IRQ_PWR1S_MASK (1 << 3)
180 #define S5M8767_IRQ_JIGR_MASK (1 << 186 #define S5M8767_IRQ_JIGR_MASK (1 << 4)
181 #define S5M8767_IRQ_JIGF_MASK (1 << 187 #define S5M8767_IRQ_JIGF_MASK (1 << 5)
182 #define S5M8767_IRQ_LOWBAT2_MASK (1 << 188 #define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
183 #define S5M8767_IRQ_LOWBAT1_MASK (1 << 189 #define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
184 190
185 #define S5M8767_IRQ_MRB_MASK (1 << 191 #define S5M8767_IRQ_MRB_MASK (1 << 2)
186 #define S5M8767_IRQ_DVSOK2_MASK (1 << 192 #define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
187 #define S5M8767_IRQ_DVSOK3_MASK (1 << 193 #define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
188 #define S5M8767_IRQ_DVSOK4_MASK (1 << 194 #define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
189 195
190 #define S5M8767_IRQ_RTC60S_MASK (1 << 196 #define S5M8767_IRQ_RTC60S_MASK (1 << 0)
191 #define S5M8767_IRQ_RTCA1_MASK (1 << 197 #define S5M8767_IRQ_RTCA1_MASK (1 << 1)
192 #define S5M8767_IRQ_RTCA2_MASK (1 << 198 #define S5M8767_IRQ_RTCA2_MASK (1 << 2)
193 #define S5M8767_IRQ_SMPL_MASK (1 << 199 #define S5M8767_IRQ_SMPL_MASK (1 << 3)
194 #define S5M8767_IRQ_RTC1S_MASK (1 << 200 #define S5M8767_IRQ_RTC1S_MASK (1 << 4)
195 #define S5M8767_IRQ_WTSR_MASK (1 << 201 #define S5M8767_IRQ_WTSR_MASK (1 << 5)
>> 202
>> 203 enum s5m8763_irq {
>> 204 S5M8763_IRQ_DCINF,
>> 205 S5M8763_IRQ_DCINR,
>> 206 S5M8763_IRQ_JIGF,
>> 207 S5M8763_IRQ_JIGR,
>> 208 S5M8763_IRQ_PWRONF,
>> 209 S5M8763_IRQ_PWRONR,
>> 210
>> 211 S5M8763_IRQ_WTSREVNT,
>> 212 S5M8763_IRQ_SMPLEVNT,
>> 213 S5M8763_IRQ_ALARM1,
>> 214 S5M8763_IRQ_ALARM0,
>> 215
>> 216 S5M8763_IRQ_ONKEY1S,
>> 217 S5M8763_IRQ_TOPOFFR,
>> 218 S5M8763_IRQ_DCINOVPR,
>> 219 S5M8763_IRQ_CHGRSTF,
>> 220 S5M8763_IRQ_DONER,
>> 221 S5M8763_IRQ_CHGFAULT,
>> 222
>> 223 S5M8763_IRQ_LOBAT1,
>> 224 S5M8763_IRQ_LOBAT2,
>> 225
>> 226 S5M8763_IRQ_NR,
>> 227 };
>> 228
>> 229 #define S5M8763_IRQ_DCINF_MASK (1 << 2)
>> 230 #define S5M8763_IRQ_DCINR_MASK (1 << 3)
>> 231 #define S5M8763_IRQ_JIGF_MASK (1 << 4)
>> 232 #define S5M8763_IRQ_JIGR_MASK (1 << 5)
>> 233 #define S5M8763_IRQ_PWRONF_MASK (1 << 6)
>> 234 #define S5M8763_IRQ_PWRONR_MASK (1 << 7)
>> 235
>> 236 #define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
>> 237 #define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
>> 238 #define S5M8763_IRQ_ALARM1_MASK (1 << 2)
>> 239 #define S5M8763_IRQ_ALARM0_MASK (1 << 3)
>> 240
>> 241 #define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
>> 242 #define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
>> 243 #define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
>> 244 #define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
>> 245 #define S5M8763_IRQ_DONER_MASK (1 << 5)
>> 246 #define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
>> 247
>> 248 #define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
>> 249 #define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
>> 250
>> 251 #define S5M8763_ENRAMP (1 << 4)
196 252
197 #endif /* __LINUX_MFD_SEC_IRQ_H */ 253 #endif /* __LINUX_MFD_SEC_IRQ_H */
198 254
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.