1 /* SPDX-License-Identifier: GPL-2.0+ */ 1
2 /*
3 * Copyright (c) 2013 Samsung Electronics Co.,
4 * http://www.samsung.com
5 */
6
7 #ifndef __LINUX_MFD_S2MPA01_H
8 #define __LINUX_MFD_S2MPA01_H
9
10 /* S2MPA01 registers */
11 enum s2mpa01_reg {
12 S2MPA01_REG_ID,
13 S2MPA01_REG_INT1,
14 S2MPA01_REG_INT2,
15 S2MPA01_REG_INT3,
16 S2MPA01_REG_INT1M,
17 S2MPA01_REG_INT2M,
18 S2MPA01_REG_INT3M,
19 S2MPA01_REG_ST1,
20 S2MPA01_REG_ST2,
21 S2MPA01_REG_PWRONSRC,
22 S2MPA01_REG_OFFSRC,
23 S2MPA01_REG_RTC_BUF,
24 S2MPA01_REG_CTRL1,
25 S2MPA01_REG_ETC_TEST,
26 S2MPA01_REG_RSVD1,
27 S2MPA01_REG_BU_CHG,
28 S2MPA01_REG_RAMP1,
29 S2MPA01_REG_RAMP2,
30 S2MPA01_REG_LDO_DSCH1,
31 S2MPA01_REG_LDO_DSCH2,
32 S2MPA01_REG_LDO_DSCH3,
33 S2MPA01_REG_LDO_DSCH4,
34 S2MPA01_REG_OTP_ADRL,
35 S2MPA01_REG_OTP_ADRH,
36 S2MPA01_REG_OTP_DATA,
37 S2MPA01_REG_MON1SEL,
38 S2MPA01_REG_MON2SEL,
39 S2MPA01_REG_LEE,
40 S2MPA01_REG_RSVD2,
41 S2MPA01_REG_RSVD3,
42 S2MPA01_REG_RSVD4,
43 S2MPA01_REG_RSVD5,
44 S2MPA01_REG_RSVD6,
45 S2MPA01_REG_TOP_RSVD,
46 S2MPA01_REG_DVS_SEL,
47 S2MPA01_REG_DVS_PTR,
48 S2MPA01_REG_DVS_DATA,
49 S2MPA01_REG_RSVD_NO,
50 S2MPA01_REG_UVLO,
51 S2MPA01_REG_LEE_NO,
52 S2MPA01_REG_B1CTRL1,
53 S2MPA01_REG_B1CTRL2,
54 S2MPA01_REG_B2CTRL1,
55 S2MPA01_REG_B2CTRL2,
56 S2MPA01_REG_B3CTRL1,
57 S2MPA01_REG_B3CTRL2,
58 S2MPA01_REG_B4CTRL1,
59 S2MPA01_REG_B4CTRL2,
60 S2MPA01_REG_B5CTRL1,
61 S2MPA01_REG_B5CTRL2,
62 S2MPA01_REG_B5CTRL3,
63 S2MPA01_REG_B5CTRL4,
64 S2MPA01_REG_B5CTRL5,
65 S2MPA01_REG_B5CTRL6,
66 S2MPA01_REG_B6CTRL1,
67 S2MPA01_REG_B6CTRL2,
68 S2MPA01_REG_B7CTRL1,
69 S2MPA01_REG_B7CTRL2,
70 S2MPA01_REG_B8CTRL1,
71 S2MPA01_REG_B8CTRL2,
72 S2MPA01_REG_B9CTRL1,
73 S2MPA01_REG_B9CTRL2,
74 S2MPA01_REG_B10CTRL1,
75 S2MPA01_REG_B10CTRL2,
76 S2MPA01_REG_L1CTRL,
77 S2MPA01_REG_L2CTRL,
78 S2MPA01_REG_L3CTRL,
79 S2MPA01_REG_L4CTRL,
80 S2MPA01_REG_L5CTRL,
81 S2MPA01_REG_L6CTRL,
82 S2MPA01_REG_L7CTRL,
83 S2MPA01_REG_L8CTRL,
84 S2MPA01_REG_L9CTRL,
85 S2MPA01_REG_L10CTRL,
86 S2MPA01_REG_L11CTRL,
87 S2MPA01_REG_L12CTRL,
88 S2MPA01_REG_L13CTRL,
89 S2MPA01_REG_L14CTRL,
90 S2MPA01_REG_L15CTRL,
91 S2MPA01_REG_L16CTRL,
92 S2MPA01_REG_L17CTRL,
93 S2MPA01_REG_L18CTRL,
94 S2MPA01_REG_L19CTRL,
95 S2MPA01_REG_L20CTRL,
96 S2MPA01_REG_L21CTRL,
97 S2MPA01_REG_L22CTRL,
98 S2MPA01_REG_L23CTRL,
99 S2MPA01_REG_L24CTRL,
100 S2MPA01_REG_L25CTRL,
101 S2MPA01_REG_L26CTRL,
102
103 S2MPA01_REG_LDO_OVCB1,
104 S2MPA01_REG_LDO_OVCB2,
105 S2MPA01_REG_LDO_OVCB3,
106 S2MPA01_REG_LDO_OVCB4,
107
108 };
109
110 /* S2MPA01 regulator ids */
111 enum s2mpa01_regulators {
112 S2MPA01_LDO1,
113 S2MPA01_LDO2,
114 S2MPA01_LDO3,
115 S2MPA01_LDO4,
116 S2MPA01_LDO5,
117 S2MPA01_LDO6,
118 S2MPA01_LDO7,
119 S2MPA01_LDO8,
120 S2MPA01_LDO9,
121 S2MPA01_LDO10,
122 S2MPA01_LDO11,
123 S2MPA01_LDO12,
124 S2MPA01_LDO13,
125 S2MPA01_LDO14,
126 S2MPA01_LDO15,
127 S2MPA01_LDO16,
128 S2MPA01_LDO17,
129 S2MPA01_LDO18,
130 S2MPA01_LDO19,
131 S2MPA01_LDO20,
132 S2MPA01_LDO21,
133 S2MPA01_LDO22,
134 S2MPA01_LDO23,
135 S2MPA01_LDO24,
136 S2MPA01_LDO25,
137 S2MPA01_LDO26,
138
139 S2MPA01_BUCK1,
140 S2MPA01_BUCK2,
141 S2MPA01_BUCK3,
142 S2MPA01_BUCK4,
143 S2MPA01_BUCK5,
144 S2MPA01_BUCK6,
145 S2MPA01_BUCK7,
146 S2MPA01_BUCK8,
147 S2MPA01_BUCK9,
148 S2MPA01_BUCK10,
149
150 S2MPA01_REGULATOR_MAX,
151 };
152
153 #define S2MPA01_LDO_VSEL_MASK 0x3F
154 #define S2MPA01_BUCK_VSEL_MASK 0xFF
155 #define S2MPA01_ENABLE_MASK (0x03 << S2MPA
156 #define S2MPA01_ENABLE_SHIFT 0x06
157 #define S2MPA01_LDO_N_VOLTAGES (S2MPA01_LDO_V
158 #define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_
159
160 #define S2MPA01_RAMP_DELAY 12500 /* uV/
161
162 #define S2MPA01_BUCK16_RAMP_SHIFT 4
163 #define S2MPA01_BUCK24_RAMP_SHIFT 6
164 #define S2MPA01_BUCK3_RAMP_SHIFT 4
165 #define S2MPA01_BUCK5_RAMP_SHIFT 6
166 #define S2MPA01_BUCK7_RAMP_SHIFT 2
167 #define S2MPA01_BUCK8910_RAMP_SHIFT 0
168
169 #define S2MPA01_BUCK1_RAMP_EN_SHIFT 3
170 #define S2MPA01_BUCK2_RAMP_EN_SHIFT 2
171 #define S2MPA01_BUCK3_RAMP_EN_SHIFT 1
172 #define S2MPA01_BUCK4_RAMP_EN_SHIFT 0
173 #define S2MPA01_PMIC_EN_SHIFT 6
174
175 #endif /*__LINUX_MFD_S2MPA01_H */
176
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