1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright (c) 2015 Samsung Electronics Co., 3 * Copyright (c) 2015 Samsung Electronics Co., Ltd
4 * http://www.samsung.com 4 * http://www.samsung.com
5 */ 5 */
6 6
7 #ifndef __LINUX_MFD_S2MPS15_H 7 #ifndef __LINUX_MFD_S2MPS15_H
8 #define __LINUX_MFD_S2MPS15_H 8 #define __LINUX_MFD_S2MPS15_H
9 9
10 /* S2MPS15 registers */ 10 /* S2MPS15 registers */
11 enum s2mps15_reg { 11 enum s2mps15_reg {
12 S2MPS15_REG_ID, 12 S2MPS15_REG_ID,
13 S2MPS15_REG_INT1, 13 S2MPS15_REG_INT1,
14 S2MPS15_REG_INT2, 14 S2MPS15_REG_INT2,
15 S2MPS15_REG_INT3, 15 S2MPS15_REG_INT3,
16 S2MPS15_REG_INT1M, 16 S2MPS15_REG_INT1M,
17 S2MPS15_REG_INT2M, 17 S2MPS15_REG_INT2M,
18 S2MPS15_REG_INT3M, 18 S2MPS15_REG_INT3M,
19 S2MPS15_REG_ST1, 19 S2MPS15_REG_ST1,
20 S2MPS15_REG_ST2, 20 S2MPS15_REG_ST2,
21 S2MPS15_REG_PWRONSRC, 21 S2MPS15_REG_PWRONSRC,
22 S2MPS15_REG_OFFSRC, 22 S2MPS15_REG_OFFSRC,
23 S2MPS15_REG_BU_CHG, 23 S2MPS15_REG_BU_CHG,
24 S2MPS15_REG_RTC_BUF, 24 S2MPS15_REG_RTC_BUF,
25 S2MPS15_REG_CTRL1, 25 S2MPS15_REG_CTRL1,
26 S2MPS15_REG_CTRL2, 26 S2MPS15_REG_CTRL2,
27 S2MPS15_REG_RSVD1, 27 S2MPS15_REG_RSVD1,
28 S2MPS15_REG_RSVD2, 28 S2MPS15_REG_RSVD2,
29 S2MPS15_REG_RSVD3, 29 S2MPS15_REG_RSVD3,
30 S2MPS15_REG_RSVD4, 30 S2MPS15_REG_RSVD4,
31 S2MPS15_REG_RSVD5, 31 S2MPS15_REG_RSVD5,
32 S2MPS15_REG_RSVD6, 32 S2MPS15_REG_RSVD6,
33 S2MPS15_REG_CTRL3, 33 S2MPS15_REG_CTRL3,
34 S2MPS15_REG_RSVD7, 34 S2MPS15_REG_RSVD7,
35 S2MPS15_REG_RSVD8, 35 S2MPS15_REG_RSVD8,
36 S2MPS15_REG_RSVD9, 36 S2MPS15_REG_RSVD9,
37 S2MPS15_REG_B1CTRL1, 37 S2MPS15_REG_B1CTRL1,
38 S2MPS15_REG_B1CTRL2, 38 S2MPS15_REG_B1CTRL2,
39 S2MPS15_REG_B2CTRL1, 39 S2MPS15_REG_B2CTRL1,
40 S2MPS15_REG_B2CTRL2, 40 S2MPS15_REG_B2CTRL2,
41 S2MPS15_REG_B3CTRL1, 41 S2MPS15_REG_B3CTRL1,
42 S2MPS15_REG_B3CTRL2, 42 S2MPS15_REG_B3CTRL2,
43 S2MPS15_REG_B4CTRL1, 43 S2MPS15_REG_B4CTRL1,
44 S2MPS15_REG_B4CTRL2, 44 S2MPS15_REG_B4CTRL2,
45 S2MPS15_REG_B5CTRL1, 45 S2MPS15_REG_B5CTRL1,
46 S2MPS15_REG_B5CTRL2, 46 S2MPS15_REG_B5CTRL2,
47 S2MPS15_REG_B6CTRL1, 47 S2MPS15_REG_B6CTRL1,
48 S2MPS15_REG_B6CTRL2, 48 S2MPS15_REG_B6CTRL2,
49 S2MPS15_REG_B7CTRL1, 49 S2MPS15_REG_B7CTRL1,
50 S2MPS15_REG_B7CTRL2, 50 S2MPS15_REG_B7CTRL2,
51 S2MPS15_REG_B8CTRL1, 51 S2MPS15_REG_B8CTRL1,
52 S2MPS15_REG_B8CTRL2, 52 S2MPS15_REG_B8CTRL2,
53 S2MPS15_REG_B9CTRL1, 53 S2MPS15_REG_B9CTRL1,
54 S2MPS15_REG_B9CTRL2, 54 S2MPS15_REG_B9CTRL2,
55 S2MPS15_REG_B10CTRL1, 55 S2MPS15_REG_B10CTRL1,
56 S2MPS15_REG_B10CTRL2, 56 S2MPS15_REG_B10CTRL2,
57 S2MPS15_REG_BBCTRL1, 57 S2MPS15_REG_BBCTRL1,
58 S2MPS15_REG_BBCTRL2, 58 S2MPS15_REG_BBCTRL2,
59 S2MPS15_REG_BRAMP, 59 S2MPS15_REG_BRAMP,
60 S2MPS15_REG_LDODVS1, 60 S2MPS15_REG_LDODVS1,
61 S2MPS15_REG_LDODVS2, 61 S2MPS15_REG_LDODVS2,
62 S2MPS15_REG_LDODVS3, 62 S2MPS15_REG_LDODVS3,
63 S2MPS15_REG_LDODVS4, 63 S2MPS15_REG_LDODVS4,
64 S2MPS15_REG_L1CTRL, 64 S2MPS15_REG_L1CTRL,
65 S2MPS15_REG_L2CTRL, 65 S2MPS15_REG_L2CTRL,
66 S2MPS15_REG_L3CTRL, 66 S2MPS15_REG_L3CTRL,
67 S2MPS15_REG_L4CTRL, 67 S2MPS15_REG_L4CTRL,
68 S2MPS15_REG_L5CTRL, 68 S2MPS15_REG_L5CTRL,
69 S2MPS15_REG_L6CTRL, 69 S2MPS15_REG_L6CTRL,
70 S2MPS15_REG_L7CTRL, 70 S2MPS15_REG_L7CTRL,
71 S2MPS15_REG_L8CTRL, 71 S2MPS15_REG_L8CTRL,
72 S2MPS15_REG_L9CTRL, 72 S2MPS15_REG_L9CTRL,
73 S2MPS15_REG_L10CTRL, 73 S2MPS15_REG_L10CTRL,
74 S2MPS15_REG_L11CTRL, 74 S2MPS15_REG_L11CTRL,
75 S2MPS15_REG_L12CTRL, 75 S2MPS15_REG_L12CTRL,
76 S2MPS15_REG_L13CTRL, 76 S2MPS15_REG_L13CTRL,
77 S2MPS15_REG_L14CTRL, 77 S2MPS15_REG_L14CTRL,
78 S2MPS15_REG_L15CTRL, 78 S2MPS15_REG_L15CTRL,
79 S2MPS15_REG_L16CTRL, 79 S2MPS15_REG_L16CTRL,
80 S2MPS15_REG_L17CTRL, 80 S2MPS15_REG_L17CTRL,
81 S2MPS15_REG_L18CTRL, 81 S2MPS15_REG_L18CTRL,
82 S2MPS15_REG_L19CTRL, 82 S2MPS15_REG_L19CTRL,
83 S2MPS15_REG_L20CTRL, 83 S2MPS15_REG_L20CTRL,
84 S2MPS15_REG_L21CTRL, 84 S2MPS15_REG_L21CTRL,
85 S2MPS15_REG_L22CTRL, 85 S2MPS15_REG_L22CTRL,
86 S2MPS15_REG_L23CTRL, 86 S2MPS15_REG_L23CTRL,
87 S2MPS15_REG_L24CTRL, 87 S2MPS15_REG_L24CTRL,
88 S2MPS15_REG_L25CTRL, 88 S2MPS15_REG_L25CTRL,
89 S2MPS15_REG_L26CTRL, 89 S2MPS15_REG_L26CTRL,
90 S2MPS15_REG_L27CTRL, 90 S2MPS15_REG_L27CTRL,
91 S2MPS15_REG_LDODSCH1, 91 S2MPS15_REG_LDODSCH1,
92 S2MPS15_REG_LDODSCH2, 92 S2MPS15_REG_LDODSCH2,
93 S2MPS15_REG_LDODSCH3, 93 S2MPS15_REG_LDODSCH3,
94 S2MPS15_REG_LDODSCH4, 94 S2MPS15_REG_LDODSCH4,
95 }; 95 };
96 96
97 /* S2MPS15 regulator ids */ 97 /* S2MPS15 regulator ids */
98 enum s2mps15_regulators { 98 enum s2mps15_regulators {
99 S2MPS15_LDO1, 99 S2MPS15_LDO1,
100 S2MPS15_LDO2, 100 S2MPS15_LDO2,
101 S2MPS15_LDO3, 101 S2MPS15_LDO3,
102 S2MPS15_LDO4, 102 S2MPS15_LDO4,
103 S2MPS15_LDO5, 103 S2MPS15_LDO5,
104 S2MPS15_LDO6, 104 S2MPS15_LDO6,
105 S2MPS15_LDO7, 105 S2MPS15_LDO7,
106 S2MPS15_LDO8, 106 S2MPS15_LDO8,
107 S2MPS15_LDO9, 107 S2MPS15_LDO9,
108 S2MPS15_LDO10, 108 S2MPS15_LDO10,
109 S2MPS15_LDO11, 109 S2MPS15_LDO11,
110 S2MPS15_LDO12, 110 S2MPS15_LDO12,
111 S2MPS15_LDO13, 111 S2MPS15_LDO13,
112 S2MPS15_LDO14, 112 S2MPS15_LDO14,
113 S2MPS15_LDO15, 113 S2MPS15_LDO15,
114 S2MPS15_LDO16, 114 S2MPS15_LDO16,
115 S2MPS15_LDO17, 115 S2MPS15_LDO17,
116 S2MPS15_LDO18, 116 S2MPS15_LDO18,
117 S2MPS15_LDO19, 117 S2MPS15_LDO19,
118 S2MPS15_LDO20, 118 S2MPS15_LDO20,
119 S2MPS15_LDO21, 119 S2MPS15_LDO21,
120 S2MPS15_LDO22, 120 S2MPS15_LDO22,
121 S2MPS15_LDO23, 121 S2MPS15_LDO23,
122 S2MPS15_LDO24, 122 S2MPS15_LDO24,
123 S2MPS15_LDO25, 123 S2MPS15_LDO25,
124 S2MPS15_LDO26, 124 S2MPS15_LDO26,
125 S2MPS15_LDO27, 125 S2MPS15_LDO27,
126 S2MPS15_BUCK1, 126 S2MPS15_BUCK1,
127 S2MPS15_BUCK2, 127 S2MPS15_BUCK2,
128 S2MPS15_BUCK3, 128 S2MPS15_BUCK3,
129 S2MPS15_BUCK4, 129 S2MPS15_BUCK4,
130 S2MPS15_BUCK5, 130 S2MPS15_BUCK5,
131 S2MPS15_BUCK6, 131 S2MPS15_BUCK6,
132 S2MPS15_BUCK7, 132 S2MPS15_BUCK7,
133 S2MPS15_BUCK8, 133 S2MPS15_BUCK8,
134 S2MPS15_BUCK9, 134 S2MPS15_BUCK9,
135 S2MPS15_BUCK10, 135 S2MPS15_BUCK10,
136 S2MPS15_BUCK11, 136 S2MPS15_BUCK11,
137 S2MPS15_REGULATOR_MAX, 137 S2MPS15_REGULATOR_MAX,
138 }; 138 };
139 139
140 #define S2MPS15_LDO_VSEL_MASK (0x3F) 140 #define S2MPS15_LDO_VSEL_MASK (0x3F)
141 #define S2MPS15_BUCK_VSEL_MASK (0xFF) 141 #define S2MPS15_BUCK_VSEL_MASK (0xFF)
142 142
143 #define S2MPS15_ENABLE_SHIFT (0x06) 143 #define S2MPS15_ENABLE_SHIFT (0x06)
144 #define S2MPS15_ENABLE_MASK (0x03 144 #define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
145 145
146 #define S2MPS15_LDO_N_VOLTAGES (S2MPS 146 #define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
147 #define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_ 147 #define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
148 148
149 #endif /* __LINUX_MFD_S2MPS15_H */ 149 #endif /* __LINUX_MFD_S2MPS15_H */
150 150
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