1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* 2 /*
3 * Atmel SMC (Static Memory Controller) regist 3 * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
4 * 4 *
5 * Copyright (C) 2014 Atmel 5 * Copyright (C) 2014 Atmel
6 * Copyright (C) 2014 Free Electrons 6 * Copyright (C) 2014 Free Electrons
7 * 7 *
8 * Author: Boris Brezillon <boris.brezillon@fr 8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
9 */ 9 */
10 10
11 #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 11 #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
12 #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ 12 #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
13 13
14 #include <linux/kernel.h> 14 #include <linux/kernel.h>
15 #include <linux/of.h> 15 #include <linux/of.h>
16 #include <linux/regmap.h> 16 #include <linux/regmap.h>
17 17
18 #define ATMEL_SMC_SETUP(cs) 18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
19 #define ATMEL_HSMC_SETUP(layout, cs) 19 #define ATMEL_HSMC_SETUP(layout, cs) \
20 ((layout)->timing_regs_offset + ((cs) 20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) 21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
22 #define ATMEL_HSMC_PULSE(layout, cs) 22 #define ATMEL_HSMC_PULSE(layout, cs) \
23 ((layout)->timing_regs_offset + ((cs) 23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) 24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
25 #define ATMEL_HSMC_CYCLE(layout, cs) 25 #define ATMEL_HSMC_CYCLE(layout, cs) \
26 ((layout)->timing_regs_offset + ((cs) 26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
27 #define ATMEL_SMC_NWE_SHIFT 27 #define ATMEL_SMC_NWE_SHIFT 0
28 #define ATMEL_SMC_NCS_WR_SHIFT 28 #define ATMEL_SMC_NCS_WR_SHIFT 8
29 #define ATMEL_SMC_NRD_SHIFT 29 #define ATMEL_SMC_NRD_SHIFT 16
30 #define ATMEL_SMC_NCS_RD_SHIFT 30 #define ATMEL_SMC_NCS_RD_SHIFT 24
31 31
32 #define ATMEL_SMC_MODE(cs) 32 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
33 #define ATMEL_HSMC_MODE(layout, cs) 33 #define ATMEL_HSMC_MODE(layout, cs) \
34 ((layout)->timing_regs_offset + ((cs) 34 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
35 #define ATMEL_SMC_MODE_READMODE_MASK 35 #define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
36 #define ATMEL_SMC_MODE_READMODE_NCS 36 #define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
37 #define ATMEL_SMC_MODE_READMODE_NRD 37 #define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
38 #define ATMEL_SMC_MODE_WRITEMODE_MASK 38 #define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
39 #define ATMEL_SMC_MODE_WRITEMODE_NCS 39 #define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
40 #define ATMEL_SMC_MODE_WRITEMODE_NWE 40 #define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
41 #define ATMEL_SMC_MODE_EXNWMODE_MASK 41 #define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
42 #define ATMEL_SMC_MODE_EXNWMODE_DISABLE 42 #define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
43 #define ATMEL_SMC_MODE_EXNWMODE_FROZEN 43 #define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
44 #define ATMEL_SMC_MODE_EXNWMODE_READY 44 #define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
45 #define ATMEL_SMC_MODE_BAT_MASK 45 #define ATMEL_SMC_MODE_BAT_MASK BIT(8)
46 #define ATMEL_SMC_MODE_BAT_SELECT 46 #define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
47 #define ATMEL_SMC_MODE_BAT_WRITE 47 #define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
48 #define ATMEL_SMC_MODE_DBW_MASK 48 #define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
49 #define ATMEL_SMC_MODE_DBW_8 49 #define ATMEL_SMC_MODE_DBW_8 (0 << 12)
50 #define ATMEL_SMC_MODE_DBW_16 50 #define ATMEL_SMC_MODE_DBW_16 (1 << 12)
51 #define ATMEL_SMC_MODE_DBW_32 51 #define ATMEL_SMC_MODE_DBW_32 (2 << 12)
52 #define ATMEL_SMC_MODE_TDF_MASK 52 #define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
53 #define ATMEL_SMC_MODE_TDF(x) 53 #define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
54 #define ATMEL_SMC_MODE_TDF_MAX 54 #define ATMEL_SMC_MODE_TDF_MAX 16
55 #define ATMEL_SMC_MODE_TDF_MIN 55 #define ATMEL_SMC_MODE_TDF_MIN 1
56 #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED 56 #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
57 #define ATMEL_SMC_MODE_PMEN 57 #define ATMEL_SMC_MODE_PMEN BIT(24)
58 #define ATMEL_SMC_MODE_PS_MASK 58 #define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
59 #define ATMEL_SMC_MODE_PS_4 59 #define ATMEL_SMC_MODE_PS_4 (0 << 28)
60 #define ATMEL_SMC_MODE_PS_8 60 #define ATMEL_SMC_MODE_PS_8 (1 << 28)
61 #define ATMEL_SMC_MODE_PS_16 61 #define ATMEL_SMC_MODE_PS_16 (2 << 28)
62 #define ATMEL_SMC_MODE_PS_32 62 #define ATMEL_SMC_MODE_PS_32 (3 << 28)
63 63
64 #define ATMEL_HSMC_TIMINGS(layout, cs) 64 #define ATMEL_HSMC_TIMINGS(layout, cs) \
65 ((layout)->timing_regs_offset + ((cs) 65 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
66 #define ATMEL_HSMC_TIMINGS_OCMS 66 #define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
67 #define ATMEL_HSMC_TIMINGS_RBNSEL(x) 67 #define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
68 #define ATMEL_HSMC_TIMINGS_NFSEL 68 #define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
69 #define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 69 #define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
70 #define ATMEL_HSMC_TIMINGS_TADL_SHIFT 70 #define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
71 #define ATMEL_HSMC_TIMINGS_TAR_SHIFT 71 #define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
72 #define ATMEL_HSMC_TIMINGS_TRR_SHIFT 72 #define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
73 #define ATMEL_HSMC_TIMINGS_TWB_SHIFT 73 #define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
74 74
75 struct atmel_hsmc_reg_layout { 75 struct atmel_hsmc_reg_layout {
76 unsigned int timing_regs_offset; 76 unsigned int timing_regs_offset;
77 }; 77 };
78 78
79 /** 79 /**
80 * struct atmel_smc_cs_conf - SMC CS config as 80 * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
81 * @setup: NCS/NWE/NRD setup timings (not appl 81 * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
82 * @pulse: NCS/NWE/NRD pulse timings (not appl 82 * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
83 * @cycle: NWE/NRD cycle timings (not applicab 83 * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
84 * @timings: advanced NAND related timings (on 84 * @timings: advanced NAND related timings (only applicable to HSMC)
85 * @mode: all kind of config parameters (see t 85 * @mode: all kind of config parameters (see the fields definition above).
86 * The mode fields are different on at9 86 * The mode fields are different on at91rm9200
87 */ 87 */
88 struct atmel_smc_cs_conf { 88 struct atmel_smc_cs_conf {
89 u32 setup; 89 u32 setup;
90 u32 pulse; 90 u32 pulse;
91 u32 cycle; 91 u32 cycle;
92 u32 timings; 92 u32 timings;
93 u32 mode; 93 u32 mode;
94 }; 94 };
95 95
96 void atmel_smc_cs_conf_init(struct atmel_smc_c 96 void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
97 int atmel_smc_cs_conf_set_timing(struct atmel_ 97 int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
98 unsigned int 98 unsigned int shift,
99 unsigned int 99 unsigned int ncycles);
100 int atmel_smc_cs_conf_set_setup(struct atmel_s 100 int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
101 unsigned int s 101 unsigned int shift, unsigned int ncycles);
102 int atmel_smc_cs_conf_set_pulse(struct atmel_s 102 int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
103 unsigned int s 103 unsigned int shift, unsigned int ncycles);
104 int atmel_smc_cs_conf_set_cycle(struct atmel_s 104 int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
105 unsigned int s 105 unsigned int shift, unsigned int ncycles);
106 void atmel_smc_cs_conf_apply(struct regmap *re 106 void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
107 const struct atme 107 const struct atmel_smc_cs_conf *conf);
108 void atmel_hsmc_cs_conf_apply(struct regmap *r 108 void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
109 const struct atm 109 const struct atmel_hsmc_reg_layout *reglayout,
110 int cs, const st 110 int cs, const struct atmel_smc_cs_conf *conf);
111 void atmel_smc_cs_conf_get(struct regmap *regm 111 void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
112 struct atmel_smc_cs 112 struct atmel_smc_cs_conf *conf);
113 void atmel_hsmc_cs_conf_get(struct regmap *reg 113 void atmel_hsmc_cs_conf_get(struct regmap *regmap,
114 const struct atmel 114 const struct atmel_hsmc_reg_layout *reglayout,
115 int cs, struct atm 115 int cs, struct atmel_smc_cs_conf *conf);
116 const struct atmel_hsmc_reg_layout * 116 const struct atmel_hsmc_reg_layout *
117 atmel_hsmc_get_reg_layout(struct device_node * 117 atmel_hsmc_get_reg_layout(struct device_node *np);
118 118
119 #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ 119 #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */
120 120
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