1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * Copyright (C) 2015 Texas Instruments Incorp 3 * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com/
4 * Andrew F. Davis <afd@ti.com> 4 * Andrew F. Davis <afd@ti.com>
5 * 5 *
6 * Based on the TPS65912 driver 6 * Based on the TPS65912 driver
7 */ 7 */
8 8
9 #ifndef __LINUX_MFD_TPS65086_H 9 #ifndef __LINUX_MFD_TPS65086_H
10 #define __LINUX_MFD_TPS65086_H 10 #define __LINUX_MFD_TPS65086_H
11 11
12 #include <linux/device.h> 12 #include <linux/device.h>
13 #include <linux/regmap.h> 13 #include <linux/regmap.h>
14 14
15 /* List of registers for TPS65086 */ 15 /* List of registers for TPS65086 */
16 #define TPS65086_DEVICEID1 0x00 16 #define TPS65086_DEVICEID1 0x00
17 #define TPS65086_DEVICEID2 0x01 17 #define TPS65086_DEVICEID2 0x01
18 #define TPS65086_IRQ 0x02 18 #define TPS65086_IRQ 0x02
19 #define TPS65086_IRQ_MASK 0x03 19 #define TPS65086_IRQ_MASK 0x03
20 #define TPS65086_PMICSTAT 0x04 20 #define TPS65086_PMICSTAT 0x04
21 #define TPS65086_SHUTDNSRC 0x05 21 #define TPS65086_SHUTDNSRC 0x05
22 #define TPS65086_BUCK1CTRL 0x20 22 #define TPS65086_BUCK1CTRL 0x20
23 #define TPS65086_BUCK2CTRL 0x21 23 #define TPS65086_BUCK2CTRL 0x21
24 #define TPS65086_BUCK3DECAY 0x22 24 #define TPS65086_BUCK3DECAY 0x22
25 #define TPS65086_BUCK3VID 0x23 25 #define TPS65086_BUCK3VID 0x23
26 #define TPS65086_BUCK3SLPCTRL 0x24 26 #define TPS65086_BUCK3SLPCTRL 0x24
27 #define TPS65086_BUCK4CTRL 0x25 27 #define TPS65086_BUCK4CTRL 0x25
28 #define TPS65086_BUCK5CTRL 0x26 28 #define TPS65086_BUCK5CTRL 0x26
29 #define TPS65086_BUCK6CTRL 0x27 29 #define TPS65086_BUCK6CTRL 0x27
30 #define TPS65086_LDOA2CTRL 0x28 30 #define TPS65086_LDOA2CTRL 0x28
31 #define TPS65086_LDOA3CTRL 0x29 31 #define TPS65086_LDOA3CTRL 0x29
32 #define TPS65086_DISCHCTRL1 0x40 32 #define TPS65086_DISCHCTRL1 0x40
33 #define TPS65086_DISCHCTRL2 0x41 33 #define TPS65086_DISCHCTRL2 0x41
34 #define TPS65086_DISCHCTRL3 0x42 34 #define TPS65086_DISCHCTRL3 0x42
35 #define TPS65086_PG_DELAY1 0x43 35 #define TPS65086_PG_DELAY1 0x43
36 #define TPS65086_FORCESHUTDN 0x91 36 #define TPS65086_FORCESHUTDN 0x91
37 #define TPS65086_BUCK1SLPCTRL 0x92 37 #define TPS65086_BUCK1SLPCTRL 0x92
38 #define TPS65086_BUCK2SLPCTRL 0x93 38 #define TPS65086_BUCK2SLPCTRL 0x93
39 #define TPS65086_BUCK4VID 0x94 39 #define TPS65086_BUCK4VID 0x94
40 #define TPS65086_BUCK4SLPVID 0x95 40 #define TPS65086_BUCK4SLPVID 0x95
41 #define TPS65086_BUCK5VID 0x96 41 #define TPS65086_BUCK5VID 0x96
42 #define TPS65086_BUCK5SLPVID 0x97 42 #define TPS65086_BUCK5SLPVID 0x97
43 #define TPS65086_BUCK6VID 0x98 43 #define TPS65086_BUCK6VID 0x98
44 #define TPS65086_BUCK6SLPVID 0x99 44 #define TPS65086_BUCK6SLPVID 0x99
45 #define TPS65086_LDOA2VID 0x9A 45 #define TPS65086_LDOA2VID 0x9A
46 #define TPS65086_LDOA3VID 0x9B 46 #define TPS65086_LDOA3VID 0x9B
47 #define TPS65086_BUCK123CTRL 0x9C 47 #define TPS65086_BUCK123CTRL 0x9C
48 #define TPS65086_PG_DELAY2 0x9D 48 #define TPS65086_PG_DELAY2 0x9D
49 #define TPS65086_PIN_EN_MASK1 0x9E 49 #define TPS65086_PIN_EN_MASK1 0x9E
50 #define TPS65086_PIN_EN_MASK2 0x9F 50 #define TPS65086_PIN_EN_MASK2 0x9F
51 #define TPS65086_SWVTT_EN 0x9F 51 #define TPS65086_SWVTT_EN 0x9F
52 #define TPS65086_PIN_EN_OVR1 0xA0 52 #define TPS65086_PIN_EN_OVR1 0xA0
53 #define TPS65086_PIN_EN_OVR2 0xA1 53 #define TPS65086_PIN_EN_OVR2 0xA1
54 #define TPS65086_GPOCTRL 0xA1 54 #define TPS65086_GPOCTRL 0xA1
55 #define TPS65086_PWR_FAULT_MASK1 0xA2 55 #define TPS65086_PWR_FAULT_MASK1 0xA2
56 #define TPS65086_PWR_FAULT_MASK2 0xA3 56 #define TPS65086_PWR_FAULT_MASK2 0xA3
57 #define TPS65086_GPO1PG_CTRL1 0xA4 57 #define TPS65086_GPO1PG_CTRL1 0xA4
58 #define TPS65086_GPO1PG_CTRL2 0xA5 58 #define TPS65086_GPO1PG_CTRL2 0xA5
59 #define TPS65086_GPO4PG_CTRL1 0xA6 59 #define TPS65086_GPO4PG_CTRL1 0xA6
60 #define TPS65086_GPO4PG_CTRL2 0xA7 60 #define TPS65086_GPO4PG_CTRL2 0xA7
61 #define TPS65086_GPO2PG_CTRL1 0xA8 61 #define TPS65086_GPO2PG_CTRL1 0xA8
62 #define TPS65086_GPO2PG_CTRL2 0xA9 62 #define TPS65086_GPO2PG_CTRL2 0xA9
63 #define TPS65086_GPO3PG_CTRL1 0xAA 63 #define TPS65086_GPO3PG_CTRL1 0xAA
64 #define TPS65086_GPO3PG_CTRL2 0xAB 64 #define TPS65086_GPO3PG_CTRL2 0xAB
65 #define TPS65086_LDOA1CTRL 0xAE 65 #define TPS65086_LDOA1CTRL 0xAE
66 #define TPS65086_PG_STATUS1 0xB0 66 #define TPS65086_PG_STATUS1 0xB0
67 #define TPS65086_PG_STATUS2 0xB1 67 #define TPS65086_PG_STATUS2 0xB1
68 #define TPS65086_PWR_FAULT_STATUS1 0xB2 68 #define TPS65086_PWR_FAULT_STATUS1 0xB2
69 #define TPS65086_PWR_FAULT_STATUS2 0xB3 69 #define TPS65086_PWR_FAULT_STATUS2 0xB3
70 #define TPS65086_TEMPCRIT 0xB4 70 #define TPS65086_TEMPCRIT 0xB4
71 #define TPS65086_TEMPHOT 0xB5 71 #define TPS65086_TEMPHOT 0xB5
72 #define TPS65086_OC_STATUS 0xB6 72 #define TPS65086_OC_STATUS 0xB6
73 73
74 /* IRQ Register field definitions */ 74 /* IRQ Register field definitions */
75 #define TPS65086_IRQ_DIETEMP_MASK BIT(0) 75 #define TPS65086_IRQ_DIETEMP_MASK BIT(0)
76 #define TPS65086_IRQ_SHUTDN_MASK BIT(3) 76 #define TPS65086_IRQ_SHUTDN_MASK BIT(3)
77 #define TPS65086_IRQ_FAULT_MASK BIT(7) 77 #define TPS65086_IRQ_FAULT_MASK BIT(7)
78 78
79 /* DEVICEID1 Register field definitions */ 79 /* DEVICEID1 Register field definitions */
80 #define TPS6508640_ID 0x00 80 #define TPS6508640_ID 0x00
81 #define TPS65086401_ID 0x01 81 #define TPS65086401_ID 0x01
82 #define TPS6508641_ID 0x10 82 #define TPS6508641_ID 0x10
83 #define TPS65086470_ID 0x70 83 #define TPS65086470_ID 0x70
84 84
85 /* DEVICEID2 Register field definitions */ 85 /* DEVICEID2 Register field definitions */
86 #define TPS65086_DEVICEID2_PART_MASK GENMAS 86 #define TPS65086_DEVICEID2_PART_MASK GENMASK(3, 0)
87 #define TPS65086_DEVICEID2_OTP_MASK GENMAS 87 #define TPS65086_DEVICEID2_OTP_MASK GENMASK(5, 4)
88 #define TPS65086_DEVICEID2_REV_MASK GENMAS 88 #define TPS65086_DEVICEID2_REV_MASK GENMASK(7, 6)
89 89
90 /* VID Masks */ 90 /* VID Masks */
91 #define BUCK_VID_MASK GENMAS 91 #define BUCK_VID_MASK GENMASK(7, 1)
92 #define VDOA1_VID_MASK GENMAS 92 #define VDOA1_VID_MASK GENMASK(4, 1)
93 #define VDOA23_VID_MASK GENMAS 93 #define VDOA23_VID_MASK GENMASK(3, 0)
94 94
95 /* Define the TPS65086 IRQ numbers */ 95 /* Define the TPS65086 IRQ numbers */
96 enum tps65086_irqs { 96 enum tps65086_irqs {
97 TPS65086_IRQ_DIETEMP, 97 TPS65086_IRQ_DIETEMP,
98 TPS65086_IRQ_SHUTDN, 98 TPS65086_IRQ_SHUTDN,
99 TPS65086_IRQ_FAULT, 99 TPS65086_IRQ_FAULT,
100 }; 100 };
101 101
102 struct tps65086_regulator_config; 102 struct tps65086_regulator_config;
103 103
104 /** 104 /**
105 * struct tps65086 - state holder for the tps6 105 * struct tps65086 - state holder for the tps65086 driver
106 * 106 *
107 * Device data may be used to access the TPS65 107 * Device data may be used to access the TPS65086 chip
108 */ 108 */
109 struct tps65086 { 109 struct tps65086 {
110 struct device *dev; 110 struct device *dev;
111 struct regmap *regmap; 111 struct regmap *regmap;
112 unsigned int chip_id; 112 unsigned int chip_id;
113 const struct tps65086_regulator_config 113 const struct tps65086_regulator_config *reg_config;
114 114
115 /* IRQ Data */ 115 /* IRQ Data */
116 int irq; 116 int irq;
117 struct regmap_irq_chip_data *irq_data; 117 struct regmap_irq_chip_data *irq_data;
118 }; 118 };
119 119
120 #endif /* __LINUX_MFD_TPS65086_H */ 120 #endif /* __LINUX_MFD_TPS65086_H */
121 121
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