1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * linux/mfd/tps65217.h 2 * linux/mfd/tps65217.h
4 * 3 *
5 * Functions to access TPS65217 power manageme 4 * Functions to access TPS65217 power management chip.
6 * 5 *
7 * Copyright (C) 2011 Texas Instruments Incorp 6 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or
>> 9 * modify it under the terms of the GNU General Public License as
>> 10 * published by the Free Software Foundation version 2.
>> 11 *
>> 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> 13 * kind, whether express or implied; without even the implied warranty
>> 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 15 * GNU General Public License for more details.
8 */ 16 */
9 17
10 #ifndef __LINUX_MFD_TPS65217_H 18 #ifndef __LINUX_MFD_TPS65217_H
11 #define __LINUX_MFD_TPS65217_H 19 #define __LINUX_MFD_TPS65217_H
12 20
13 #include <linux/i2c.h> 21 #include <linux/i2c.h>
14 #include <linux/regulator/driver.h> 22 #include <linux/regulator/driver.h>
15 #include <linux/regulator/machine.h> 23 #include <linux/regulator/machine.h>
16 24
17 /* TPS chip id list */ 25 /* TPS chip id list */
18 #define TPS65217 0xF0 26 #define TPS65217 0xF0
19 27
20 /* I2C ID for TPS65217 part */ 28 /* I2C ID for TPS65217 part */
21 #define TPS65217_I2C_ID 0x24 29 #define TPS65217_I2C_ID 0x24
22 30
23 /* All register addresses */ 31 /* All register addresses */
24 #define TPS65217_REG_CHIPID 0X00 32 #define TPS65217_REG_CHIPID 0X00
25 #define TPS65217_REG_PPATH 0X01 33 #define TPS65217_REG_PPATH 0X01
26 #define TPS65217_REG_INT 0X02 34 #define TPS65217_REG_INT 0X02
27 #define TPS65217_REG_CHGCONFIG0 0X03 35 #define TPS65217_REG_CHGCONFIG0 0X03
28 #define TPS65217_REG_CHGCONFIG1 0X04 36 #define TPS65217_REG_CHGCONFIG1 0X04
29 #define TPS65217_REG_CHGCONFIG2 0X05 37 #define TPS65217_REG_CHGCONFIG2 0X05
30 #define TPS65217_REG_CHGCONFIG3 0X06 38 #define TPS65217_REG_CHGCONFIG3 0X06
31 #define TPS65217_REG_WLEDCTRL1 0X07 39 #define TPS65217_REG_WLEDCTRL1 0X07
32 #define TPS65217_REG_WLEDCTRL2 0X08 40 #define TPS65217_REG_WLEDCTRL2 0X08
33 #define TPS65217_REG_MUXCTRL 0X09 41 #define TPS65217_REG_MUXCTRL 0X09
34 #define TPS65217_REG_STATUS 0X0A 42 #define TPS65217_REG_STATUS 0X0A
35 #define TPS65217_REG_PASSWORD 0X0B 43 #define TPS65217_REG_PASSWORD 0X0B
36 #define TPS65217_REG_PGOOD 0X0C 44 #define TPS65217_REG_PGOOD 0X0C
37 #define TPS65217_REG_DEFPG 0X0D 45 #define TPS65217_REG_DEFPG 0X0D
38 #define TPS65217_REG_DEFDCDC1 0X0E 46 #define TPS65217_REG_DEFDCDC1 0X0E
39 #define TPS65217_REG_DEFDCDC2 0X0F 47 #define TPS65217_REG_DEFDCDC2 0X0F
40 #define TPS65217_REG_DEFDCDC3 0X10 48 #define TPS65217_REG_DEFDCDC3 0X10
41 #define TPS65217_REG_DEFSLEW 0X11 49 #define TPS65217_REG_DEFSLEW 0X11
42 #define TPS65217_REG_DEFLDO1 0X12 50 #define TPS65217_REG_DEFLDO1 0X12
43 #define TPS65217_REG_DEFLDO2 0X13 51 #define TPS65217_REG_DEFLDO2 0X13
44 #define TPS65217_REG_DEFLS1 0X14 52 #define TPS65217_REG_DEFLS1 0X14
45 #define TPS65217_REG_DEFLS2 0X15 53 #define TPS65217_REG_DEFLS2 0X15
46 #define TPS65217_REG_ENABLE 0X16 54 #define TPS65217_REG_ENABLE 0X16
47 #define TPS65217_REG_DEFUVLO 0X18 55 #define TPS65217_REG_DEFUVLO 0X18
48 #define TPS65217_REG_SEQ1 0X19 56 #define TPS65217_REG_SEQ1 0X19
49 #define TPS65217_REG_SEQ2 0X1A 57 #define TPS65217_REG_SEQ2 0X1A
50 #define TPS65217_REG_SEQ3 0X1B 58 #define TPS65217_REG_SEQ3 0X1B
51 #define TPS65217_REG_SEQ4 0X1C 59 #define TPS65217_REG_SEQ4 0X1C
52 #define TPS65217_REG_SEQ5 0X1D 60 #define TPS65217_REG_SEQ5 0X1D
53 #define TPS65217_REG_SEQ6 0X1E 61 #define TPS65217_REG_SEQ6 0X1E
54 62
55 #define TPS65217_REG_MAX TPS652 63 #define TPS65217_REG_MAX TPS65217_REG_SEQ6
56 64
57 /* Register field definitions */ 65 /* Register field definitions */
58 #define TPS65217_CHIPID_CHIP_MASK 0xF0 66 #define TPS65217_CHIPID_CHIP_MASK 0xF0
59 #define TPS65217_CHIPID_REV_MASK 0x0F 67 #define TPS65217_CHIPID_REV_MASK 0x0F
60 68
61 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7) 69 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
62 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6) 70 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
63 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5) 71 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
64 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4) 72 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
65 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C 73 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
66 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03 74 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
67 75
68 #define TPS65217_INT_PBM BIT(6) 76 #define TPS65217_INT_PBM BIT(6)
69 #define TPS65217_INT_ACM BIT(5) 77 #define TPS65217_INT_ACM BIT(5)
70 #define TPS65217_INT_USBM BIT(4) 78 #define TPS65217_INT_USBM BIT(4)
71 #define TPS65217_INT_PBI BIT(2) 79 #define TPS65217_INT_PBI BIT(2)
72 #define TPS65217_INT_ACI BIT(1) 80 #define TPS65217_INT_ACI BIT(1)
73 #define TPS65217_INT_USBI BIT(0) 81 #define TPS65217_INT_USBI BIT(0)
74 #define TPS65217_INT_SHIFT 4 82 #define TPS65217_INT_SHIFT 4
75 #define TPS65217_INT_MASK (TPS65 83 #define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \
76 TPS652 84 TPS65217_INT_USBM)
77 85
78 #define TPS65217_CHGCONFIG0_TREG BIT(7) 86 #define TPS65217_CHGCONFIG0_TREG BIT(7)
79 #define TPS65217_CHGCONFIG0_DPPM BIT(6) 87 #define TPS65217_CHGCONFIG0_DPPM BIT(6)
80 #define TPS65217_CHGCONFIG0_TSUSP BIT(5) 88 #define TPS65217_CHGCONFIG0_TSUSP BIT(5)
81 #define TPS65217_CHGCONFIG0_TERMI BIT(4) 89 #define TPS65217_CHGCONFIG0_TERMI BIT(4)
82 #define TPS65217_CHGCONFIG0_ACTIVE BIT(3) 90 #define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
83 #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) 91 #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
84 #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) 92 #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
85 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0) 93 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
86 94
87 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0 95 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
88 #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) 96 #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
89 #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) 97 #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
90 #define TPS65217_CHGCONFIG1_RESET BIT(3) 98 #define TPS65217_CHGCONFIG1_RESET BIT(3)
91 #define TPS65217_CHGCONFIG1_TERM BIT(2) 99 #define TPS65217_CHGCONFIG1_TERM BIT(2)
92 #define TPS65217_CHGCONFIG1_SUSP BIT(1) 100 #define TPS65217_CHGCONFIG1_SUSP BIT(1)
93 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0) 101 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
94 102
95 #define TPS65217_CHGCONFIG2_DYNTMR BIT(7) 103 #define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
96 #define TPS65217_CHGCONFIG2_VPREGHG BIT(6) 104 #define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
97 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30 105 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
98 106
99 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0 107 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
100 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30 108 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
101 #define TPS65217_CHGCONFIG2_PCHRGT BIT(3) 109 #define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
102 #define TPS65217_CHGCONFIG2_TERMIF 0x06 110 #define TPS65217_CHGCONFIG2_TERMIF 0x06
103 #define TPS65217_CHGCONFIG2_TRANGE BIT(0) 111 #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
104 112
105 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) 113 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
106 #define TPS65217_WLEDCTRL1_ISEL BIT(2) 114 #define TPS65217_WLEDCTRL1_ISEL BIT(2)
107 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03 115 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
108 116
109 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F 117 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
110 118
111 #define TPS65217_MUXCTRL_MUX_MASK 0x07 119 #define TPS65217_MUXCTRL_MUX_MASK 0x07
112 120
113 #define TPS65217_STATUS_OFF BIT(7) 121 #define TPS65217_STATUS_OFF BIT(7)
114 #define TPS65217_STATUS_ACPWR BIT(3) 122 #define TPS65217_STATUS_ACPWR BIT(3)
115 #define TPS65217_STATUS_USBPWR BIT(2) 123 #define TPS65217_STATUS_USBPWR BIT(2)
116 #define TPS65217_STATUS_PB BIT(0) 124 #define TPS65217_STATUS_PB BIT(0)
117 125
118 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D 126 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
119 127
120 #define TPS65217_PGOOD_LDO3_PG BIT(6) 128 #define TPS65217_PGOOD_LDO3_PG BIT(6)
121 #define TPS65217_PGOOD_LDO4_PG BIT(5) 129 #define TPS65217_PGOOD_LDO4_PG BIT(5)
122 #define TPS65217_PGOOD_DC1_PG BIT(4) 130 #define TPS65217_PGOOD_DC1_PG BIT(4)
123 #define TPS65217_PGOOD_DC2_PG BIT(3) 131 #define TPS65217_PGOOD_DC2_PG BIT(3)
124 #define TPS65217_PGOOD_DC3_PG BIT(2) 132 #define TPS65217_PGOOD_DC3_PG BIT(2)
125 #define TPS65217_PGOOD_LDO1_PG BIT(1) 133 #define TPS65217_PGOOD_LDO1_PG BIT(1)
126 #define TPS65217_PGOOD_LDO2_PG BIT(0) 134 #define TPS65217_PGOOD_LDO2_PG BIT(0)
127 135
128 #define TPS65217_DEFPG_LDO1PGM BIT(3) 136 #define TPS65217_DEFPG_LDO1PGM BIT(3)
129 #define TPS65217_DEFPG_LDO2PGM BIT(2) 137 #define TPS65217_DEFPG_LDO2PGM BIT(2)
130 #define TPS65217_DEFPG_PGDLY_MASK 0x03 138 #define TPS65217_DEFPG_PGDLY_MASK 0x03
131 139
132 #define TPS65217_DEFDCDCX_XADJX BIT(7) 140 #define TPS65217_DEFDCDCX_XADJX BIT(7)
133 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F 141 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
134 142
135 #define TPS65217_DEFSLEW_GO BIT(7) 143 #define TPS65217_DEFSLEW_GO BIT(7)
136 #define TPS65217_DEFSLEW_GODSBL BIT(6) 144 #define TPS65217_DEFSLEW_GODSBL BIT(6)
137 #define TPS65217_DEFSLEW_PFM_EN1 BIT(5) 145 #define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
138 #define TPS65217_DEFSLEW_PFM_EN2 BIT(4) 146 #define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
139 #define TPS65217_DEFSLEW_PFM_EN3 BIT(3) 147 #define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
140 #define TPS65217_DEFSLEW_SLEW_MASK 0x07 148 #define TPS65217_DEFSLEW_SLEW_MASK 0x07
141 149
142 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F 150 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
143 151
144 #define TPS65217_DEFLDO2_TRACK BIT(6) 152 #define TPS65217_DEFLDO2_TRACK BIT(6)
145 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F 153 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
146 154
147 #define TPS65217_DEFLDO3_LDO3_EN BIT(5) 155 #define TPS65217_DEFLDO3_LDO3_EN BIT(5)
148 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F 156 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
149 157
150 #define TPS65217_DEFLDO4_LDO4_EN BIT(5) 158 #define TPS65217_DEFLDO4_LDO4_EN BIT(5)
151 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F 159 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
152 160
153 #define TPS65217_ENABLE_LS1_EN BIT(6) 161 #define TPS65217_ENABLE_LS1_EN BIT(6)
154 #define TPS65217_ENABLE_LS2_EN BIT(5) 162 #define TPS65217_ENABLE_LS2_EN BIT(5)
155 #define TPS65217_ENABLE_DC1_EN BIT(4) 163 #define TPS65217_ENABLE_DC1_EN BIT(4)
156 #define TPS65217_ENABLE_DC2_EN BIT(3) 164 #define TPS65217_ENABLE_DC2_EN BIT(3)
157 #define TPS65217_ENABLE_DC3_EN BIT(2) 165 #define TPS65217_ENABLE_DC3_EN BIT(2)
158 #define TPS65217_ENABLE_LDO1_EN BIT(1) 166 #define TPS65217_ENABLE_LDO1_EN BIT(1)
159 #define TPS65217_ENABLE_LDO2_EN BIT(0) 167 #define TPS65217_ENABLE_LDO2_EN BIT(0)
160 168
161 #define TPS65217_DEFUVLO_UVLOHYS BIT(2) 169 #define TPS65217_DEFUVLO_UVLOHYS BIT(2)
162 #define TPS65217_DEFUVLO_UVLO_MASK 0x03 170 #define TPS65217_DEFUVLO_UVLO_MASK 0x03
163 171
164 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0 172 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
165 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F 173 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
166 174
167 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0 175 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
168 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F 176 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
169 177
170 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0 178 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
171 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F 179 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
172 180
173 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0 181 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
174 182
175 #define TPS65217_SEQ5_DLY1_MASK 0xC0 183 #define TPS65217_SEQ5_DLY1_MASK 0xC0
176 #define TPS65217_SEQ5_DLY2_MASK 0x30 184 #define TPS65217_SEQ5_DLY2_MASK 0x30
177 #define TPS65217_SEQ5_DLY3_MASK 0x0C 185 #define TPS65217_SEQ5_DLY3_MASK 0x0C
178 #define TPS65217_SEQ5_DLY4_MASK 0x03 186 #define TPS65217_SEQ5_DLY4_MASK 0x03
179 187
180 #define TPS65217_SEQ6_DLY5_MASK 0xC0 188 #define TPS65217_SEQ6_DLY5_MASK 0xC0
181 #define TPS65217_SEQ6_DLY6_MASK 0x30 189 #define TPS65217_SEQ6_DLY6_MASK 0x30
182 #define TPS65217_SEQ6_SEQUP BIT(2) 190 #define TPS65217_SEQ6_SEQUP BIT(2)
183 #define TPS65217_SEQ6_SEQDWN BIT(1) 191 #define TPS65217_SEQ6_SEQDWN BIT(1)
184 #define TPS65217_SEQ6_INSTDWN BIT(0) 192 #define TPS65217_SEQ6_INSTDWN BIT(0)
185 193
186 #define TPS65217_MAX_REGISTER 0x1E 194 #define TPS65217_MAX_REGISTER 0x1E
187 #define TPS65217_PROTECT_NONE 0 195 #define TPS65217_PROTECT_NONE 0
188 #define TPS65217_PROTECT_L1 1 196 #define TPS65217_PROTECT_L1 1
189 #define TPS65217_PROTECT_L2 2 197 #define TPS65217_PROTECT_L2 2
190 198
191 199
192 enum tps65217_regulator_id { 200 enum tps65217_regulator_id {
193 /* DCDC's */ 201 /* DCDC's */
194 TPS65217_DCDC_1, 202 TPS65217_DCDC_1,
195 TPS65217_DCDC_2, 203 TPS65217_DCDC_2,
196 TPS65217_DCDC_3, 204 TPS65217_DCDC_3,
197 /* LDOs */ 205 /* LDOs */
198 TPS65217_LDO_1, 206 TPS65217_LDO_1,
199 TPS65217_LDO_2, 207 TPS65217_LDO_2,
200 TPS65217_LDO_3, 208 TPS65217_LDO_3,
201 TPS65217_LDO_4, 209 TPS65217_LDO_4,
202 }; 210 };
203 211
204 #define TPS65217_MAX_REG_ID TPS652 212 #define TPS65217_MAX_REG_ID TPS65217_LDO_4
205 213
206 /* Number of step-down converters available */ 214 /* Number of step-down converters available */
207 #define TPS65217_NUM_DCDC 3 215 #define TPS65217_NUM_DCDC 3
208 /* Number of LDO voltage regulators available 216 /* Number of LDO voltage regulators available */
209 #define TPS65217_NUM_LDO 4 217 #define TPS65217_NUM_LDO 4
210 /* Number of total regulators available */ 218 /* Number of total regulators available */
211 #define TPS65217_NUM_REGULATOR (TPS65 219 #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
212 220
213 enum tps65217_bl_isel { 221 enum tps65217_bl_isel {
214 TPS65217_BL_ISET1 = 1, 222 TPS65217_BL_ISET1 = 1,
215 TPS65217_BL_ISET2, 223 TPS65217_BL_ISET2,
216 }; 224 };
217 225
218 enum tps65217_bl_fdim { 226 enum tps65217_bl_fdim {
219 TPS65217_BL_FDIM_100HZ, 227 TPS65217_BL_FDIM_100HZ,
220 TPS65217_BL_FDIM_200HZ, 228 TPS65217_BL_FDIM_200HZ,
221 TPS65217_BL_FDIM_500HZ, 229 TPS65217_BL_FDIM_500HZ,
222 TPS65217_BL_FDIM_1000HZ, 230 TPS65217_BL_FDIM_1000HZ,
223 }; 231 };
224 232
225 struct tps65217_bl_pdata { 233 struct tps65217_bl_pdata {
226 enum tps65217_bl_isel isel; 234 enum tps65217_bl_isel isel;
227 enum tps65217_bl_fdim fdim; 235 enum tps65217_bl_fdim fdim;
228 int dft_brightness; 236 int dft_brightness;
229 }; 237 };
230 238
231 /* Interrupt numbers */ 239 /* Interrupt numbers */
232 #define TPS65217_IRQ_USB 0 240 #define TPS65217_IRQ_USB 0
233 #define TPS65217_IRQ_AC 1 241 #define TPS65217_IRQ_AC 1
234 #define TPS65217_IRQ_PB 2 242 #define TPS65217_IRQ_PB 2
235 #define TPS65217_NUM_IRQ 3 243 #define TPS65217_NUM_IRQ 3
236 244
237 /** 245 /**
238 * struct tps65217_board - packages regulator 246 * struct tps65217_board - packages regulator init data
239 * @tps65217_regulator_data: regulator initial 247 * @tps65217_regulator_data: regulator initialization values
240 * 248 *
241 * Board data may be used to initialize regula 249 * Board data may be used to initialize regulator.
242 */ 250 */
243 struct tps65217_board { 251 struct tps65217_board {
244 struct regulator_init_data *tps65217_i 252 struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
245 struct device_node *of_node[TPS65217_N 253 struct device_node *of_node[TPS65217_NUM_REGULATOR];
246 struct tps65217_bl_pdata *bl_pdata; 254 struct tps65217_bl_pdata *bl_pdata;
247 }; 255 };
248 256
249 /** 257 /**
250 * struct tps65217 - tps65217 sub-driver chip 258 * struct tps65217 - tps65217 sub-driver chip access routines
251 * 259 *
252 * Device data may be used to access the TPS65 260 * Device data may be used to access the TPS65217 chip
253 */ 261 */
254 262
255 struct tps65217 { 263 struct tps65217 {
256 struct device *dev; 264 struct device *dev;
257 struct tps65217_board *pdata; 265 struct tps65217_board *pdata;
258 struct regulator_desc desc[TPS65217_NU 266 struct regulator_desc desc[TPS65217_NUM_REGULATOR];
259 struct regmap *regmap; 267 struct regmap *regmap;
260 u8 *strobes; 268 u8 *strobes;
261 struct irq_domain *irq_domain; 269 struct irq_domain *irq_domain;
262 struct mutex irq_lock; 270 struct mutex irq_lock;
263 u8 irq_mask; 271 u8 irq_mask;
264 int irq; 272 int irq;
265 }; 273 };
266 274
267 static inline struct tps65217 *dev_to_tps65217 275 static inline struct tps65217 *dev_to_tps65217(struct device *dev)
268 { 276 {
269 return dev_get_drvdata(dev); 277 return dev_get_drvdata(dev);
270 } 278 }
271 279
272 int tps65217_reg_read(struct tps65217 *tps, un 280 int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
273 unsign 281 unsigned int *val);
274 int tps65217_reg_write(struct tps65217 *tps, u 282 int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
275 unsigned int val, unsi 283 unsigned int val, unsigned int level);
276 int tps65217_set_bits(struct tps65217 *tps, un 284 int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
277 unsigned int mask, unsigned in 285 unsigned int mask, unsigned int val, unsigned int level);
278 int tps65217_clear_bits(struct tps65217 *tps, 286 int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
279 unsigned int mask, unsigned in 287 unsigned int mask, unsigned int level);
280 288
281 #endif /* __LINUX_MFD_TPS65217_H */ 289 #endif /* __LINUX_MFD_TPS65217_H */
282 290
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