1 /* SPDX-License-Identifier: GPL-2.0-only */ 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* 2 /*
3 * linux/mfd/tps65217.h 3 * linux/mfd/tps65217.h
4 * 4 *
5 * Functions to access TPS65217 power manageme 5 * Functions to access TPS65217 power management chip.
6 * 6 *
7 * Copyright (C) 2011 Texas Instruments Incorp 7 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
8 */ 8 */
9 9
10 #ifndef __LINUX_MFD_TPS65217_H 10 #ifndef __LINUX_MFD_TPS65217_H
11 #define __LINUX_MFD_TPS65217_H 11 #define __LINUX_MFD_TPS65217_H
12 12
13 #include <linux/i2c.h> 13 #include <linux/i2c.h>
14 #include <linux/regulator/driver.h> 14 #include <linux/regulator/driver.h>
15 #include <linux/regulator/machine.h> 15 #include <linux/regulator/machine.h>
16 16
17 /* TPS chip id list */ 17 /* TPS chip id list */
18 #define TPS65217 0xF0 18 #define TPS65217 0xF0
19 19
20 /* I2C ID for TPS65217 part */ 20 /* I2C ID for TPS65217 part */
21 #define TPS65217_I2C_ID 0x24 21 #define TPS65217_I2C_ID 0x24
22 22
23 /* All register addresses */ 23 /* All register addresses */
24 #define TPS65217_REG_CHIPID 0X00 24 #define TPS65217_REG_CHIPID 0X00
25 #define TPS65217_REG_PPATH 0X01 25 #define TPS65217_REG_PPATH 0X01
26 #define TPS65217_REG_INT 0X02 26 #define TPS65217_REG_INT 0X02
27 #define TPS65217_REG_CHGCONFIG0 0X03 27 #define TPS65217_REG_CHGCONFIG0 0X03
28 #define TPS65217_REG_CHGCONFIG1 0X04 28 #define TPS65217_REG_CHGCONFIG1 0X04
29 #define TPS65217_REG_CHGCONFIG2 0X05 29 #define TPS65217_REG_CHGCONFIG2 0X05
30 #define TPS65217_REG_CHGCONFIG3 0X06 30 #define TPS65217_REG_CHGCONFIG3 0X06
31 #define TPS65217_REG_WLEDCTRL1 0X07 31 #define TPS65217_REG_WLEDCTRL1 0X07
32 #define TPS65217_REG_WLEDCTRL2 0X08 32 #define TPS65217_REG_WLEDCTRL2 0X08
33 #define TPS65217_REG_MUXCTRL 0X09 33 #define TPS65217_REG_MUXCTRL 0X09
34 #define TPS65217_REG_STATUS 0X0A 34 #define TPS65217_REG_STATUS 0X0A
35 #define TPS65217_REG_PASSWORD 0X0B 35 #define TPS65217_REG_PASSWORD 0X0B
36 #define TPS65217_REG_PGOOD 0X0C 36 #define TPS65217_REG_PGOOD 0X0C
37 #define TPS65217_REG_DEFPG 0X0D 37 #define TPS65217_REG_DEFPG 0X0D
38 #define TPS65217_REG_DEFDCDC1 0X0E 38 #define TPS65217_REG_DEFDCDC1 0X0E
39 #define TPS65217_REG_DEFDCDC2 0X0F 39 #define TPS65217_REG_DEFDCDC2 0X0F
40 #define TPS65217_REG_DEFDCDC3 0X10 40 #define TPS65217_REG_DEFDCDC3 0X10
41 #define TPS65217_REG_DEFSLEW 0X11 41 #define TPS65217_REG_DEFSLEW 0X11
42 #define TPS65217_REG_DEFLDO1 0X12 42 #define TPS65217_REG_DEFLDO1 0X12
43 #define TPS65217_REG_DEFLDO2 0X13 43 #define TPS65217_REG_DEFLDO2 0X13
44 #define TPS65217_REG_DEFLS1 0X14 44 #define TPS65217_REG_DEFLS1 0X14
45 #define TPS65217_REG_DEFLS2 0X15 45 #define TPS65217_REG_DEFLS2 0X15
46 #define TPS65217_REG_ENABLE 0X16 46 #define TPS65217_REG_ENABLE 0X16
47 #define TPS65217_REG_DEFUVLO 0X18 47 #define TPS65217_REG_DEFUVLO 0X18
48 #define TPS65217_REG_SEQ1 0X19 48 #define TPS65217_REG_SEQ1 0X19
49 #define TPS65217_REG_SEQ2 0X1A 49 #define TPS65217_REG_SEQ2 0X1A
50 #define TPS65217_REG_SEQ3 0X1B 50 #define TPS65217_REG_SEQ3 0X1B
51 #define TPS65217_REG_SEQ4 0X1C 51 #define TPS65217_REG_SEQ4 0X1C
52 #define TPS65217_REG_SEQ5 0X1D 52 #define TPS65217_REG_SEQ5 0X1D
53 #define TPS65217_REG_SEQ6 0X1E 53 #define TPS65217_REG_SEQ6 0X1E
54 54
55 #define TPS65217_REG_MAX TPS652 55 #define TPS65217_REG_MAX TPS65217_REG_SEQ6
56 56
57 /* Register field definitions */ 57 /* Register field definitions */
58 #define TPS65217_CHIPID_CHIP_MASK 0xF0 58 #define TPS65217_CHIPID_CHIP_MASK 0xF0
59 #define TPS65217_CHIPID_REV_MASK 0x0F 59 #define TPS65217_CHIPID_REV_MASK 0x0F
60 60
61 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7) 61 #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
62 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6) 62 #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
63 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5) 63 #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
64 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4) 64 #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
65 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C 65 #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
66 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03 66 #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
67 67
68 #define TPS65217_INT_PBM BIT(6) 68 #define TPS65217_INT_PBM BIT(6)
69 #define TPS65217_INT_ACM BIT(5) 69 #define TPS65217_INT_ACM BIT(5)
70 #define TPS65217_INT_USBM BIT(4) 70 #define TPS65217_INT_USBM BIT(4)
71 #define TPS65217_INT_PBI BIT(2) 71 #define TPS65217_INT_PBI BIT(2)
72 #define TPS65217_INT_ACI BIT(1) 72 #define TPS65217_INT_ACI BIT(1)
73 #define TPS65217_INT_USBI BIT(0) 73 #define TPS65217_INT_USBI BIT(0)
74 #define TPS65217_INT_SHIFT 4 74 #define TPS65217_INT_SHIFT 4
75 #define TPS65217_INT_MASK (TPS65 75 #define TPS65217_INT_MASK (TPS65217_INT_PBM | TPS65217_INT_ACM | \
76 TPS652 76 TPS65217_INT_USBM)
77 77
78 #define TPS65217_CHGCONFIG0_TREG BIT(7) 78 #define TPS65217_CHGCONFIG0_TREG BIT(7)
79 #define TPS65217_CHGCONFIG0_DPPM BIT(6) 79 #define TPS65217_CHGCONFIG0_DPPM BIT(6)
80 #define TPS65217_CHGCONFIG0_TSUSP BIT(5) 80 #define TPS65217_CHGCONFIG0_TSUSP BIT(5)
81 #define TPS65217_CHGCONFIG0_TERMI BIT(4) 81 #define TPS65217_CHGCONFIG0_TERMI BIT(4)
82 #define TPS65217_CHGCONFIG0_ACTIVE BIT(3) 82 #define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
83 #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2) 83 #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
84 #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1) 84 #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
85 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0) 85 #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
86 86
87 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0 87 #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
88 #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5) 88 #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
89 #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4) 89 #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
90 #define TPS65217_CHGCONFIG1_RESET BIT(3) 90 #define TPS65217_CHGCONFIG1_RESET BIT(3)
91 #define TPS65217_CHGCONFIG1_TERM BIT(2) 91 #define TPS65217_CHGCONFIG1_TERM BIT(2)
92 #define TPS65217_CHGCONFIG1_SUSP BIT(1) 92 #define TPS65217_CHGCONFIG1_SUSP BIT(1)
93 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0) 93 #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
94 94
95 #define TPS65217_CHGCONFIG2_DYNTMR BIT(7) 95 #define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
96 #define TPS65217_CHGCONFIG2_VPREGHG BIT(6) 96 #define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
97 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30 97 #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
98 98
99 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0 99 #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
100 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30 100 #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
101 #define TPS65217_CHGCONFIG2_PCHRGT BIT(3) 101 #define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
102 #define TPS65217_CHGCONFIG2_TERMIF 0x06 102 #define TPS65217_CHGCONFIG2_TERMIF 0x06
103 #define TPS65217_CHGCONFIG2_TRANGE BIT(0) 103 #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
104 104
105 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3) 105 #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
106 #define TPS65217_WLEDCTRL1_ISEL BIT(2) 106 #define TPS65217_WLEDCTRL1_ISEL BIT(2)
107 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03 107 #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
108 108
109 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F 109 #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
110 110
111 #define TPS65217_MUXCTRL_MUX_MASK 0x07 111 #define TPS65217_MUXCTRL_MUX_MASK 0x07
112 112
113 #define TPS65217_STATUS_OFF BIT(7) 113 #define TPS65217_STATUS_OFF BIT(7)
114 #define TPS65217_STATUS_ACPWR BIT(3) 114 #define TPS65217_STATUS_ACPWR BIT(3)
115 #define TPS65217_STATUS_USBPWR BIT(2) 115 #define TPS65217_STATUS_USBPWR BIT(2)
116 #define TPS65217_STATUS_PB BIT(0) 116 #define TPS65217_STATUS_PB BIT(0)
117 117
118 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D 118 #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
119 119
120 #define TPS65217_PGOOD_LDO3_PG BIT(6) 120 #define TPS65217_PGOOD_LDO3_PG BIT(6)
121 #define TPS65217_PGOOD_LDO4_PG BIT(5) 121 #define TPS65217_PGOOD_LDO4_PG BIT(5)
122 #define TPS65217_PGOOD_DC1_PG BIT(4) 122 #define TPS65217_PGOOD_DC1_PG BIT(4)
123 #define TPS65217_PGOOD_DC2_PG BIT(3) 123 #define TPS65217_PGOOD_DC2_PG BIT(3)
124 #define TPS65217_PGOOD_DC3_PG BIT(2) 124 #define TPS65217_PGOOD_DC3_PG BIT(2)
125 #define TPS65217_PGOOD_LDO1_PG BIT(1) 125 #define TPS65217_PGOOD_LDO1_PG BIT(1)
126 #define TPS65217_PGOOD_LDO2_PG BIT(0) 126 #define TPS65217_PGOOD_LDO2_PG BIT(0)
127 127
128 #define TPS65217_DEFPG_LDO1PGM BIT(3) 128 #define TPS65217_DEFPG_LDO1PGM BIT(3)
129 #define TPS65217_DEFPG_LDO2PGM BIT(2) 129 #define TPS65217_DEFPG_LDO2PGM BIT(2)
130 #define TPS65217_DEFPG_PGDLY_MASK 0x03 130 #define TPS65217_DEFPG_PGDLY_MASK 0x03
131 131
132 #define TPS65217_DEFDCDCX_XADJX BIT(7) 132 #define TPS65217_DEFDCDCX_XADJX BIT(7)
133 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F 133 #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
134 134
135 #define TPS65217_DEFSLEW_GO BIT(7) 135 #define TPS65217_DEFSLEW_GO BIT(7)
136 #define TPS65217_DEFSLEW_GODSBL BIT(6) 136 #define TPS65217_DEFSLEW_GODSBL BIT(6)
137 #define TPS65217_DEFSLEW_PFM_EN1 BIT(5) 137 #define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
138 #define TPS65217_DEFSLEW_PFM_EN2 BIT(4) 138 #define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
139 #define TPS65217_DEFSLEW_PFM_EN3 BIT(3) 139 #define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
140 #define TPS65217_DEFSLEW_SLEW_MASK 0x07 140 #define TPS65217_DEFSLEW_SLEW_MASK 0x07
141 141
142 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F 142 #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
143 143
144 #define TPS65217_DEFLDO2_TRACK BIT(6) 144 #define TPS65217_DEFLDO2_TRACK BIT(6)
145 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F 145 #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
146 146
147 #define TPS65217_DEFLDO3_LDO3_EN BIT(5) 147 #define TPS65217_DEFLDO3_LDO3_EN BIT(5)
148 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F 148 #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
149 149
150 #define TPS65217_DEFLDO4_LDO4_EN BIT(5) 150 #define TPS65217_DEFLDO4_LDO4_EN BIT(5)
151 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F 151 #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
152 152
153 #define TPS65217_ENABLE_LS1_EN BIT(6) 153 #define TPS65217_ENABLE_LS1_EN BIT(6)
154 #define TPS65217_ENABLE_LS2_EN BIT(5) 154 #define TPS65217_ENABLE_LS2_EN BIT(5)
155 #define TPS65217_ENABLE_DC1_EN BIT(4) 155 #define TPS65217_ENABLE_DC1_EN BIT(4)
156 #define TPS65217_ENABLE_DC2_EN BIT(3) 156 #define TPS65217_ENABLE_DC2_EN BIT(3)
157 #define TPS65217_ENABLE_DC3_EN BIT(2) 157 #define TPS65217_ENABLE_DC3_EN BIT(2)
158 #define TPS65217_ENABLE_LDO1_EN BIT(1) 158 #define TPS65217_ENABLE_LDO1_EN BIT(1)
159 #define TPS65217_ENABLE_LDO2_EN BIT(0) 159 #define TPS65217_ENABLE_LDO2_EN BIT(0)
160 160
161 #define TPS65217_DEFUVLO_UVLOHYS BIT(2) 161 #define TPS65217_DEFUVLO_UVLOHYS BIT(2)
162 #define TPS65217_DEFUVLO_UVLO_MASK 0x03 162 #define TPS65217_DEFUVLO_UVLO_MASK 0x03
163 163
164 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0 164 #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
165 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F 165 #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
166 166
167 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0 167 #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
168 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F 168 #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
169 169
170 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0 170 #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
171 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F 171 #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
172 172
173 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0 173 #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
174 174
175 #define TPS65217_SEQ5_DLY1_MASK 0xC0 175 #define TPS65217_SEQ5_DLY1_MASK 0xC0
176 #define TPS65217_SEQ5_DLY2_MASK 0x30 176 #define TPS65217_SEQ5_DLY2_MASK 0x30
177 #define TPS65217_SEQ5_DLY3_MASK 0x0C 177 #define TPS65217_SEQ5_DLY3_MASK 0x0C
178 #define TPS65217_SEQ5_DLY4_MASK 0x03 178 #define TPS65217_SEQ5_DLY4_MASK 0x03
179 179
180 #define TPS65217_SEQ6_DLY5_MASK 0xC0 180 #define TPS65217_SEQ6_DLY5_MASK 0xC0
181 #define TPS65217_SEQ6_DLY6_MASK 0x30 181 #define TPS65217_SEQ6_DLY6_MASK 0x30
182 #define TPS65217_SEQ6_SEQUP BIT(2) 182 #define TPS65217_SEQ6_SEQUP BIT(2)
183 #define TPS65217_SEQ6_SEQDWN BIT(1) 183 #define TPS65217_SEQ6_SEQDWN BIT(1)
184 #define TPS65217_SEQ6_INSTDWN BIT(0) 184 #define TPS65217_SEQ6_INSTDWN BIT(0)
185 185
186 #define TPS65217_MAX_REGISTER 0x1E 186 #define TPS65217_MAX_REGISTER 0x1E
187 #define TPS65217_PROTECT_NONE 0 187 #define TPS65217_PROTECT_NONE 0
188 #define TPS65217_PROTECT_L1 1 188 #define TPS65217_PROTECT_L1 1
189 #define TPS65217_PROTECT_L2 2 189 #define TPS65217_PROTECT_L2 2
190 190
191 191
192 enum tps65217_regulator_id { 192 enum tps65217_regulator_id {
193 /* DCDC's */ 193 /* DCDC's */
194 TPS65217_DCDC_1, 194 TPS65217_DCDC_1,
195 TPS65217_DCDC_2, 195 TPS65217_DCDC_2,
196 TPS65217_DCDC_3, 196 TPS65217_DCDC_3,
197 /* LDOs */ 197 /* LDOs */
198 TPS65217_LDO_1, 198 TPS65217_LDO_1,
199 TPS65217_LDO_2, 199 TPS65217_LDO_2,
200 TPS65217_LDO_3, 200 TPS65217_LDO_3,
201 TPS65217_LDO_4, 201 TPS65217_LDO_4,
202 }; 202 };
203 203
204 #define TPS65217_MAX_REG_ID TPS652 204 #define TPS65217_MAX_REG_ID TPS65217_LDO_4
205 205
206 /* Number of step-down converters available */ 206 /* Number of step-down converters available */
207 #define TPS65217_NUM_DCDC 3 207 #define TPS65217_NUM_DCDC 3
208 /* Number of LDO voltage regulators available 208 /* Number of LDO voltage regulators available */
209 #define TPS65217_NUM_LDO 4 209 #define TPS65217_NUM_LDO 4
210 /* Number of total regulators available */ 210 /* Number of total regulators available */
211 #define TPS65217_NUM_REGULATOR (TPS65 211 #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
212 212
213 enum tps65217_bl_isel { 213 enum tps65217_bl_isel {
214 TPS65217_BL_ISET1 = 1, 214 TPS65217_BL_ISET1 = 1,
215 TPS65217_BL_ISET2, 215 TPS65217_BL_ISET2,
216 }; 216 };
217 217
218 enum tps65217_bl_fdim { 218 enum tps65217_bl_fdim {
219 TPS65217_BL_FDIM_100HZ, 219 TPS65217_BL_FDIM_100HZ,
220 TPS65217_BL_FDIM_200HZ, 220 TPS65217_BL_FDIM_200HZ,
221 TPS65217_BL_FDIM_500HZ, 221 TPS65217_BL_FDIM_500HZ,
222 TPS65217_BL_FDIM_1000HZ, 222 TPS65217_BL_FDIM_1000HZ,
223 }; 223 };
224 224
225 struct tps65217_bl_pdata { 225 struct tps65217_bl_pdata {
226 enum tps65217_bl_isel isel; 226 enum tps65217_bl_isel isel;
227 enum tps65217_bl_fdim fdim; 227 enum tps65217_bl_fdim fdim;
228 int dft_brightness; 228 int dft_brightness;
229 }; 229 };
230 230
231 /* Interrupt numbers */ 231 /* Interrupt numbers */
232 #define TPS65217_IRQ_USB 0 232 #define TPS65217_IRQ_USB 0
233 #define TPS65217_IRQ_AC 1 233 #define TPS65217_IRQ_AC 1
234 #define TPS65217_IRQ_PB 2 234 #define TPS65217_IRQ_PB 2
235 #define TPS65217_NUM_IRQ 3 235 #define TPS65217_NUM_IRQ 3
236 236
237 /** 237 /**
238 * struct tps65217_board - packages regulator 238 * struct tps65217_board - packages regulator init data
239 * @tps65217_regulator_data: regulator initial 239 * @tps65217_regulator_data: regulator initialization values
240 * 240 *
241 * Board data may be used to initialize regula 241 * Board data may be used to initialize regulator.
242 */ 242 */
243 struct tps65217_board { 243 struct tps65217_board {
244 struct regulator_init_data *tps65217_i 244 struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
245 struct device_node *of_node[TPS65217_N 245 struct device_node *of_node[TPS65217_NUM_REGULATOR];
246 struct tps65217_bl_pdata *bl_pdata; 246 struct tps65217_bl_pdata *bl_pdata;
247 }; 247 };
248 248
249 /** 249 /**
250 * struct tps65217 - tps65217 sub-driver chip 250 * struct tps65217 - tps65217 sub-driver chip access routines
251 * 251 *
252 * Device data may be used to access the TPS65 252 * Device data may be used to access the TPS65217 chip
253 */ 253 */
254 254
255 struct tps65217 { 255 struct tps65217 {
256 struct device *dev; 256 struct device *dev;
257 struct tps65217_board *pdata; 257 struct tps65217_board *pdata;
258 struct regulator_desc desc[TPS65217_NU 258 struct regulator_desc desc[TPS65217_NUM_REGULATOR];
259 struct regmap *regmap; 259 struct regmap *regmap;
260 u8 *strobes; 260 u8 *strobes;
261 struct irq_domain *irq_domain; 261 struct irq_domain *irq_domain;
262 struct mutex irq_lock; 262 struct mutex irq_lock;
263 u8 irq_mask; 263 u8 irq_mask;
264 int irq; 264 int irq;
265 }; 265 };
266 266
267 static inline struct tps65217 *dev_to_tps65217 267 static inline struct tps65217 *dev_to_tps65217(struct device *dev)
268 { 268 {
269 return dev_get_drvdata(dev); 269 return dev_get_drvdata(dev);
270 } 270 }
271 271
272 int tps65217_reg_read(struct tps65217 *tps, un 272 int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
273 unsign 273 unsigned int *val);
274 int tps65217_reg_write(struct tps65217 *tps, u 274 int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
275 unsigned int val, unsi 275 unsigned int val, unsigned int level);
276 int tps65217_set_bits(struct tps65217 *tps, un 276 int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
277 unsigned int mask, unsigned in 277 unsigned int mask, unsigned int val, unsigned int level);
278 int tps65217_clear_bits(struct tps65217 *tps, 278 int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
279 unsigned int mask, unsigned in 279 unsigned int mask, unsigned int level);
280 280
281 #endif /* __LINUX_MFD_TPS65217_H */ 281 #endif /* __LINUX_MFD_TPS65217_H */
282 282
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